Status of the electronics systems
of the MEG experiment
PSI - Jan. 15th, 2006
1
HV system
• External HV power supply
• Control and regulation
through MSCB
• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector
4 different requirements:
–
–
–
–
PSI - Jan. 15th, 2006
Lxe: 1000V , 100 uA
TC bars: 2400V, 1 mA
TC curved: 500V, <1 uA
DC: 2400V, ~1 uA
50 channels successfully
tested on the LP for a
couple of months
1000 channels for LXe, TC and
DC in production
2
Ready by June ‘06
Splitter boards
• Studies on the cross-talk on twisted
cables suggested better insulation among
the full-bandwidth output for DRS
• High bandwidth output layout was changed
for new connector from JAE
• Cross-talk expected ~< 1%
trigger/DRS
Input
DRS
trigger
PSI - Jan. 15th, 2006
Power
3
Splitter backplane layout
The DRS calibration circuit has been
included on the backplane
It provides programmable DC levels on all
the splitter outputs (0.-2. V at 1mV
resolution)
Control through MSCB
A special calibration signal is provided by
the trigger system
PSI - Jan. 15th, 2006
Example of a
calibration pattern
4
Splitter orders status
•
Parts all ordered, many arrived:
– Cables
•
•
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•
Input cables + carriers: partially delivered
Output 34p tw 2.54 pitch cables + connectors (trigger): delivered
Output 10p tw 2.54 pitch cables + connectors (sum) : delivered
Output 68p tw 1.27 pitch cables + connectors (DRS) : ordered
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•
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•
9U Crates with accessories: ordered
Fans: delivered
Power supply: ordered
Backplane printed circuit: ordered
Backplane connectors: delivered
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Printed circuit: ordered
Card components: ordered
Front panels: ordered
Mechanical accessories: delivered
– Crates
– Cards
•
Installation expected in May ‘06
PSI - Jan. 15th, 2006
5
TC discriminator cards
Timing measurement
• Eurocard 6U height
• 8 boards
• Hosted in the splitter
crate
B
to Splitter
Analog signals
to DRS and trigger
PMT
S
B
TC Analog Sign. Monitor
Passive
Splitter
Prototype under test at
Frascati
Delivery in May
Installation in June
D/D
RAMP
GEN.
to Splitters
Signals to DRS
Dual Threshold
Discriminator
PSI - Jan. 15th, 2006
NIM Signal
6
for any possible use
TC fibers
8 Ch APD F.E. Card
TC mezzanine board
Output for
the trigger
system
APD F.E. card:
•
•
•
•
•
•
Concentrator Card
Front-end prototype for APD under test
Final prototypes construction will start by 15th of
february
Final production: 3 weeks after acceptance.
Delivery expected in May
Same schedule for concentrator cards and mezzanine for
VME-VPC board.
FPGA CODE (V1.01) ready. Soon will start the evaluation
process that will take 1 months
PSI - Jan. 15th, 2006
PSI GPVME board
7
2 boards
14 boards
LXe front face
(216 PMTs)
16
Type1
Type1
Type1
14 x 48
Type2
4
2 x 48
Type2
LXe lateral faces
back (216 PMTs) 4 in 1 16
lat. (144x2 PMTs) 4 in 1
up/down (54x2 PMTs) 4 in 1 4
5+5+2 boards
Type1
Type1
Type1
Trigger
system
structure
1 board
9 x 48
2 x 48
Type2
Type2
Timing counters
curved (640 APDs) 8 in 1
u/d stream (30x2 PMTs)
1 board
9 boards
16
Type1
Type1
Type1
9 x 48
1 x 48
4
Type2
1 board
2 boards
Drift chambers
16+16 channels
16
Type1
Type1
16
2 x 48
4
Auxiliary devices
16 channels
16
Type1
4
PSI - Jan. 15th, 2006
1 x 48
8
Type1
Type2
PSI - Jan. 15th, 2006
9
Short summary
• Test of the board Type1  completed
• Test of the board Type2  completed
• System test  completed
• Corrections and improvements
• One missing connection per board
• Control of the power up procedure
• Increased the read-out speed (~50 events/s)
•
•
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•
Final PCB production in progress delivery confirmed for Feb. 10th ’06
Board mounting assigned company waiting for PCB
Crates 6U (PSI), crate 9U (CAEN), interfaces ordered
On-line PC (DAQ model) waiting
Two test station are ready
Firmware design in progress strongly dependent on PMT cabling
Installation at PSI, together with the DAQ june ’06
PSI - Jan. 15th, 2006
10
Auxiliary digitization
We consider useful exploiting the trigger FADC as
auxiliary digitazing system
100MHz, 10 bits, 5 s depth, no fanin
Two options are considered
Modified Type1 boards from 16 to 32 channels
Requires manpower…
Use of the Type1 boards as they are, without mounting
part of the components
Requires 2 crates…
both solutions have the same cost
PSI - Jan. 15th, 2006
11
DRS2 - new CMC card
• Better analog design (lower crosstalk
and noise
• Moved chips more to front
• Dedicated clock input
• Dual FADC
• Temperature sensor
• 1k EEPROM
128 DRS2 channels ready
Noise level with
the new CMC
PSI - Jan. 15th, 2006
12
DRS2 - Clock “nonlinearity”
0.2-1 ns
Inverter (“Domino”) chain
Rotating
signal
Input 1
Output 1
30ns
Input 2
Output 2
Channels
3ns
to 10
40 MHz
PSI - Jan. 15th, 2006
bin
13
DRS2 – cell self-heating
~1mA
Vin
“Differential
Pair”
R
Vout
read
Vin
Vout
write
...
write
C
I = c1 * Vin + c2 * Vin * kT
C
Ib/2
Ib/2
Ib
•
•
•
•
Current depends on “history” of cell
Quadratic effect
Small below input voltage of 0.5V
Solution: OTA readout
PSI - Jan. 15th, 2006
+
-
14
DRS2 - ghost pulses
0.2-1 ns
Rotating
signal
Inverter (“Domino”) chain
Input 1
Output 1
signal
Input 2
after one turn
Output 2
Channels
3 to 10
after two turns
2%
PSI - Jan. 15th, 2006
40 MHz
>0.5%
15
DRS2 vs DRS3
Issue
Solution
Voltage nonlinearity
Calibration with cubic splines in Front-end

Clock nonlinearity
Time calibration & frequency regulation

Cross talk
1% @ 7ns risetime
Redesign of CMC card with ERNI 68-pin
connector and interleaved ground lines

Temperature
dependence
- Calibration maybe possible to some extend
- Keep electronics temperature constant
- On-chip temperature compensation
?
()
- Only use small signals (<0.5 V)
- On-chip temperature compensation
()
Self-heating of cells
Ghost pulses
PSI - Jan. 15th, 2006
- Veto trigger ~5us after cosmic or LED event
- Veto trigger after other calorimeter hits?
- Record 2us calorimeter history in each event?
- Redesign sampling cell
DRS2
DRS3



?
?

16
DRS short summary
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DRS2 available for all experiment channels: LXe, TC and DC
DRS2 installation foreseen in june 2006
Design of the DRS3 started (with the help of a new engineering )
Solutions for the DRS2 problems were identified
Replacement of part or all DRS2 with DRS3 expected during
2007 beam shutdown
PSI - Jan. 15th, 2006
17
DAQ
•
•
•
•
Readout speed
Struck SIS3100
VPC board with CMC
2eVME transfer protocol
Desktop PC (2.6 GHz P4)
T = 125us + size/84 MB/sec
25 ms/event at full readout
VME Speed
DAQ computers
80
70
60
MB/sec
Producer: www.thomas-krenn.com
Cost: 1800 €
• Hot–plug cooler
• Redundant power supply
• Hot swap hard disks
• Remote management card
90
50
40
30
20
10
0
PSI - Jan. 15th, 2006
1
10
100
1000
10000
Buffer size [Bytes]
100000
1000000 1000000
18
0
Slow Control System - 2000
Based on Midas Slow Control Bus
Evolution of the SCS 1000
Slow control of all MEG equipments
• 8 banks @ 8 In- or Outputs → 64 I/O
• Each bank may contain
– Output: 5V, 24V, 4-20mA, ±10V, LED pulser
– Input: 5V, 24V, 4-20mA, ±10V, comparator
• Outputs stable during CPU software upgrade and
reboot
• CPLD can be used for hard-wired logic
→ control operation w/o CPU
PSI - Jan. 15th, 2006
19
Conclusions of the last BVR
• An electronics integration scheme has been
developed
• Minor details needs to be fixed – done!
• All key electronics elements will be available
before March 06 moved to June 06
• A test of the final electronics systems, together
with crates, in magnetic field environment is
planned in autumn done!
PSI - Jan. 15th, 2006
20
Electronic chain
HV
front PMT
216
Active
Splitter
1:1
1:1
4:1
lateral PMT
612
Active
Splitter
1:1
1:1
4:1
Active
Splitter
1:1
1:1
4:1
LXe
HV
60
bars PMT
TC
Ramp
Pre-Amp
DRS
DRS
DRS
DRS
DRS
DRS
8:1
640
HV
Wires
Pre-Amp
Strips
Pre-Amp
PSI - Jan. 15th, 2006
Trigger
Trigger
Trigger
3 crates
HV
fibers APD
DC
120
atten
6 crates
32
576
1156
Aux. devices
Hit
registers
4 boards
21
DAQ and control
pE5 area
‘counting room’
Trigger
clock
start
stop
sync
Ancillary
system
Trigger
Trigger
Trigger
3 crates
Busy
Error
Run start
Run stop
Trigger config
DRS
DRS
DRS
DRS
DRS
DRS
20 MHz
clock
Hit
registers
6 crates
PSI - Jan. 15th, 2006
Front-End PCs
Main DAQ PC
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Gigabit
Ethernet
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Trigger signal
Event number
Trigger type
storage
Event
builder
On-line farm
22
Rack space
RACK 1
HV
Splitter
supply
Splitter
supply
Splitter
supply
Splitter
supply
Splitter
supply
Splitter
supply
HV Supply
RACK 2
Trigger
Trigger
Type1
#1
HV Supply
HV distrib
TC
#6
Splitter
RACK 4
DRS Lxe
RACK 5
DRS TC
DRS
LXe
#1
DRS
DC
#3
RACK 6
free
RACK 7
HV LXe
RACK 8
HV LXe
Slow
Control Lxe
Slow
Control DC
Splitter
HV Supply
DRS
Lxe+TC
#2
Trigger
Type2
#3
HV distrib
DC
#7
HV Supply
RACK 3
Splitter
DRS
DC + TC
#4
HV distrib
LXe
#3
HV Supply
Splitter
Extra
Trigger
boards
Trigger
Type1
#2
PSI - Jan. 15th, 2006
DRS
DC
#5
Splitter
Splitter
supply
Splitter
supply
HV distrib
LXe
#4
HV distrib
LXe
#2
HV distrib
LXe
#5
HV distrib
LXe
#1
23