 Standard ICs – ICs sold as Standard Parts
 SSI/LSI/ MSI IC such as MUX, Encoder, Memory
Chips, or Microprocessor IC
 Application Specific Integrated Circuits (ASIC) –
 An IC Customized to a Particular System
or Application –Custom ICs
 Reduced Cost and Improved Reliability
Example. :A Chip for Toy Bear, Auto-Mobile Control
Chip, Different Communication Chips
 Application Specific Standard Parts (ASSP) –
Controller, Chip for PC or a Modem
2
 Full-Custom Ics
Fixed ASICs and
Programmable ASICs
3
Types of ASICs – Cont’d
4
Full-Custom ASICs:
Possibly all logic cells and all mask layers customized
Semi-Custom ASICs:
All logic cells are pre-designed and some (possibly all)
mask layers customized
Full custom
VLSI design
ASICs
Speed / Density /
Complexity / Likely
Market Volume
CPLDs
FPGAs
PLDs
Engineering cost / Time to develop
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist or
 Existing library cells are not fast enough or
 The available pre-designed/pre-tested cells consume too
much power that a design can allow or
 The available logic cells are not compact enough to fit or
 ASIC technology is new or/and so special that no cell
library exits.
7
Offer highest performance and lowest cost
(smallest die size) but at the expense of
increased design time, complexity, higher
design cost and higher risk.
 Some Examples:
High-Voltage Automobile Control Chips.
Ana-Digi Communication Chips,
Sensors and Actuators
Semi-Custom ASICs
1. Standard-Cell based ASICs (CBIC- “sea-bick”)
 Use logic blocks from standard cell libraries, other
mega-cells, full-custom blocks, system-level macros
(SLMs), functional standard blocks (FSBs), cores etc.
 Get all mask layers customized- transistors and
interconnect
9
Manufacturing lead time is around 8 weeks
Less efficient in size and performance but lower in
design cost
 Semi-Custom ASICs – Cont’d
2. Gate Array based ASICs
In a gate-array-based ASIC, the transistors are
predefined on the silicon wafer
The predefined pattern of transistors is called the
base array
The smallest element that is
replicated to make the base array
is called the base or primitive cell
11
Design is performed by connecting predesigned
and characterized logic cells from a library (macros)
After validation, automatic placement and routing
are typically used to convert the macro-based
design into a layout on the ASIC using primitive
cells
Types of MGAs:
1. Channeled Gate Array
2. Channelless Gate Array
3. Structured Gate Array


Only the interconnect is
customized

The interconnect uses
predefined spaces
between rows of base
cells

Manufacturing lead time
is between two days and
two weeks
Figure: Channel
gate-array die


There are no predefined areas
set aside for routing - routing
is over the top of the gatearray devices

Achievable logic density is
higher than for channeled gate
arrays

Manufacturing lead time is
between two days and two
weeks
Figure 1.6 Sea-Of-Gates
(SOG) array die



Only the interconnect is
customized
Custom blocks (the same for
each design) can be
embedded
These can be complete blocks
such as a processor or memory
array, or
 An array of different base cells
better suited to implementing a
specific function


Manufacturing lead time is
between two days and two
weeks.
Figure : Gate array die
with embedded block

Semi-Custom ASICs – Cont’d
3. Programmable ASICs
 PLDs - PLDs are low-density devices which contain
1k – 10 k gates and are available both in bipolar and
CMOS technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs - FPGAs combine
architecture of gate arrays with programmability of
PLDs.
User Configurable
 Contain Regular Structures - circuit elements such
as AND, OR, NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming Technologies
 Allow both Matrix and Row-based Architectures
16
Comparison
Var.
Fixed height
Fixed
Fixed
Var.
Var.
Fixed
Programmable
Var.
In row
Fixed
Fixed
Var.
Var.
Var.
Programmable
High
Medium
Medium
low
17
Comparison
Compact
Compact to
moderate
Moderate
Large
High
High to
moderate
Moderate
Low
All layers
All layers
Routing
layers only
No layers
18
1. Design entry - Using a hardware
description language ( HDL ) or
schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide a
large system into ASIC-sized
pieces
4. Prelayout simulation - Check to
see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the connections
between cells and blocks
8. Extraction - Determine the
resistance and capacitance of
the interconnect
9. Postlayout simulation - Check
to see the design still works with
the added loads of the
interconnect
Figure 1 ASIC design flow
• Digital designer has various options:
SSI (small scale integrated circuits) or
 MSI (medium scale integrated circuits) components
Difficulties arises as design size
increases
Interconnections grow with complexity
resulting in a prolonged testing phase
Programmable Logic Devices (PLD)
It is General purpose chip for implementing
circuits.
Can be customized using programmable
switches.
In programmable logic device (PLD) design,
we use a computer aided design (CAD) software tool to
perform “design entry.”
We can also use the same package for “design verification”
Same can be used to “download” the “design program” into
hardware (i.e. the PLD).
Example
Our design now becomes:
+5V
A
B
C
Y
0
1
2
3
4
1
2
3
4
a1
Vcc1
b1
a2
b2
a3
b3
a4
b4
a1
EPM7032
b1
a2
b2
a3
b3
a4
GND
0
b4
5
6
7
8
5
6
7
8
This single chip design requires
Less power,
less board space,
should cost less on a per gate basis,
easier to debug (in software),
and be easier to manufacture.
Also, Intellectual Property (IP) can be
protected and exploited using a FPLD.
1. Increased system performance (Speed)
•
•
•
This is due to the reduced interconnect distances between gates.
In a TTL design we have large RC delays as we propagate signals
from one chip to another.
In PLD designs, this distances are in the µm range.
A
B
C
0
1
2
Large Delay on this net
+5V
3
4
1
2
3
4
a1
Vcc1
0
b1
a2
b2
a3
b3
a4
b4
a1
74HC04
b1
a2
b2
a3
b3
a4
GND
0
b4
5
1
6
2
7
3
8
4
5
1
6
2
7
3
8
4
a1
Vcc1
0
b1
a2
b2
a3
b3
a4
b4
a1
74HC08
b1
a2
b2
a3
b3
a4
GND
0
b4
5
1
6
2
7
3
8
4
5
1
6
2
7
3
8
4
a1
Vcc1
b1
a2
b2
a3
b3
a4
b4
a1
74HC32
b1
a2
b2
a3
b3
a4
GND
b4
5
6
7
8
5
6
7
8
0
Y
FPLD Design
The same net
is now internal
to the FPLD
A
B
C
Y
+5V
0
1
2
3
4
1
2
3
4
a1
Vcc1
b1
a2
b2
a3
b3
a4
b4
a1
EPM7032
b1
a2
b2
a3
b3
a4
GND
0
b4
5
6
7
8
5
6
7
8
2. Increased Gate Density
More logic gates on each PLD implies that you can
have more functionality per unit area of board
space. A single PLDs/FPGAs can hold the
equivalent of over 1 million TTL logic gates.
3. Reduced Development Time
CAD tools significantly reduce the development time
for new designs. This not only cuts down the “time
to market,” but also allows reduces the size of the
team needed to complete a design.
4. Rapid Hardware Prototyping
Hardware prototyping is greatly simplified using PLDs
because it is relatively easy to change the design. One
major concern however is I/O pin assignments.
5. Reduced “Time to Market”
Since PLDs are already “complete,” there is no need to
wait for fabrication.
6. Future Modifications
Since PLDs can be “reconfigured” in the field. It
is possible to have the end user perform system
“upgrades.”
7. Reduced Development Costs
The development costs for FPLDs tend to be
lower than Application Specific Integrated
Circuits (ASICs); however, the per unit cost of a
FPLD is higher than an ASIC for large volumes.
1. Unlike a Microprocessor, a PLD implements real
logic gates
2. PLDs can operate very fast
3. PLDs can do more than one thing at a time –
a single micro can only pretend to do more than
one thing at a time
– Main types of PLDs
PLA
PAL
ROM
CPLD
FPGA
INPUT
Fixed AND plane
(decoder)
Programmable
Connections
Programmable
OR plane
OUTPUT
(Programmable) Read-Only Memory (ROM)
INPUT
Programmable
AND plane
Programmable
Connections
Programmable
OR plane
OUTPUT
Programmable Logic Array (PLA)
INPUT
Programmable
AND plane
Fixed
OR plane
F/F
OUTPUT
Programmable Array Logic (PAL) Devices
1) PLA — a Programmable Logic Array (PLA) is a
relatively small FPD that contains two levels of
logic, an AND-plane and an OR-plane, where both
levels are programmable
2) PAL — a Programmable Array Logic (PAL) is a
relatively small FPD that has a programmable
AND-plane followed by a fixed OR-plane
3) SPLD — refers to any type of Simple PLD,
usually either a PLA or PAL
4) CPLD — a more Complex PLD that consists of
an arrangement of multiple SPLD-like blocks on a
single chip.
5) FPGA — a Field-Programmable Gate Array is
an FPD featuring a general structure that allows
very high logic capacity.
• PLD as a Black Box
Inputs
(logic variables)
Logic gates
and
programmable
switches
Outputs
(logic functions)
x1 x2
xn
– Use to implement
circuits in SOP form
– The connections in
the AND plane are
programmable
Input buffers
and
inverters
x1 x1
xn xn
P1
– The connections in
the OR plane are
programmable
AND plane
OR plane
Pk
f1
fm
Programmable AND Plane Programmable OR Plane
Programmable Node
Un-programmed
Connect
Disconnect
X
O1
Y
O3
O4
XY
XY
X
Y
X X Y Y
O2
XY
XY
3-36
Programmable AND Plane
Programmable OR Plane
YZ
XZ
XYZ
XY
X
Y
Z
?
XY+YZ
?
XZ+XYZ
3-37
• Gate Level Version of PLA
x1
x2
x3
Programmable
connections
f1 = x1x2+x1x3'+x1'x2'x3
OR plane
P1
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
P4
AND plane
f1
f2
• Customary Schematic of a PLA
x1
x2
x3
OR plane
f1 = x1x2+x1x3'+x1'x2'x3
P1
f2 = x1x2+x1'x2'x3+x1x3
P2
P3
x marks the
connections left in
place after
programming
P4
AND plane
f1
f2
– Also used to implement
circuits in SOP form
– The connections in
the AND plane are
programmable
x1 x2
Input buffers
and
inverters
x1 x1
– The connections in
the OR plane are
NOT programmable
xn
fixed
connections
xn xn
P1
AND plane
OR plane
Pk
f1
fm
Programmable AND Plane
X
Y
Fix OR Plane
O1
O2
O3
O4
3-42
• Example Schematic of a PAL
x1
x2
x3
f1 = x1x2x3'+x1'x2x3
P1
f2 = x1'x2'+x1x2x3
f1
P2
P3
f2
P4
AND plane
• Multi-Level Design with PALs
– f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag'
• where g = BC + B'C' and C = h below
A
B
Sel = 0
En = 0
0
h
1
D Q
Sel = 0
Clock
0
1
En = 1
g
D Q
Select
Clock
0
1
D Q
Clock
f
PLAs are more flexible than PALs since both AND & OR planes
are programmable in PLAs.
PLAs are expensive to fabricate and have large propagation
delay.
Logic expanders increase the flexibilities of PALs, but
result in significant propagation delay.
By using fix OR gates, PALs are cheaper and faster than PLAs.
PLAs and PALs are usually referred to as SPLD.
PALs usually contain D flip-flops connected to the outputs
of OR gates to implement sequential circuits.
3-45
– A ROM (Read Only Memory) has a fixed AND
plane and a programmable OR plane
– Size of AND plane is 2n where n = number of input
pins
• Has an AND gate for every possible minterm so
that all input combinations access a different
AND gate
– OR plane dictates function mapped by the ROM
a0
a1
2 -to-4 decoder
– 22x4 bit ROM has 4 addresses that are decoded
d3
d2
d1
d0
• “Permanent” binary information is stored
• Non-volatile memory
– Power off does not erase information stored
K-bit address
lines
K
ROM
2k words
N-bit per work
N-bit Data Output
N
5
A4
A3
5-to-32
32x8 ROM
8
Each
represents
32 wires
0
1
2
3
A2
Decoder
A1
A0
Fuse can be
implemented as
a diode or a
pass transistor
28
29
30
31
D7
D6
D5
D4
D3
D2
D1
D0
– PLAs, PALs, and ROMs are also called SPLDs –
Simple Programmable Logic Devices
– SPLDs must be programmed so that the switches
are in the correct places
• CAD tools are usually used to do this
– A fuse map is created by the CAD tool and then that map
is downloaded to the device via a special programming unit
• There are two basic types of programming techniques
– Removable sockets on a PCB
– In system programming (ISP) on a PCB
» This approach is not very common for PLAs and PALs
but it is quite common for more complex PLDs
– The SPLD is removed from the PCB, placed into
the unit and programmed there
• Removable SPLD Socket Package
– PLCC (plastic-leaded chip carrier)
PLCC socket
soldered to the PCB
d
oar
P
ted
rin
c
b
uit
c
r
i
• In System Programming (ISP)
– Used when the SPLD cannot be removed from the
PCB
– A special cable and PCB connection are required
to program the SPLD from an attached computer
– Very common approach to programming more
complex PLDs like CPLDs, FPGAs, etc.
• Macrocell
Select
OR gate from
PAL
0
1
D Q
Flip-flop
Clock
back to AND plane
Enable
f1
• Macrocell Functions
– Enable = 0 can be used to allow the output pin for
f1 to be used as an additional input pin to the PAL
– Enable = 1, Select = 0 is normal
for typical PAL operation
Select
0
– Enable = Select = 1 allows
the PAL to synchronize the
output changes with a clock
pulse
1
D Q
Clock
back to AND plane
– The feedback to the AND plane provides for multilevel design
Enable
f1
FPGA technology allows you to embed a
processor, ROM, RAM, DSP, and any other
block onto a single chip
This has major advantages for electronics
companies in terms of cost, reliability,
reusability of intellectual property, and time to
market
– Complex Programmable Logic Devices
(CPLD)
– SPLDs (PLA, PAL) are limited in size due to the
small number of input and output pins and the
limited number of product terms
• Combined number of inputs + outputs < 32
– CPLDs contain multiple circuit blocks on a single
chip
Each block is like a PAL: PAL-like block
Connections are provided between PAL-like
blocks via an interconnection network that is
programmable
Each block is connected to an I/O block as well
I/O block
PAL-like
block
I/O block
PAL-like
block
PAL-like
block
PAL-like
block
I/O block
I/O block
Interconnection wires
A collection of PLDs on a single chip with
Programmable interconnects
• Internal Structure of a PAL-like Block
– Includes macrocells: Usually about 16 each
– Fixed OR planes :OR gates have fan-in between 5-20
PAL-like block
PAL-like block
D Q
D Q
D Q
• PAL-like Blocks
– When tri-state gate is disabled, the corresponding
output pin can be used as an input pin
– The AND plane and interconnection network are
programmable
– Commercial CPLDs have between 2-100 PAL-like
blocks
• Programming a CPLD
– CPLDs have many pins – large ones have > 200
• Removal of CPLD from a PCB is difficult
without breaking the pins
• Use ISP (in system programming) to program
the CPLD
• JTAG (Joint Test Action Group) port used to
connect the CPLD to a computer
Manufacturer
Altera
Altmel
Cypress
Lattice
Philips
Vantis
Xilinx
CPLD Products
MAX 5000, 7000 & 9000
ATF & ATV
FLASH370, Ultra37000
ispLSI 1000 to 8000
XPLA
MACH 1 to 5
XC9500
Let’s takes a look at this
URL
www.altera.com
www.atmel.com
www.cypress.com
www.latticesemi.com
www.philips.com
www.vantis.com
www.xilinx.com
Features:
• The internal PLDs are called Configurable Functional Blocks
(FBs or CFBs)
• Each FB has 36 inputs and 18 Macrocells (effectively a
“36V18”)
• Each CLPD is packaged in a plastic-leaded chip carrier
(PLCC)
• The number of I/O pins are much less than the total number of
Macrocells in family of devices
36 Signal pins
18 outputs
Global Clock
Global set/reset
Global 3 state control
18 Output
enable signals
Figure: Function block
•
Each Function Block, comprised of18 independent
macrocells, each capable of implementing a
combinatorial or registered function.
•
The FB generates 18 outputs that drive the Fast
CONNECT switch matrix.
•
These 18 outputs and their corresponding output
enable signals also drive the IOB.
•Logic within the FB is implemented using a sum-ofproducts representation.
•Thirty-six inputs provide 72 true and complement
signals into the programmable AND-array to form 90
product terms.
•Any number of these product terms, up to the 90
available, can be allocated to each macrocell by the
product term allocator.
Each XC9500 macrocell may be individually configured for
a combinatorial or registered function.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates)
to implement combinatorial functions, or as control inputs
including clock, set/reset, and output enable.
The product term allocator associated with each
macrocell selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation.
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable
signals.
XC9500 Product
term allocator and
macrocell
The product term allocator controls how the five direct
product terms are assigned to each macrocell.
The product term allocator can re-assign other product
terms within the FB to increase the logic capacity of a
macrocell beyond five direct terms.
Up to 15 product terms can be available to a single
macrocell
The Fast CONNECT switch matrix connects signals to the
FB inputs,
All IOB outputs (corresponding to user pin inputs) and all
FB outputs drive the Fast CONNECT matrix.
Any of these (up to a FB fan-in limit of 36) may be selected,
through user programming, to drive each FB with a uniform
delay.
The Fast CONNECT switch matrix is capable of combining
multiple internal connections into a single wired-AND output
before driving the destination FB
XC9500 I/O Block
The I/O Block (IOB) interfaces between the internal logic
and the device user I/O pins.
Each IOB includes an input buffer, output driver, output
enable selection multiplexer, and user programmable
ground control.
The input buffer is compatible with standard 5V CMOS,
5V TTL, and 3.3V signal levels.
The input buffer uses the internal 5V voltage supply
(VCCINT) to ensure that the input thresholds are constant
and do not vary with the VCCIO voltage.
Features:
 Specifically designed to meet the needs of high volume,
 Cost-sensitive consumer electronic applications
 Spartan 3 family offers densities ranging from 50,000 to
five million system gates,
 FPGA can handle larger circuits
 No AND/OR planes
 Provide logic blocks, I/O blocks, and interconnection wires
and switches.
 Logic blocks provide functionality Interconnection switches
that allow logic blocks to be connected to each other and to
the I/O pins
FPGA programmable logic blocks have only a few
inputs and 1 or 2 flip-flops, but there are a lot more
of them compared to the number of macrocells in a
CPLD.
FPGAs are all 3.3V to reduce power consumption.
FPGAs are only available in SMT which is very
inconvenient.
FPGA’s need reprogramming each time they are
powered up by a slave processor or serial memory.
• Before powering on or off the FPGA,
configuration data is stored externally in a
PROM or some other nonvolatile medium
• After applying power, the configuration data is
written to the FPGA using any of five different
modes:
•
•
•
•
•
Master Parallel,
Slave Parallel,
Master Serial,
Slave Serial, and
Boundary Scan (JTAG).
CLB --“configurable logic block”
I/O block
logic block
I/O block
I/O block
interconnection
switch
I/O block
• Configurable Logic Blocks (CLBs) contain
 RAM-based Look-Up Tables (LUTs) to implement
logic, and
 storage elements that can be used as flip-flops or
latches.
 CLBs can be programmed to perform a wide
variety of logical functions as well as to store data.
CLB function generators (F, G, H)
• Use RAM to store a truth table
– F, G: 4 inputs, 16 bits of RAM each
– H: 3 inputs, 8 bits of RAM
– RAM is loaded from an external PROM at system
initialization.
Number of RAM Blocks by Device
• LUTs
– Logic blocks are implemented using a lookup table
(LUT)
• Small number of inputs, one output Contains
storage cells that can be loaded with the
desired values
• A 2 input LUT uses 3 MUXes to implement any
desired function of 2 variables
x1
0/1
0/1
0/1
0/1
x2
f
• Example: 2 Input LUT for XNOR
x1
0
0
1
1
x2
0
1
0
1
f
1
0
0
1
f = x1'x2' + x1x2, or using Shannon's
expansion:
f = x1'(x2') + x1(x2)
= x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))
x1
1
0
0
1
x2
f
•
•
•
•
•
Two flip-flops per CLB,
Two flip-flops per I/O cell.
25 “gates” per CLB if used for logic.
32 bits of RAM per CLB if not used for logic.
All of this is valid only if your design has a
“perfect fit”.
connections
controlled by
RAM bits
programmable switch element
turning the corner, etc.
• Input/Output Blocks (IOBs) control the
flow of data between the I/O pins and
the internal logic of the device.
• Each IOB supports bidirectional data
flow plus tri-state operation
• Field programmability is achieved through
switches (Transistors controlled by memory
elements or fuses)
• Switches control the following aspects
• Interconnection among wire segments
• Configuration of logic blocks
• Distributed memory elements controlling the
switches and configuration of logic blocks are
together called “Configuration Memory”
PEs are used to physically “program” the interconnects.
B
A
Vgate
Field Effect Transistor (FET)
FET acts like a “switch”
If Vgate is ONE, switch
is closed, connecting A
and B otherwise A and
B are isolated.
Example
B
B
Closed
A
Open
A
ONE
Vgate=One
Switch Closed
Open
Ckt
Vgate=Zero
Switch Open
So, we’ll have one FET at every programmable
Interconnect, but we need a method or technique
to “program” VGATE to be ONE or ZERO.
Before, we look at our options, some definitions
Two Types:
1. Volatile
“Program” is lost when power is removed
2. Non-volatile
“Program” is retained with power is removed.
Two Classes:
1. Re-programmable
PE can be “erased” and “re-programmed”
2. One-time-programmable (OTP)
PE can only be programmed “one” time.
(not really used anymore)
EPROM – Erasable Programmable Read Only Memory
Reprogrammable and non-volatile
It is possible to physically program an EPROM cell to
always be ONE when power is applied. Also, we can
use ultraviolet (UV) light to reset or “erase” the EPROM
cell back to ZERO.
B
A
UV
To erase
EPROM
Cell
We can, therefore, erase all the cells of the EPROM
and then program the PEs that we want to be ONEs.
EEPROM – (E2PROM)
Electrically Erasable Programmable Read Only Memory
Reprogrammable and non-volatile
Similar to an EPROM except cell can be “erased”
electrically.
 Two gates: Floating and Select
 Functionally equivalent to EPROM; only
Construction and structure is different
 Electrically Erasable: Re-programmable by
applying high voltage

(No UV radiation expose!)
 When un-programmed, the threshold (as
seen by select gate) is negative!
SRAM
Static Random Access Memory
Volatile and Reprogrammable (electrically)
SRAM
Cell
To Vgate
Store the value of VGATE within a SRAM cell. We lose
the program whenever the power is removed. Therefore,
we’ll need the ability to “reload” the design upon power-up.
Write 0
Write 1
BL
BL
1
0
1
WL
1
0
To
VGATE
0
0
1
WL
1
WL=1, turns “ON” FET, connecting BL to the cell
To
VGATE
1
Read
BL
X
data
data
To
VGATE
data
WL
0
WL=0, turns “OFF” FET, isolating data from the cell.
However, Due to “positive” feedback, data is
retained in the memory cell until power is removed
B
A
SRAM
Cell
Use a SRAM cell to store VGATE. Lose “program” when
power is removed.
antifuse polysilicon
ONO dielectric
n+ antifuse diffusion
2l
Open by default, closed by applying current pulse
Anti-Fuse
Non-volatile and OTP
Normally, anti-fuse behaves like an “open”
circuit, however you can “destroy” the fuse
electrically so that it behaves like a short circuit.
B
Anti-fuse
.
A
The antifuse is very
small compared to the
other PEs.
• Though implementation differ, all anti-fuse
programming elements share common
property
– Uses materials which normally resides in high
impedance state
– But can be fused irreversibly into low impedance
state by applying high voltage
• Very low ON Resistance (Faster implementation of
circuits)
• Limited size of anti-fuse elements; Interconnects
occupy relatively lesser area.
• One Time Programmable
– Cannot be re-programmed (Design changes
are not possible)
– Retain configuration after power off
Difference between CPLD and
FPGA
 FPGAs use LUTs (Look-up Tables) while a CPLD
uses a simpler sum of products
 Using LUTs are advantageous as it provides
significant savings in processing time as the
chip would not need to go through the process of
recalculating the sum of products as CPLDs do.
 The main difference between FPGAs and CPLDs is
the complexity or the number of logic gates contained
in each.
 you can build more complex logic with FPGAs than
with CPLDs.
 LUTs are a form of memory, but it does not persist
once power is removed. CPLDs have non-volatile
memory embedded in the chips enabling them to
function right away without the need for external
ROM.
 FPGA uses Fine Grained Architecture and best for
Large Designs. CPLD uses Course Grained
Architecture and Best for Relatively Small Designs
General-purpose processors
• Programmable device used in a
variety of applications
– Also known as “microprocessor”
• Features
– Program memory
– General datapath with large register file
and general ALU
• User benefits
– Low time-to-market and NRE costs
– High flexibility
• Example: Pentium, ARM, …
Controller
Datapath
Control
logic and
State register
Register
file
IR
PC
Program
memory
General
ALU
Data
memory
Assembly code
for:
total = 0
for i =1 to …
119
Application-specific processors
• Programmable processor optimized
for a particular class of applications
having common characteristics
• Features
– Program memory
– Optimized datapath
– Special functional units
• Benefits
– Some flexibility, good performance,
size and power
• Example: DSP, Media Processor
Controller
Datapath
Control
logic and
State register
Registers
Custom
ALU
IR
PC
Program
memory
Data
memory
Assembly code
for:
total = 0
for i =1 to …
120
Single-purpose hardware
• Digital circuit designed to execute
exactly one program
– coprocessor, accelerator
• Features
– Contains components needed to
execute a single program
– No program memory
• Benefits
– Fast
– Low power
– Small size
Controller
Control
logic
Datapath
index
total
State
register
+
Data
memory
121