Ultra Thin HDI
Multi-purpose Test Vehicle
Definition Stage Project
C.B. Katzko, TTM Technologies
HDPUG Member Meeting, 2014 October 08
Toronto, Canada
Hosted by Celestica
© High Density Packaging Users Group, Inc.
Problem Statement
• Ultra-Thin HDI now dominates mobile/wearable design, but …
• STD test vehicles (IPC/ANSI/JEDEC) lag design by a decade:
•
•
•
•
Do not reflect the form factors, density & interconnect methods
Do not capture failure modes of fine pitch BGA technology
Have fallen into disuse by OEMs
Don’t provide upstream actors adequate data for development
Worldwide Shipments by Segment (Thousands)
2012
2013
2014
2017
341,263
315,229
302,315
271,612
9,822
23,592
38,687
96,350
116,113
197,202
265,731
467,951
Mobile Phone
1,746,176
1,875,774
1,949,722
2,128,871
Total
2,213,373
2,411,796
2,556,455
2,964,783
PC (DT & NB)
Ultra Book
Tablet
UT HDI now has a
dominant share,
but how does the
performance &
reliability stack-up?
© High Density Packaging Users Group, Inc.
Typical Handheld Design Practice
PCBs – leading edge
HDI/ALV Flex & Rigid Flex
ALV-HDI logic board
populated 2 sides
flex PCB video driver
integrated
display
panel
flex PCB
camera/sensors
flex PCB camera
shield
flex PCBs
switches &
sensors
Li-ion
Battery
Source : iFixit http://www.ifixit.com/Teardown/iPhone+5s+Teardown/17383
PoP SoC
flex PCB
home button
HDI PCB
audio/speaker
rigid-flex PCB
audio jack, lighting port
© High Density Packaging Users Group, Inc.
HDI/ALV Roadmaps
BGA Design Rules (microns)
BGA Pitch
Signal
Routing
Inner Line
Inner Space
Laser Via
Inner Pad
Outer Pad
0.40mm
1 Track
0.7
-
100
200
225
300
JISSO Roadmap
0.40mm
1 Track
60
65
75
200
200
275
Current Practice
0.40mm
2 Track
40
45
75
180
180
255
Next Gen High I/O SoC,
requires mSAP
0.30mm
1 Track
50
-
75
150
240
175
JISSO Roadmap
0.30mm
1 Track
50
50
75
200
240
175
Current Practice
0.30mm
2 Track
30
30
75
150
240
175
Forecast, requires mSAP
0.25mm
1 Track
50
50
50
100
-
-
JISSO Roadmap,
requires mSAP
0.15mm
1 Track
25
25
30
75
-
-
JISSO Roadmap,
requires coreless & SAP
SM Opening Remarks
At or beyond limit of subtractive process
Dielectric Thickness (microns)
Min BGA
Signal
Routing
Core Layer
Build-up
Layer
0.40mm
1 Track
60
60
10
Current Practice STD HDI
0.30mm
1 Track
50
45
10 ~ 12
Current Practice ADV HDI
0.30mm
2 Track
40
40
10 ~ 12
Next Generation ADV HDI
0.25mm
1 Track
40
30 ~ 35
10 ~ 12
Forecast 2015-2016
Total Layers Remarks
New materials and
processes require
validation 2 years
ahead of production
to obtain regulatory &
OEM qualifications
Project Goals
• Create/validate an open source ALV-HDI test vehicle based
on current & near term Smartphone design practice
•
•
•
•
General purpose test patterns for ALV PCB and assembly level tests
Reference drop test vehicle for JESD-B22-111 (existing design)
Smartphone form factor for JESD-B22-111 validation (new design)
Run validation tests for proof or concept/design & standardization
© High Density Packaging Users Group, Inc.
Project Objectives & Deliverables
Objectives:
• Build a collaborative working group for handheld product
technology within HDP for this and future projects
• Stakeholders from Materials, PCB, Packaging and Assembly
• Establish a suite of basic methods and tools suitable for the
general assessment of the technology
• Design, build & test first generation TV designs for validation
Deliverables:
•
•
•
•
Generic, modular, Test Vehicle form factor spec & DFM guidelines
General purpose test vehicle & drop test vehicle designs in Gerber
Demonstrator samples for future reference
Test data and reports for proof of concept build
Project Scope
What we will DO:
• Establish a generic TV form-factor for HDI projects
• Design general purpose and drop test vehicles for ultra thin HDI using
Stacked Via technology
• Using a reference material set, build, test and evaluate the TVs,
correlating to existing IPC and JEDEC TVs
• Evaluate the various test pattern designs for suitability for purpose
and determine if improvements are needed
• Provide tools and guidelines as deliverables
What we will NOT DO:
• Evaluate multiple materials for the purpose of evaluating
performance, reliability or suitability for any purpose
• Harm more Tamagotchi than absolutely necessary
TV Design Goals
The TV form factor should have the capability to:
• Scale to smartphone or handheld device form factors,
materials sets and production formats typical of the art
• Include as a design technology baseline:
• Modularized, based on 50mm x 50mm increments for various
mixes of bare board & assembly TVs
•
•
•
•
•
0.40mm pitch BGA & 0.30mm pitch WCSP devices
01005 chip passives
50/60um nominal line/space design rules
All Layer Via interconnect with stacked vias, Via in Pad
12 layer build-up in plane/signal pattern configuration and
pattern density typical of the art for Smartphone logic boards
• PCB materials typical of the art with FR4.1 with 1037 & 1067
reinforcement incorporated in the design
© High Density Packaging Users Group, Inc.
Multipurpose HDI TV Design
CAF 0.60mm pitch
PTH hole/hole
with diagonal
crossover wiring
CAF 0.50mm pitch
PTH hole/hole
with diagonal
crossover wiring
multi-purpose daisy-chains
0.40mm pitch 32 x 32 BGA simulator
3 x 5 sites = 15 x 1024 stacks = 15360 stacks
x 10 via interfaces = 153600 via interfaces
CAF
layer to layer
32mm square
1 cell
4 point bend
0.40mm pitch 32 x 32
BGA simulator
w/ ball shear/pull
CAF line/line
75um line 75um
space
multi-pattern
delamination
CAF line/line
75um line 50um
space
multi-purpose daisy-chains
0.30mm pitch 32 x 32 BGA simulator
3 x 5 sites = 15 x 1024 stacks = 15360 stacks
x 10 via interfaces = 153600 via interfaces
+
0.60mm, 0.50mm pitch 0.25mm through hole
32 x 20 x 1 blocks = 640 holes (per type)
CAF 0.30mm pitch
stacked via/via
9 blocks
with diagonal
crossover wiring
Hi-Pot Line/Line
High Current Type A
CAF 0.40mm pitch
stacked via/via
9 blocks
with diagonal
crossover wiring
Hi-Pot Layer/Layer
High Current Type B
Stacked Via IST 0.30mm pitch
Peel Strength +
Thermal Blank with/without copper
“pull” coupons for
progressive
microsection
analysis
BGA pattern
daisy-chain & CAF
enable dummy
BGA mounting to
simulate strain on
stacked vias
Change To :
0.40mm, 0.30mm,
0.25mm pitch
IST coupons
12L ALV Build-up
1
9um Cu Foil + Cu Plating
1 x 1037 70% RC
9um Cu Foil + Cu Plating
1 x 1037 70% RC
9um Cu Foil + Cu Plating
1 x 1067 67% RC
9um Cu Foil + Cu Plating
1 x 1067 67% RC
9um Cu Foil + Cu Plating
1 x 1067 70% RC
9um Cu Foil + Cu Plating
0.60mm 1 x 1078
9um Cu Foil + Cu Plating
1 x 1067 70% RC
9um Cu Foil + Cu Plating
1 x 1067 67% RC
9um Cu Foil + Cu Plating
1 x 1067 67% RC
9um Cu Foil + Cu Plating
1 x 1037 70% RC
9um Cu Foil + Cu Plating
1 x 1037 70% RC
9um Cu Foil + Cu Plating
2
3
4
Core
5
6
7
Build-up Layers
8
9
10
11
12
Target
Thickness um
25
40
18
46
18
50
18
50
18
52
18
58
18
52
18
50
18
50
18
46
18
40
25
730
Total Thickness
Description
SMD Assembly
Prepreg Dielectric
Signal
Prepreg Dielectric
Plane
Prepreg Dielectric
Signa
Prepreg Dielectric
Signal
Prepreg Dielectric
Plane
Core Dielectric
Plane
Prepreg Dielectric
Signal
Prepreg Dielectric
Signal
Prepreg Dielectric
Plane
Prepreg Dielectric
Signal
Prepreg Dielectric
SMD Assembly
Target
Cu Density
48%
50%
70%
IST Group
Material Type
50%
50%
70%
70%
IST Group
Layer
50%
50%
70%
50%
IST Group
Build-up Layers
ALV Reliability Test Vehicle
48%
© High Density
Packaging Users Group, Inc.
NB - Prepreg thickness estimate based on assumed average copper pattern thickness
& density
AATS & Drop TV Design
Job: droptest_me Step: cad-dt
Lyr: 01.pho
4 point bend
0.40mm pitch 32 x 32
BGA simulator
w/ ball shear/pull
Die/PCB overlay
CAF line/line
75um line 75um
space
• Schematic design completed
• Currently designing
UT-HDI conductor density
CAF line/line
11 Sep 2014,04:02 PM
75um line 50um
simulator features
for inner & outer layers
space
multi-pattern
delamination
Peel Strength +
Thermal Blank with/without copper
Test Plan
General Project Work Flow
Start
TV Design
& Tooling
PCB TV
& PoC Build
PCBA TV Design
& PoC Build
Definition Stage
Implementation
Stage
PCB Materials
PCB Fabrication
& SOT
PCBA TV
PCBA Assembly
Tooling Design
& Preparation
Data Analysis &
Failure Analysis
Components
& Assembly
Materials
Test Report
PCBA Assembly
& ICT
Paper & Poster
Short
Term
Tests
Long
Term
Tests
PCB TV
PCB TV
AATS
Drop
Tests
PCBA TV
Drop TV
End
Test Work Flow PCB & AATS TV
Without
Conditioning
Start
PCB coupons
Reflow
Simulation
6x, 12x, 20x
Short Term
Tests
reflow pass 6x
Start
PCBA TV
Assembly & Kit
0.30mm WCSP
assembly
AATS 1000x
or to fail
Long Term
Tests
Data Analysis,
Failure Analysis
& Reporting
End
Test Work Flow Drop Test Vehicles
Without
Conditioning
Start
PCB coupons
Reflow
Simulation
6x, 12x, 20x
Short Term
Tests
reflow pass 6x
Start
PCBA TVs
Assembly Kit
0.30mm WCSP
Drop Test
Drops to Failure
Data Analysis,
Failure Analysis
& Reporting
End
Project Task List
PCB BoM
HDPUG&UT(HDI&TV&Project&(&PCB&Materials&BOM
Item
Test&Vehicle&&
1(01 General&Purpose&Test&Vehicle
1(02
1(03
Component
FR4.1&Core,&0.62mm&1078&9um/9um
FR4.1&Prepreg&1067&69%&RC
FR4.1&Prepreg&1037&72%&RC
Supplier
Panasonic
Panasonic
Panasonic
1(04
VLP(ll&Microthin&9um/35um
Mitsui
1(05
Solder&Resist
Taiyo
1(06
1(11 Assembly&Drop&Test&Vehicle
1(12
1(13
(
FR4.1&Core&placeholder
FR4.1&Prepreg&placeholder
FR4.1&Prepreg&placeholderr
(
Panasonic
Panasonic
Panasonic
1(14
VLP(ll&Microthin&9um/35um
Mitsui
1(15
Solder&Resist
Taiyo
1(16
(
(
Supplier&PN
R(A555S
R(A555S
R(A555S
HS(VSP&or
WA(VSP
PSR(4000&D10ME
Matte&Black
(
R(A555S
R(A555S
R(A555S
HS(VSP&or
WA(VSP
PSR(4000&D10ME
Matte&Black
(
• Laminate materials donated by Panasonic
• Process materials & PCB fabrication donated by TTM
Panel&Qty
TBD
TBD
TBD
Unit/Panel
1
8
2
Qty&Total
TBD
TBD
TBD
TBD
10
A/R
TBD
AR
TBD
(
TBD
TBD
TBD
(
1
4
2
(
TBD
TBD
TBD
TBD
10
TBD
TBD
AR
TBD
(
(
(
PCBA BoM
HDPUG&UT(HDI&TV&Project&(&PCB&Assembly&Materials&BOM
Item
Test&Vehicle&&
3(01 AATS&Test&Vehicle
3(02
(
3(11 Drop&Test&Vehicle
3(12
3(13
(
Component
Solder&Paste,&SAC&305&placeholder
Flux&placeholder
(
Solder&Paste,&SAC&305&placeholder
Flux&placeholder
Underfill&Resin&placeholder
(
Supplier
Senju
Senju
(
Senju
Senju
TBD
(
Supplier&PN
Module&Qty Unit/Module
M705(RGS800HF&Type5
TBD
TBD
DELTALUX&NSV301HF
TBD
TBD
(
(
(
M705(RGS800HF&Type5
TBD
TBD
DELTALUX&NSV301HF
TBD
TBD
TBD&by&Engent
TBD
TBD
(
(
(
• Solder & flux materials donated by Senju
• Underfill materials and assembly process donated by Engent
• WCSP test devices proposed to be funded by HDPUG
Qty&Total
TBD
TBD
(
TBD
TBD
TBD
(
Testing Resources
AATS
Peel Strength
Drop Shock
Thermal Analysis
CAF/Ion Migration
Key Participants
Engent
Fei Xie
Kyzen
Mike Bixenmann
Panasonic
Tony Senese
Senju
Rafael Padilla
TTM
Angela Lee
Summer Xiao
C.B. Katzko
HDPUG
Project Leader
Ruben Bergman
Robert Smith
Project Facilitator
Supporters & Friends
Alcatel-Lucent
Joseph Smetana
ITEQ
Robert Hung
Boeing
Kenneth C. Noddings
Kyzen
Mike Bixenmann
Curtiss-Wright
Ivan Straznicky
Nihon Superior
Keith Howell
Engent
Dan Baldwin
Panasonic
Abe Tomoyuki
Paul Houston
Park Electro
Silvio Bertling
Flextronics
Jennifer Nguyen
Poltronic
Paul Collander
HDPUG
Jack Fisher
Sekisui
Hiroya Ishida
Lawrence Schultz
Shengyi Sytech
Kevin Zhang
Marshall Andrews
TTM Technologies
Zaron Huang
Hitachi Chemical
Isola
Ken Hikida
Marika Immonen
Takahiro Tanabe
Tarja Rapala
Fred Hickman
Texas Instruments
Luu Nguyen
TUC
Alan Cochrane
Thank You
Q&A
© High Density Packaging Users Group, Inc.