Quartus II Basic Training
Copyright © 2005 Altera Corporation
Programmable Logic Families
 Structured ASIC
 HardCopy® II, HardCopy Stratix
 High & Medium Density FPGAs
 Stratix II, Stratix, APEX™ II, APEX
20K, & FLEX 10K®
 Low-Cost FPGAs
 Cyclone II & Cyclone
 FPGAs with Clock Data Recovery
 Stratix II GX
 CPLDs
 MAX II, MAX 7000 & MAX 3000
 Embedded Processor Solutions
 Nios II
 Configuration Devices
 Serial (EPCS) & Enhanced (EPC)
Copyright © 2005 Altera Corporation
2
MAX 7000A & MAX 3000A Family
Overview
5,000 10,000
600 1,250 2,500
EPM7512AE
EPM7256AE
EPM7128AE
EPM7032AE
EPM3512A
EPM3256A
MAX 7000A
Useable Gates
600 1,250 2,500
Macrocells
32
64
128
256
512
32
64
128
256
512
Maximum User
I/O Pins
34
66
96
158
208
36
68
100
164
212
tPD (ns)
4.5
4.5
5.0
7.5
7.5
4.5
4.5
5.0
5.5
7.5
fCNT (MHz)
227
222
192
127
116
227
222
192
172
116
tSU (ns)
2.9
2.8
3.3
5.2
5.6
2.9
2.8
3.3
3.9
5.6
tCO1 (ns)
3.0
3.1
3.4
4.8
4.7
3.0
3.1
3.4
3.5
4.7
Copyright © 2005 Altera Corporation
3
EPM3128A
EPM3064A
EPM3032A
MAX 3000A
EPM7064AE
Parameter
5,000 10,000
Complete Voltage Portfolio
5.0 V
3.3 V
2.5 V
MAX 7000S
MAX 7000AE
MAX 7000B
 Performance



Leader
Feature Leader
Wide Range of
Package Offerings
Industrial-Grade
Offerings
 High Performance
 Feature Leader
 Wide Range of
 High Performance
 Feature Leader
 Wide Range of
Package Offerings
Package Offerings
MAX 3000A
 Price Leader
 Feature & Package
Subset of
MAX 7000AE
Copyright © 2005 Altera Corporation
4
MAX Device Block Diagram
Copyright © 2005 Altera Corporation
5
MAX Macrocell
Global Global
Clear Clock
Parallel Logic
Expanders
(from other MCs)
7000 has two Global Clock
Programmable
Register
Register
Bypass
ProductTerm
Select
Matrix
36 Programmable
Interconnect
Signals
Shared Logic
Expanders
16 Expander
Product Terms
Copyright © 2005 Altera Corporation
6
PRn
D Q
VCC
Clear
Select
ENA
CLRn
Clock/
Enable to PIA
Select
to I/O
Control
Block
MAX II: The Lowest-Cost CPLD Ever
 New Logic Architecture




1/2 the Cost
1/10 the Power Consumption
2X the Performance
4X the Density
 Non-Volatile, Instant-On
 Supports 3.3-, 2.5- & 1.8-V
Supply Voltages
Breakthrough Technology
to Expand the Market
Copyright © 2005 Altera Corporation
7
Flexible Supply Voltage
On-Chip Voltage
Regulator
Accepts 3.3-, 2.5- &
1.8-V Supply Inputs
Internally Converted to
1.8-V Core Voltage
Convenience of 3.3 V with
the Power & Performance of 1.8 V
Copyright © 2005 Altera Corporation
8
MAX II Device Family
Device
Typical
Logic
Elements Macro(LEs)
cells
User
I/O
Pins
Speed
Grades
Fastest
tpd1
(ns)
User
Flash
Memory
(bits)
EPM240
240
192
80
3, 4, 5
4.7
8,192
EPM570
570
440
160
3, 4, 5
5.5
8,192
EPM1270
1,270
980
212
3, 4, 5
6.3
8,192
EPM2210
2,210
1,700
272
3, 4, 5
7.1
8,192
Copyright © 2005 Altera Corporation
9
MAX II Packaging & User I/O Pins
Device
100-Pin TQFP1 144-Pin TQFP 256-Pin FBGA2
0.5-mm Pitch 0.5-mm Pitch 1.0-mm Pitch
16 x 16 mm
22 x 22 mm
17 x 17 mm
EPM240
80
EPM570
76
EPM1270
EPM2210
Denotes Vertical Migration
Notes:
1. TQFP: thin quad flat pack
2. FineLine BGA® package (1.0-mm pitch)
Copyright © 2005 Altera Corporation
10
116
160
116
212
204
324-Pin FBGA
1.0-mm Pitch
19 x 19 mm
272
New Small Packages
T100
0.5mm TQFP
16x16mm
New Packages
Partial
M100
0.5mm MBGA
6x6mm
F256
1.0mm FBGA
17x17mm
Partial
M256
0.5mm MBGA
11x11mm
 Packages minimize PCB area and optimize
ease-of-use
 Partial arrays allow for 2 layer PCB break out
Copyright © 2005 Altera Corporation
11
MAX II Architecture
Logic
Elements
(LEs)
Staggered
I/O Pads
Configuration
Flash Memory
JTAG &
Control
Circuitry
User Flash
Memory
Copyright © 2005 Altera Corporation
12
MAX II Logic Element (LE)
sload
sclear
aload
Register
Chain
addnsub
Reg
data1
data2
data3
cin
4-Input
LUT
data4
clock
ena
aclr
Row,
Column
& Direct
Link
Routing
Local
Routing
LUT
Chain
Register
Chain
Copyright © 2005 Altera Corporation
13
User Flash Memory
 Feature
 Flash Memory
Storage Bank
 8,192 Bits Per Device
 Interface to SPI, I2C,
Parallel, or Proprietary
Buses
Industry
First!
 Applications
 Store Revision & Serial
Number Data
 Store Boot-Up &
Configuration Data
Copyright © 2005 Altera Corporation
14
User Flash
Memory Block
MAX & MAX II Comparison
Parameter
MAX
MAX II
0.3-um EEPROM
0.18-um Flash
Product Term
Look-Up Table (LUT)
32 to 512 Macrocells
128 to 2210 Macrocells
(240 to 2,210 LEs)
Global
Row & Column
None
8 Kbits
212
272
5.0 V, 3.3 V, 2.5 V
3.3 V/2.5 V, 1.8 V
5.0 V, 3.3 V, 2.5 V, 1.8 V
3.3 V, 2.5 V, 1.8 V, 1.5 V
Global Clock Networks
2 per Device
4 per Device
Output Enables (OEs)
6 to 10 per Device
1 per I/O Pin
None
1 per I/O Pin
Process Technology
Logic Architecture
Density Range
Routing Architecture
On-Chip Flash Memory
Maximum User I/O
Pins
Supply Voltage
I/O Voltages
Schmitt Triggers
Copyright © 2005 Altera Corporation
15
What is Nios II?
 Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor
Debug
On-Chip
ROM
On-Chip
RAM
FPGA
Copyright © 2005 Altera Corporation
16
Avalon Switch Fabric
Nios II
CPU
Cache
- Nios
Developed
By Altera
II Plus Internally
All Peripherals
Written In HDL
- Can
Harvard
Architecture
Be Targeted
For All Altera FPGAs
- Synthesis
Royalty-Free
Using Quartus II Integrated Synthesis
UART
GPIO
Timer
SPI
SDRAM
Controller
Nios II Processor Architecture
Classic Pipelined RISC Machine












32 General Purpose Registers
3 Instruction Formats
32-Bit Instructions
32-Bit Data Path
Flat Register File
Separate Instruction and Data Cache (configurable sizes)
Tightly-Coupled Memory Options
Branch Prediction
32 Prioritized Interrupts
On-Chip Hardware (Multiply, Shift, Rotate)
Custom Instructions
JTAG-Based Hardware Debug Unit
Copyright © 2005 Altera Corporation
17
Problem: Reduce Cost, Complexity &
Power
Flash
I/O
CPU
SDRAM
I/O
I/O
I/O
I/O
I/O
FPGA
CPU
DSP
DSP
Solution: Replace External Devices
with Programmable Logic
Copyright © 2005 Altera Corporation
18
Problem:
Cost, Complexity
&
System
OnReduce
A Programmable
Chip (SOPC)
Power
Flash
FPGA
SDRAM
CPU is a Critical
Function
Solution:
ReplaceControl
External
Devices
Required
forProgrammable
System-Level Logic
Integration
with
Copyright © 2005 Altera Corporation
19
Licensing
 Nios II Delivered As Encrypted Megacore
 Licensed Via Feature Line In Existing Quartus II License File
 Consistent With General Altera Megacore Delivery Mechanism
 Enables Detection Of Nios II In Customer Designs (Talkback)
 No Nios II Feature Line (OpenCore Plus Mode)
 System Runs If Tethered To Host PC
 System Times Out If Disconnected from PC After ~ 1 hr
 Nios II Feature Line (Active Subscriber)
 Subscription and New Dev Kit Customers Obtain Licenses From
www.altera.com
 Nios II CPU RTL Remains Encrypted
 Nios II Source License
 Available Upon Request On Case-By-Case Basis
 Included With Purchase Of Nios II ASIC License
Copyright © 2005 Altera Corporation
20
Quartus II Basic Training
Quartus II Development System
Feature Overview
Copyright © 2005 Altera Corporation
Software & Development Tools
 Quartus II
 All Stratix, Cyclone & Hardcopy Devices
 APEX II, APEX 20K/E/C, Excalibur, &
Mercury Devices
 FLEX 10K/A/E, ACEX 1K, FLEX 6000
Devices
 MAX II, MAX 7000S/AE/B, MAX 3000A
Devices
 Quartus II Web Edition
 Free Version
 Not All Features & Devices Included
 See www.altera.com for Feature
Comparison
 MAX+PLUS® II
 All FLEX, ACEX, & MAX Devices
Copyright © 2005 Altera Corporation
22
Quartus II Development System
Fully-Integrated Design Tool
 Multiple Design Entry Methods
 Logic Synthesis
 Place & Route
 Simulation
 Timing & Power Analysis
 Device Programming
Copyright © 2005 Altera Corporation
Typical PLD Design Flow
Design Entry/RTL Coding
Design Specification
- Behavioral or Structural Description of Design
RTL Simulation
- Functional Simulation (Modelsim®, Quartus II)
- Verify Logic Model & Data Flow
(No Timing Delays)
LE
M512
M4K
I/O
Synthesis
- Translate Design into Device Specific Primitives
- Optimization to Meet Required Area & Performance Constraints
- Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA,
Quartus II
Place & Route
- Map Primitives to Specific Locations inside
Target Technology with Reference to Area &
Performance Constraints
- Specify Routing Resources to Be Used
Copyright © 2005 Altera Corporation
24
Typical PLD Design Flow
tclk
Timing Analysis
- Verify Performance Specifications Were Met
- Static Timing Analysis
Gate Level Simulation
- Timing Simulation
- Verify Design Will Work in Target Technology
PC Board Simulation & Test
- Simulate Board Design
- Program & Test Device on Board
- Use SignalTap II for Debugging
Copyright © 2005 Altera Corporation
25
Design Entry Methods
 Quartus II
TopLevel
File
 Text Editor
Top-level design files can
be schematic, HDL or 3rdParty Netlist File
 AHDL
 VHDL
 Verilog
 Schematic Editor
 Block Diagram File
 Graphic Design File
.bdf
.gdf
.bsf
.tdf
.vhd
.v
.edf
.edif
.v, vlg,
.vhd, .vhdl,
vqm
Block
File
Symbol
File
Text
File
Text
File
Text
File
Text
File
Text
File
 Memory Editor
 HEX
 MIF
Generated within Quartus II
 3rd-Party EDA Tools
 EDIF
 HDL
 VQM
 Mixing & Matching Design Files Allowed
Copyright © 2005 Altera Corporation
26
Imported from 3rd-Party
EDA tools
Quartus II Basic Training
Quartus II Quick Start
LAB1
Copyright © 2005 Altera Corporation
Objectives
Create a project using the New Project
Wizard
Name the project
Add design files
Pick a device
Copyright © 2005 Altera Corporation
28
Step 1 (Setup Project for QII5_1)
Under File, Select New Project Wizard….
A new window appears. If an Introduction
screen appears, click Next.
Copyright © 2005 Altera Corporation
29
Step 2 (Setup Project for QII5_1)
Page 1 of the wizard should be completed with the following
working directory for this project
<lab_install_directory> \Dsp_7_segment\
name of project
Dsp_7_segment
top-level design entity
Dsp_7_segment
Copy “state_machine.v” and past in
Dsp_7_segment
Click Next to advance to the
Project Wizard: Add Files [page 2 of 5].
Copyright © 2005 Altera Corporation
30
Step 3 (Setup Project for QII5_1)
Using the browse button, select state_machine.v
Add to the project. Click Next.
Copyright © 2005 Altera Corporation
31
Step 4 (Setup Project for QII5_1)
On page 3, select Stratix as the Family. Also, in the Filters section,
set Package to FBFA, Pin count to 780, and Speed grade to 5.
Select the EP1S25F780C5 device from
the Available devices: window. Click Next.
Copyright © 2005 Altera Corporation
32
Step 5 (Setup Project for QII5_1)
On page 4 , you can specify any third party EDA tools you may be using
along with Quartus II. Since these exercises will be done entirely within
Quartus II, click Next.
Copyright © 2005 Altera Corporation
33
Step 6 (Setup Project for QII5_1)
The summary screen appears as shown. Click Finish.
The project is now created.
Copyright © 2005 Altera Corporation
34
Quartus II Basic Training
Quartus II Quick Start
LAB2
Copyright © 2005 Altera Corporation
Objectives
Create a counter using the MegaWizard
Plug-in Manager
Build a design using the schematic editor
Analyze and elaborate the design to check
for errors
Copyright © 2005 Altera Corporation
36
Step 1 Create schematic file
Select File  New and select Block Diagram/Schematic File. Click OK.
Select File  Save As and save the file as
<lab_install_directory> \Dsp_7_segment\ Dsp_7_segment.bdf
Copyright © 2005 Altera Corporation
37
Step 2 Build an 23 bits counter using the MegaWizard Plug-in Manager
1.Choose Tools  MegaWizard Plug-In Manager. In the window that appears,
select Create a new custom megafunction variation. Click on Next.
2.On page 2a of the MegaWizard expand the arithmetic folder and select
LPM_COUNTER.
3.Choose Verilog HDL output For the name of the output file, type timer_1s.
Click on Next
Copyright © 2005 Altera Corporation
38
Step 3
1.
2.
3.
Set the output bus to 27 bits. For the remaining settings in this window,
use the defaults that appear .. Select next
.Turn on “Modulus , with a count modulus of “and key in 79999999
Select finish
Copyright © 2005 Altera Corporation
39
Step 4
In the Graphic Editor, double-click in the screen so that the Symbol Window
appears. Inside the symbol window, click on
to expand the symbols defined
in the Project folder. Double-click on timer_1s. Click the
left mouse button to put down the symbol inside the schematic file.. The symbol
for “timer_1s” now appears in the schematic.
Copyright © 2005 Altera Corporation
40
Step 5
1.
2.
3.
4.
From the File menu, open the file state_machine.v
From the File menu, go the Create/Update menu option and select
Create Symbol Files for Current File. Click Yes to save changes
to Dsp_7_segment.bdf.
Once Quartus II is finished creating the symbol, click OK. Close the
state_machine.v file
In the Graphic Editor, double-click in the screen so that the Symbol
Window appears again. Double-click on state_machine in the
Project folder. Click OK... The symbol for state_machine now
appears in the schematic.
Copyright © 2005 Altera Corporation
41
Step 6 Add Pins to the Design
1.
2.
3.
4.
.
Input
Output
sys_clk
7_out[6..0]
reset
Dig1
For each of the pins listed in left Table , you must insert
a pin and change its name
To place pins in the schematic file, go to Edit  Insert  Symbol OR
double-click in any empty location of the Graphic Editor.
Browse to libraries  primitives  pin folder. Double-click on input
or output Hint: To insert multiple pins select Repeat Insert Mode.
To rename the pins double-click on the pin name after it has been
inserted.
Type the name in the Pin name(s) field and Click OK
Copyright © 2005 Altera Corporation
42
Step 7 Connect the Pins and Blocks in the Schematic
1.
In the left hand tool bar click on
button to draw a wire and
button to draw a bus.
Another way to draw wires and busses is to place the cursor next to the port of any
symbol. When you do this, the wire or bus tool will automatically appear.
2.
Connect all of the pins and blocks as shown in the figure below
Copyright © 2005 Altera Corporation
43
Step 8 Save and check the schematic
1.
2.
3.
Click on the Save button in the toolbar
to save the schematic.
From the Project menu, select Add/Remove Files in Project.
Click on the browse button to make sure the Dsp_7_segment.bdf,
timer_1s and state_machine are added to the project.
From the Processing menu, select Start  Start Analysis & Elaboration.
4.
Analysis and elaboration checks that all the design files are present and
connections have been made correctly.
Click OK when analysis and elaboration is completed
Copyright © 2005 Altera Corporation
44
Quartus II Basic Training
Quartus II Quick Start
LAB3
Copyright © 2005 Altera Corporation
Objectives
Pin assignment
Perform full compilation Build a design
using the schematic editor
How to Download programming file
Copyright © 2005 Altera Corporation
46
Step 1
1.
2.
3.
Choose Assignments  Assignment editor.
From the View menu, select Show All Know Pin Names.
Please click Pin in Category
Copyright © 2005 Altera Corporation
47
Step 2
1.
2.
3.
4.
5.
6.
7.
Pls install DSP Development Kit Stratix edtion CD
Open ds_stratix_dsp_bd.pdf from C:\megacore\stratix_dsp_kit-v1.1.0\Doc
Check clk , pushbotton and seven segment display pin location from
ds_stratix_dsp_bd.pdf
Key your pin number in location
Click on the Save button in the toolbar
From Assignments, select Device. Click Device & Pin options. Click
Unused pins .Select As input tri-stated from Reserve all unused pins
From the Processing menu, select Start Compilation
Copyright © 2005 Altera Corporation
48
Step 3
1.
2.
3.
4.
From the Tools menu, select programmer
Click on Add File. Select Dsp_7_segment.sof.
Check Hardware Setup. Select your download cable on
Currently selected hardware(ByteBlasterII)
Select JTAG from Mode
Copyright © 2005 Altera Corporation
49
Step 4
1.
2.
3.
Turn on Program/configure. Or see figure below
Click Start
See 7-segment status
Copyright © 2005 Altera Corporation
50
SignalTap II Agenda
 SignalTap II Overview & Features
 Using SignalTap II Interface
 Advanced Triggering
Copyright © 2005 Altera Corporation
51
SignalTap II ELA
 Captures the Logic State of FPGA Internal
Signals Using a Defined Clock Signal
 Gives Designers Ability to Monitor Buried Signals
 Connects to Quartus II through FPGA JTAG Pins
 Captures Real-Time Data
 Up to 200 Mhz
 Is Available for Free
 Installed with Full Subscription or Web Edition
 Installed with Stand-Alone Programmer
Copyright © 2005 Altera Corporation
52
SignalTap II Device Support
Stratix & Stratix II
Stratix GX
Cyclone & Cyclone II
Excalibur
Mercury
APEX II
APEX 20K/E/C
Copyright © 2005 Altera Corporation
53
How Does It Work?
1. Configure ELA
2. Download ELA into
FPGA along with
Design
3. ELA Samples Internal
Signals
4. Quartus II
Communicates with
ELA through JTAG
Copyright © 2005 Altera Corporation
54
Stratix/Cyclone Sample Resource Usage
Number of
Channels
Logic Elements
Trigger Level 1
Trigger Level 2
Trigger Level 3
8
316
371
426
32
566
773
981
256
2900
4528
6156
Number of
Channels
M4Ks Based on Sample Depth
256
512
2K
8K
32K
8
<1
1
4
16
64
32
2
4
16
64
256
256
16
32
128
512
Copyright © 2005 Altera Corporation
55
Modes of Operation
Three Different Configurations
 Internal RAM ELA Configuration
 Debug Port ELA Configuration
 Hybrid Approach
Provides Flexibility Based on Available
Device Resources
 Memory Resources Are Limited
Use Debug Port Configuration
 Pin Resources Are Limited
Use Internal RAM Configuration
Copyright © 2005 Altera Corporation
56
Supported Download Cables
USB Blaster
 USB Port Cable
ByteBlaster™ II
 Parallel Port Cable
ByteBlasterMV™
 Parallel Port
MasterBlaster™
 USB / Serial Port Cable
Copyright © 2005 Altera Corporation
57
SignalTap II Key Features
Setup
Data Triggering
Data Capture
Data Analysis
Copyright © 2005 Altera Corporation
58
Setup Features
 Up to 1024 Data Channels
 Multiple Analyzers in One Device
 Supports Analysis of Multiple Clock
Domains
 Each Analyzer Can Run Simultaneously
Setup
Data Triggering
Data Capture
 Resource Usage Estimation
 Incremental Design Support
Copyright © 2005 Altera Corporation
59
Data Analysis
Data Triggering Features
 Up to 10 Trigger Levels Per Channel
Setup
 Allows Application of Simple (Basic) &
Complex (Advanced) Triggering Schemes
 Defines a Sequential Pattern of Logic Conditions
Data Triggering
 Each Trigger Level is Logically ANDED
 If (L1 & L2 ... & L10) == TRUE  Data Capture
Data Capture
Data Analysis
Copyright © 2005 Altera Corporation
60
Data Triggering Features (Cont.)
 Three Main Trigger Positions
Setup
trigger
Samples Captured
Samples Captured
Old Samples
New Samples
TIME
Data Triggering
 Trigger Input
 Setup External Trigger to Trigger the Analyzer
 Trigger Output
Data Capture
 Signifies Trigger Event Occurred with SignalTap II
 Use One ELA’s Trigger Output as Trigger
Input for Another
Copyright © 2005 Altera Corporation
61
Data Analysis
Data Capture Features
 Up to 128K Samples Per Channel
Setup
 Increases Chance of Catching Target
Event
 Two Methods of Data Acquisition
1. Circular
2. Segmented
Data Triggering
Data Capture
 Mnemonic Tables

Create User-Defined Labels for Bit Sequences
(Ex. State Machine)
Copyright © 2005 Altera Corporation
62
Data Analysis
SignalTap II Design Flow
1) Use SignalTap II File (.STP)
 Use Quartus II GUI
 STP Separate from Design Files
2) Use Quartus II MegaWizard
 Instantiate Directly into HDL
Copyright © 2005 Altera Corporation
63
Using STP File
1. Create .STP File
•
•
•
•
•
Assign Sample Clock
Specify Sample Depth
Assign Signals to STP File
Specify Triggering
Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
Copyright © 2005 Altera Corporation
64
1) Creating a New .STP File
 To Create a .STP File
 Method 1
 Select the
in Quartus II
 Method 2
 Select New (File Menu)
 Other Files
 SignalTap II File
 Default File Name Will Be STP1.stp
Copyright © 2005 Altera Corporation
65
Main .STP File Components
.STP File
JTAG Chain
Configuration
Instance Manager
Waveform Viewer
Copyright © 2005 Altera Corporation
66
Signal Configuration
Instance Manager
Instance Manager
 Selects Current ELA to Setup/View
 Displays the Current Status of each Instance
 Displays Size (Resource Usage) of ELA
Copyright © 2005 Altera Corporation
67
Assign Sample Clock
 Use Global Clock for Best
Results
 Data Written to Memory on
Every Sample Clock Rising
Edge
 Clock Signal Cannot Be
Monitored as Data
 External Clock Pin Created
Automatically if Clock
Unassigned
 auto_stp_external_clock
 ELA Expects External Signal to
be Connected to Clock Pin
Copyright © 2005 Altera Corporation
68
Specify Sample Depth
 Sample Depth
 Set Number of Samples
Stored for each Data Signal
 0 to 128K Sample Depth
 0 Selected When External
Analyzer Is Used
 Select RAM Type for Stratix
& Stratix II Devices
 Useful when Preserving a
Specific Memory Type is
Necessary
Copyright © 2005 Altera Corporation
69
Data Capture
 Circular
 Specify Trigger Position
 Pre
 Center
 Post
 Continuous
 Segmented
 Specify Segment Depth
Copyright © 2005 Altera Corporation
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Triggering
 Trigger Levels
 Indicate up to 10 Trigger Conditions
 Trigger-In
 Any I/O Pin Can Trigger the SignalTap
II Analyzer
 Generates auto_stp_trigger_in_n Pin
 Trigger-Out
 Indicates When a Trigger Pattern
Occurs
 Generates auto_stp_trigger_out_n Pin
 Delayed 4 Clock Cycles after Actual
Trigger Event
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Waveform Viewer
Setup Tab Describes the Signal Settings
 Data Signals vs. Trigger Signals
 Sets up Each Triggering Level (L1 – L10)
Data Tab Displays Captured Data
Copyright © 2005 Altera Corporation
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STP File Waveform Viewer
Setup Tab
Data Tab
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Basic Triggering
All Signals Must Be
True for Level to
Cause Data Capture
Right-Click
to Set Value
Copyright © 2005 Altera Corporation
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Debug Port
 Routes Data Signals to Spare I/O Pins for
Capture by External Logic Analyzer
 Quartus II Automatically Generates
auto_stp_debug_out_m_n Pin
 m Represents the Instance Number of the Analyzer
 n Represents the Order the Debug Port Pin Occurs
in the Signal List
Copyright © 2005 Altera Corporation
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Mnemonic Table
 Allows a Set of Bit Patterns
to Be Assigned UserDefined Names
 Right-Click in the Setup View
of an STP File & Select
Mnemonic Setup
 Select Add Table
 Select Add Entry
 Ex. State Machines or
Decoders/Encoders
Copyright © 2005 Altera Corporation
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JTAG Chain Configuration
Select Programming Hardware
Scan Chan Button Automatically
Determines Devices Physically Connected
to the Chain
Detects Non-Altera Devices & Displays Them as
Unknown
Copyright © 2005 Altera Corporation
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2) Save .STP File & Compile

SignalTap II Logic Analyzer Control in Compiler
Settings
 Assignments  Settings
 Specify the STP File to Compile with Project
Copyright © 2005 Altera Corporation
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3) Program Device(s)
 Use Quartus II Programmer or STP File
 Program Button in the SignalTap II Interface Only
Configures the Selected Device in Chain
 Use Quartus II Programmer to Program Multiple
Devices
 Can Create a STP File for each Device in the JTAG Chain
Copyright © 2005 Altera Corporation
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4) Acquire Data
SignalTap II Toolbar & STP File Controls
 Run
 Autorun
 Stop
 Read Data (Reads in Data from Last Analysis)
Copyright © 2005 Altera Corporation
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Displaying Acquired Data
Format in Time or
Sample Number
 Display Signal as Bar or Line Chart
 Export to Other Tools for Viewing or Analysis (File
Menu)
 Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File
Copyright © 2005 Altera Corporation
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Using STP File Review
1. Create .STP File
•
•
•
•
•
Assign Sample Clock
Specify Sample Depth
Assign Signals to STP File
Specify Triggering
Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
Copyright © 2005 Altera Corporation
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Recompilation
Recompilation Required
 Addition/Removal of Instance, Data or Trigger
 Modifying the Sample Clock or Buffer Depth
 Enabling/Modifying Trigger-In/Trigger-Out
 Enabling the Debug Port
Lock Mode Prevents Changes Requiring
Recompilation
Copyright © 2005 Altera Corporation
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Reducing Recompilation Times
 Incremental Compilation
 Maintains Design Synthesis & Placement
 Recompiles Only Logic Analyzer
 Change SignalTap II Configuration without Affecting Existing
Logic
 Incremental Routing
 Allows Switching Trigger & Data Nodes without Full
Recompilation
 Cannot Be Used Together in 5.0
 Use Incremental Compilation First, Switch to Routing
 Will Be Supported in Future Version of Quartus II
Copyright © 2005 Altera Corporation
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SignalTap II Incremental Compilation
1)
Enable Full Incremental Compilation

2)
Any User-Defined
Partitions Must Be
Removed
(5.0 Limitation)
Set Netlist Type of Top-Level Partition to Post-Fit
Copyright © 2005 Altera Corporation
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Assignments Menu
SignalTap II Incremental Compilation
3)
4)
Compile Design
Enable SignalTap II Incremental Compilation


Only Post Fitting Nodes Can Be Incrementally Compiled
Quartus II Will Automatically Convert Pre-Synthesis Nodes to
Post-Fitting
Copyright © 2005 Altera Corporation
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SignalTap II Incremental Routing
1)
Enable Smart Recompilation
2)
Manually Set the Number of Allocated Nodes


Nodes Acts as Place Holders for Real Signals that Can Be Added Later
Auto Creates Enough Nodes for Current Number of Data/Triggers
Copyright © 2005 Altera Corporation
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SignalTap II Incremental Routing
3)
Add Post-Fitting nodes to STP file


SignalTap II: Post-Fitting Nodes Always Incrementally Routed
SignalTap II: Pre-Synthesis Nodes Always Cause Full
Recompilation if Added Later

Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes
is They Can Be Removed & Replaced with Post-fitting Nodes
without Total Recompilation
Pre-Synthesis
Nodes
Post-fitting
Nodes
Copyright © 2005 Altera Corporation
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Quartus II Netlist Optimization
 New Synthesis Optimization Features Do Not
Work Well with SignalTap II
 SignalTap II Nodes may Disappear
 Register Re-timing & WYSIWYG Re-Synthesis Should
be Disabled if SignalTap II is Used
 Set Netlist Optimizations Logic Option to Never
Allow on Entities which Have SignalTap II Nodes
Copyright © 2005 Altera Corporation
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Performance Preservation
SignalTap II can Potentially Effect the
Performance of a Design
 Routing and/or Placement Can Change
Possible Solution
 Back-Annotate Design before Adding
SignalTap II
 See Quartus II Handbook, Volume 3, Chapter
10 for More Suggestions
Copyright © 2005 Altera Corporation
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Thank You
Copyright © 2005 Altera Corporation
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