EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
INSTITUTO TECNOLÓGICO Y DE ESTUDIOS SUPERIORES DE OCCIDENTE
RECONOCIMIENTO DE VALIDEZ OFICIAL, ACUERDO S.E.P. No. 86990
DE FECHA 3 DE DICIEMBRE DE 1976
DEPARTAMENTO DE ELECTRÓNICA, SISTEMAS E INFORMÁTICA
Especialidad en diseño de circuitos Integrados.
Presenta:
Ing. Ricardo Dávila Castro
Instructor:
Mariano Aguirre
1
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
TAREA 4.- Diseño de microprocesador MIPS32 básico multi-ciclo
Máquina de estados Propuesta .
0
1
FETCH
INICIO
MemRead = 1'b1;
ALUSrcA = 1'b0;
lorD= 1'b0;
IRWrite = 1'b1;
ALUSrcB = 2'b01;
ALUOp= 2'b00;
PCWrite = 1'b1;
PCSource = 2'b00;
6
8
DECODE
ALUSrcA = 1'b0;
ALUSrcB = 2'b11;
ALUOp= 2'b00;
2
9
10
MEMORY ADDRESS
COMPUTATION
BRANCH
EXECUTION
ALUSrcA = 1'b1;
ALUSrcB = 2'b00;
ALUOp= 2'b01;
PCSource = 2'b00;
PCWriteCond = 1'b1;
ALUSrcA = 1'b1;
ALUSrcB = 2'b00;
ALUOp= 2'b10;
ALUSrcA = 1'b1;
ALUSrcB = 2'b10;
ALUOp= 2'b00;
JUMP
PCWrite = 1'b1;
PCSource = 2'b10;
IMMEDIATE
ALUSrcA= 1'b1;
ALUSrcB= 2'b10;
ALUOp = 2'b11;
11
3
7
5
IMMEDIATE COMPLETITION
MEMORY ACCESS
MemRead = 1'b1;
lorD= 1'b1;
MEMORY ACCESS
lorD= 1'b0;
MemWrite = 1'b0;
R-TYPE COMPLETION
RegWrite = 1'b0;
MemtoReg = 1'b0;
RegDst = 1'b0;
RegWrite = 1'b0;
MemtoReg = 1'b0;
RegDst = 1'b0;
4
MEMORY READ
COMPLETITION STEP
RegWrite = 1'b0;
MemtoReg = 1'b0;
RegDst = 1'b0;
2
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Zero
PcWriteCond
PcWrite
lorD
Control
PCSouce
AluSrcA
MemWrite
MemRead
AluScrB
AluControl
IRWrite
RegWrite
CONTADOR
DE
PROGRAMA
Instruccion
[25:0]
Instrucción
[31-26]
MUX
0
Jump Address
[31:0]
0
REGISTRO A
Instuccion
[25:21]
Address
[31:0]
MUX
1
Instuccion
[20:16]
REGISTER FILE
REGISTER FILE
0
MemtoReg
MEMORIA
ALU
MUX
REGISTRO B
Instuccion
[15:0]
1
4
0
1
2
MUX
3
0
MUX
MEMORY DATA REGISTER
1
1
Instuccion
Extension
PortOut
[15:0]
Signo
[31:0]
PortIn
[31:0]
Funct/Opcode
[5:0]
SHIFT TO
LEFT
Diagrama a bloques Micro Mips
3
2
SHIFT TO
LEFT
Shamp
[5:0]
RegDst
SHIFT TO
RIGHT
>>2
0
1
Departamento de Electrónica, Sistemas e Informática (DESI)
Alu
Control
REGISTO ALU
3
MUX
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Codigo Verilog Modulos
/*
* MemoriaRamRom.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module MemoriaRamRom(Clk, MemRst, MemAddress, WriteData, MemWrite, MemRead, MemData);
input [31:0] MemAddress, WriteData;
input MemRead, MemWrite, MemRst,Clk;
output wire [31:0] MemData;
reg [31:0] ArrMemory [0:63];
always @ (posedge Clk) begin
if (MemRst)
begin
/*INSTRUCCIONES EN MEMORIA*/
ArrMemory[0] <= 32'h 1C_01_00_08;
ArrMemory[1] <= 32'h 8C_01_00_0D; //Load LW 100011ss sssttttt i1000iii iiiiiiii 10001100 00000001 00000
ArrMemory[2] <= 32'h 8C_02_00_0E; // Load LW
ArrMemory[3] <= 32'h 00_41_18_20; //Add
ArrMemory[4] <= 32'h AC_23_00_15; //Store SW
ArrMemory[5] <= 32'h 00_41_20_22; //SUB
ArrMemory[6] <= 32'h 00_41_28_24; //and 000000 00_010 00001 _00101000_00000000;
ArrMemory[7] <= 32'h 00_41_30_26; //xor 000000 00_010 00001 _00110000_00000000;
ArrMemory[8] <= 32'h 00_24_38_E7; //00000000_00000001_00111000_11100111; //shift to right 000000-- ---ttttt dddddhhh hh000010 28+2 x00111000 11100111
ArrMemory[9] <= 32'h 00_24_40_EE; //shift to left 000000ss sssttttt dddddhhh hh000010
ArrMemory[10] <= 32'h 1C_33_00_08; //ADDI
000111ss sssttttt dddddiii iiiiiiii
ArrMemory[11] <= 32'h 08_00_00_1C; //jump
00001000 00000000 00000000 00000000
ArrMemory[12] <= 32'h 10_A1_00_02; //beq
000100ss sssttttt iiiiiiii iiiiiiii Magnitud del salto a partir de la instrucción actual,
//
representado en complemento a 2
/*DATOS EN MEMORIA */
// 10100001
ArrMemory[13] <= 32'h 04; //DATO EN 0A LO ESCRIBE EN EL REG 1
ArrMemory[14] <= 32'h 05;
ArrMemory[15] <= 32'h 03; //sw
ArrMemory[16] <= 32'h 01;
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Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
ArrMemory[17] <= 32'h 15;
ArrMemory[28] <= 32'h 10_A1_00_02;
ArrMemory[31] <= 32'h 78;
end
else
if(MemWrite && (MemAddress > 8'h11))
begin
ArrMemory[MemAddress] <= WriteData;
end
end
assign MemData = (MemRead) ? ArrMemory[MemAddress] : 0;
endmodule
/*
* RegisterFile.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module RegisterFile(
input Clk,
input Reset,
input [31:0] PortIn,
input RegWrite, // señal de control
input [4:0] ReadRegA, // primer registro fuente Operando A rs
input [4:0] ReadRegB, //primer registro fuente Operando B rt
input [4:0] WriteRegister, // registro destino resultado rd
input [31:0] WriteData, //dato
output [31:0]ReadDataA, // a la alu
output [31:0]ReadDataB, // a la alu
output [31:0] PortOut
);
parameter [5:0] REG_ANCHO = 32;
parameter [5:0] REG_LARGO = 32;
reg [REG_ANCHO-1:0] RegFile [0:REG_LARGO-1];
reg [5:0] i;
5
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
always @(posedge Clk)
begin
if (Reset)
RegFile[0] <= 0;// reg base
if(RegWrite)
if ((WriteRegister != 5'h 00) || (WriteRegister != 5'h 1F))
RegFile[WriteRegister] <= WriteData;
else
if ((WriteRegister == 5'h 00))
RegFile[WriteRegister] <= 0;
else
RegFile[30] <= PortIn;
end
assign ReadDataA = RegFile[ReadRegA] ;
assign ReadDataB = RegFile[ReadRegB] ;
assign PortOut = (WriteRegister != 5'h 1E)? 32'h zz_zz_zz_zz: RegFile[31] ;
//assign ReadDataA = (WriteRegister != 5'h 1E) ? RegFile[ReadRegA] : RegFile[30] ;
//assign ReadDataB = (WriteRegister != 5'h 1E) ? RegFile[ReadRegB] : RegFile[30] ;
endmodule
/*
*Alu.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
//MODULO DE LA UNIDAD ARITMETICO LOGICA
module Alu(DatoInA, DatoInB,Shampt, Operacion, AluResult, Zero);
input [4:0] Shampt;
input [31:0] DatoInA, DatoInB;
input [3:0] Operacion;
output reg [31:0] AluResult;
output Zero;
always @ (*) begin
case (Operacion)
4'h0: AluResult = DatoInA&DatoInB; //and
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Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
4'h1:
4'h2:
4'h3:
4'h6:
4'h7:
AluResult = DatoInA|DatoInB; //or
AluResult = DatoInA+DatoInB; //add suma
AluResult = DatoInA^DatoInB; //xor
AluResult = DatoInA-DatoInB; //Zero= (!AluResult)? 1:0 ; end//subtract resta
begin
/*if(DatoInB<DatoInA) */ AluResult = 32'h ff_ff_ff_ff;
//if(DatoInB>=DatoInA) AluResult = 32'h 00_00_00_00;
end
4'hC: AluResult = ~(DatoInA|DatoInB); //NOR
4'hD: AluResult = ~(DatoInA&DatoInB); //NAND
4'hE: AluResult = DatoInB >> Shampt[4:0]; //shift right
4'hF: AluResult = DatoInB << Shampt[4:0]; //shift left
default :
AluResult=0;
endcase
end
assign Zero = (AluResult==0)? 1 : 0;
endmodule
/*
* AluControl.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module AluControl(
input [5:0] Opcode, //pa la add inmediata
input [1:0] ALUOp,
input [5:0] Funct,
output reg [3:0]Operacion
);
parameter [1:0] DATATRANSFER = 00,
BRANCH= 2'b 01,
REGISTER = 2'b 10,
IMMEDIATE = 2'b 11;
always @ (*)
begin
Operacion = 4'h 2;
case (ALUOp)
DATATRANSFER: Operacion = 4'h 2; //suma
7
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
BRANCH: Operacion = 4'h 6; //resta
REGISTER: case (Funct)
6'h 20: Operacion = 4'h 2; //R-type add
6'h 22: Operacion = 4'h 6; //R-type subtract
6'h 24: Operacion = 4'h 0; //R-type and
6'h 25: Operacion = 4'h 1; //R-type or
6'h 2A: Operacion = 4'h 7; //R-type set on less than
6'h 26: Operacion = 4'h 3; //R-type xor
6'h 27: Operacion = 4'h E; //R-type shift right
6'h 2E: Operacion = 4'h F; //R-type shift left
default:
Operacion = 4'h x;
endcase
IMMEDIATE: begin if (Opcode==4'h7) Operacion = 4'h 2; end
default :
Operacion = 4'h x;
endcase
end
endmodule
/*
* Control.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module Control(
input Clk,
input Reset,
input [5:0] Op,
output reg PCWriteCond,
output reg PCWrite,
output reg lorD,
output reg MemRead,
output reg MemWrite,
output reg MemtoReg,
output reg IRWrite,
output reg [1:0] PCSource,
output reg [1:0] ALUOp,
output reg [1:0] ALUSrcB,
output reg ALUSrcA,
output reg RegWrite,
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Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
output reg RegDst
);
reg [4:0] EstadoActual =0;
//reg [4:0] Inicio;
reg [4:0] SiguienteEstado=0;
parameter [3:0] S0=0;
parameter [3:0] S1=1;
parameter [3:0] S2=2;
parameter [3:0] S3=3;
parameter [3:0] S4=4;
parameter [3:0] S5=5;
parameter [3:0] S6=6;
parameter [3:0] S7=7;
parameter [3:0] S8=8;
parameter [3:0] S9=9;
parameter [3:0] S10=10;//inmediato
parameter [3:0] S11=11; //inmediato
always@(posedge Clk) begin
if (Reset)
EstadoActual <= S0;
else
EstadoActual <= SiguienteEstado;
end
always @(*) begin
MemRead = 1'b0; //1
ALUSrcA = 1'b0; //2
lorD= 1'b0;
//3
IRWrite = 1'b0; //4
ALUSrcB = 2'b00; //5
ALUOp= 2'b00; //6
PCWrite = 1'b0; //7
PCSource = 2'b00; //8
RegWrite = 1'b0;
MemWrite = 1'b0;
RegDst = 1'b0;
MemtoReg = 1'b0;
PCWriteCond = 1'b0;
SiguienteEstado = EstadoActual;
9
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
case(EstadoActual)
S0: begin //fetch
MemRead = 1'b1; //1
ALUSrcA = 1'b0; //2
lorD= 1'b0;
//3
IRWrite = 1'b1; //4
ALUSrcB = 2'b01; //5
ALUOp= 2'b00; //6
PCWrite = 1'b1; //7
PCSource = 2'b00; //8
RegWrite = 1'b0; //10
MemWrite = 1'b0; //11
PCWriteCond = 1'b0; //12
MemtoReg = 1'b0; //13
RegDst = 1'b0;
SiguienteEstado = S1;
end
S1: begin //decodificacion
MemRead=1'b0;
IRWrite=1'b0;
ALUSrcA=1'b0;
ALUSrcB=2'b11;
PCWrite=1'b0;
ALUOp= 2'b00;
//si el op code carga ld o un std
if(Op==6'h 23 || Op==6'h 2B) begin SiguienteEstado=S2; end
//if R type instruction
if(Op==6'h 00) begin SiguienteEstado=S6; end
//salto si es igual
if(Op==6'h 04) begin SiguienteEstado=S8; end
//si es un salto
if(Op==6'h 02) begin SiguienteEstado=S9; end
// pal inmediato
// if((Op==6'b001100)|(Op==6'b001101)|(Op==6'b001110)|(Op==6'b001111)) begin SiguienteEstado = S10; end // estado extra
if((Op==6'h 07)|(Op==6'h 0D)|(Op==6'h 0E )|(Op==6'h 0F)) begin SiguienteEstado = S10; end // estado extra
end
S2: begin // memory addres computation
ALUSrcA = 1'b1;
ALUSrcB= 2'b10;
ALUOp = 2'b00;
// ld
10
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
if(Op==6'h 23) begin SiguienteEstado=S3; end
//std
if(Op==6'h 2B) begin SiguienteEstado=S5; end
end
S3: begin
MemRead=1'b1;
lorD = 1'b1;
SiguienteEstado=S4;
end
S4: begin
RegDst = 1'b0;
RegWrite = 1'b1;
MemtoReg= 1'b1;
MemRead=1'b0;
SiguienteEstado=S0;
end
S5: begin //para el sw
ALUSrcB= 2'b00; //aqui
MemWrite=1'b1;
lorD= 1'b1;
SiguienteEstado=S0; // se acaba
end
S6: begin // del estado uno cuando es tipo registro
ALUSrcA= 1'b1; //execute
ALUSrcB= 2'b00;
ALUOp = 2'b10;
SiguienteEstado = S7;
end
S7: begin
RegDst= 1'b1;
RegWrite = 1'b1;
MemtoReg = 1'b0;
SiguienteEstado= S0; // se acaba
end
S8: begin
ALUSrcA= 1'b1;
ALUSrcB= 2'b00;
ALUOp=2'b01;
PCWriteCond= 1'b1;
PCSource = 2'b01;
SiguienteEstado= S0; // se acaba
11
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
end
S9: begin
PCWrite= 1'b1;
PCSource= 2'b10;
SiguienteEstado= S0; //se acaba
end
//estado para los opcode cuando la instruccion en inmediata
S10: begin
ALUSrcA= 1'b1;
ALUSrcB= 2'b10;
ALUOp = 2'b11;
SiguienteEstado = S11;
end
S11: begin
RegDst= 1'b0;
RegWrite = 1'b1;
MemtoReg = 1'b0;
SiguienteEstado = S0;
end
default:
SiguienteEstado = S0; //al fetch estado inicial
endcase
end
endmodule
/*
* InstrutionRegister.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module InstrutionRegister(
input clk,
input IRWrite,
input [31:0] dIn,
//output reg [1:0] port,
output reg[5:0] instruction,
output reg[4:0] rs,
output reg[4:0] rt,
output reg[4:0] rd,
output reg[10:0] shamtFunct //rd [15:11] shamt [10:6] funct [5:0] solo para R-type
);
12
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
always @(posedge clk)
begin
if (IRWrite)
begin
// port <= dIn[31:30];
instruction <= dIn[31:26];
/* if (dIn [10:6])
rs<=dIn [10:6];
else*/
rs<=dIn [25:21];
rt<=dIn [20:16];
rd<=dIn [15:11];
shamtFunct <= dIn [10:0];
end
end
endmodule
/*
* Mux2.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module Mux2(
input [4:0] In0,
input [4:0] In1,
input Sel,
output reg [4:0] Out
);
always @ (*)
begin
if (Sel) begin Out = In1; end
else begin Out = In0; end
end
endmodule
/*
* Shift2Left.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
13
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
*/
module Shift2Left(
input [25:0] DataIn,
output reg [27:0] DataOut
);
always@(*)
begin
DataOut = DataIn << 2; // multimplicacion por 4
end
endmodule
/*
* Shift2LeftUno.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module Shift2LeftUno(
input [31:0] DataIn,
output reg [31:0] DataOut
);
always@(*)
begin
DataOut = DataIn << 2; // multimplicacion por 4
end
endmodule
/*
* Shift2Right.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module Shift2Right(
input [31:0] DataIn,
output reg [31:0] DataOut
);
14
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
always@(*)
begin
DataOut = DataIn >> 2; // multiplicacion por 4
end
endmodule
/*
* Registros.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
//para los registros, A , B AluOut, Memory Data Register
module Registros(
input clk,
input reset,
input [31:0] dIn,
output reg [31:0] dOut
);
always @(posedge clk)
begin
if (!reset)
dOut<=dIn;
else
dOut<=0;
end
endmodule
/*
* PcCounter.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module PcCouter(
input Reset,
input Clk,
input [31:0] PCSiguiente,
15
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
input PcWrite,
output reg [31:0] PCActual
);
always @ (posedge Reset, posedge Clk)
begin
if (Reset)
PCActual <= 0;
else
if (PcWrite)
PCActual <= PCSiguiente;
end
endmodule
/*
* Mux2_31.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module Mux2_31(
input [31:0] In0,
input [31:0] In1,
input Sel,
output reg [31:0] Out
);
always @ (*)
begin
if (Sel) begin Out = In1; end
else begin Out = In0; end
end
endmodule
/*
* Mux2_31.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
16
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
/*
* uPMips.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
module uPMips(
input Reset,
input Clk,
input [31:0] PortIn,
output [31:0] PortOut
);
/* bloque registro Alu */
wire [31:0] wAluResult;
//wire [31:0] wAluResultReg;
/* bloque registro a b y MDR*/
wire [31:0] wMemData;
wire [31:0] wReadDataA;
wire [31:0] wReadDataB;
//wire [31:0] wA;
//wire [31:0] wB;
//wire [31:0] wMDRout;
/* bloque alu control*/
wire [1:0] wAluOp;
//wire [5:0] waddress; input
//wire [3:0] wAluOperacion; output
/* bloque alu*/
wire [31:0] wMux4Alu;
wire [31:0] wMux2Alu;
wire [3:0] wAluOperacion;
//wire wZero; output
//wire wAluResult; output
/* bloque RegisterFile*/
wire [4:0] wReadRegA; //wire [25:21] rs ;
17
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
wire [4:0] wReadRegB; //wire [20:16] rt ;
wire [4:0] wWriteRegister;
wire [31:0] wWriteData;
wire wRegWrite;
//wire [31:0] wReadDataA;
//wire [31:0] wReadDataB;
/* bloque Instruction Register*/
wire wIRWrite;
//wire [31:0] wMemData; entrada
//wire [5:0] wInstruccion, //wire wInstruccion [31:26];
//wire [4:0] wReadRegA; //wire [25:21] rs ; --//wire [4:0] wReadRegB; //wire [20:16] rt ;--//wire [15:0] waddress; wire waddress [15:0] ---
/* bloque Mux MuA , MuxMDR y MuxPC*/
wire [31:0] wPCActual;
wire [31:0] wA;
wire wAluSrcA;
//wire [31:0] wMux2Alu; --wire [31:0] wMDRout;
wire [31:0] wAluResultReg;
wire wMemtoReg;
//wire [31:0] wWriteData; ---//wire [31:0] wPCActual;
//wire [31:0] wAluResultReg; //entrada tambien
wire wlorD;
//wire [31:0] wMemAddress ;--wire wPCWriteCond;
wire wPcWrite;
wire wOr;
wire wAnd;
/* bloque PC counter*/
wire wZero;
assign wAnd = wPCWriteCond & wZero;
assign wOr = wAnd | wPcWrite;
//wire [31:0] wPcSiguienteDos;
wire [31:0] wPcSiguiente;
//wire [31:0] wPCActual;
18
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
/* bloque Mux B*/
wire [31:0] wB;
reg [31:0] RegCuatro = 32'h 00_00_00_04;
wire [31:0] wOutSignExt;
wire [31:0] wShiftUno;
wire [1:0] wAluSrcB;
//wire [31:0] wMux4Alu;
wire [15:0] waddress;
/* bloque Mux Shift Uno y Dos*/
//wire [31:0] wOutSignExt; // por que es la misma entrada al mux de cuatro
//wire [31:0] wShiftUno -wire [25:0] wConcatenado; //5
//5
//16
assign wConcatenado = {wReadRegA,wReadRegB,waddress};
//wire [28:0] wShiftDos
/* bloque Control */
//reg Clk;
//reg Reset;
wire [5:0] wInstruccion;
//wire [1:0] wAluSrcB;
/* bloque Mux Instruction Reg*/
//wire [4:0] wReadRegB; //wire [20:16] rt ; entrada
// wire [15:11] waddress ;
wire wRegDst;
/* bloque Memoria Ram Rom*/
wire wMemRead;
wire wMemWrite;
wire [31:0] wMemAddress ;
//wire [31:0] wMux4Alu; lo que le sale al registro B le entra a la memoria
//wire [31:0] wMemData; salida
/* bloque SignExtension */
//wire [15:0] waddress;
//wire [31:0] wOutSignExt; ---
19
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
/* bloque Mux Jump */
//wire [31:0] wAluResult;
//wire [31:0] wPcSiguiente;
wire [27:0] wShiftDos;
wire [1:0] wPcSource;
//wire [31:0] wMuxJump;
wire [31:0] wConcatenaJump;
assign wConcatenaJump = {wPCActual[31:28],wShiftDos};
/* bloque Shift2Right */
//wire [31:0] wPcCount;
wire [31:0] wPcSiguienteDos;
Shift2LeftUno inShift2LeftUnoUno(.DataIn(wOutSignExt),.DataOut(wShiftUno));
Shift2Left inShift2LeftDos(.DataIn(wConcatenado),.DataOut(wShiftDos));
Shift2Right inShift2RightUno(.DataIn(wPCActual),.DataOut(wPcSiguienteDos));
MuxCuatro Mux4_Jump(.AluSrcB(wPcSource),.InCero(wAluResult),.InUno(wAluResultReg),.InDos(wConcatenaJump),.InTres(0),.Out2Alu(wPcSiguiente));
PcCouter pcCounter(.Reset(Reset),.Clk(Clk),.PCSiguiente(wPcSiguiente),.PcWrite(wOr),.PCActual(wPCActual));
RegisterFile
RegFile(.Clk(Clk),.Reset(Reset),.PortIn(PortIn),.PortOut(PortOut),.RegWrite(wRegWrite),.ReadRegA(wReadRegA),.ReadRegB(wReadRegB),.WriteRegister(wWriteRegister),.W
riteData(wWriteData),.ReadDataA(wReadDataA),.ReadDataB(wReadDataB));
InstrutionRegister
InsReg(.clk(Clk),.IRWrite(wIRWrite),.dIn(wMemData),.instruction(wInstruccion),.rs(wReadRegA),.rt(wReadRegB),.rd(waddress[15:11]),.shamtFunct(waddress[10:0]));
//InstructionRegister InstReg(.clk(Clk),.IRWrite(wIRWrite),.dIn(wMemData),/*.port(),*/.instruction(wInstruccion),.rs(wReadRegA),.rt(wReadRegB),.address(waddress));
Mux2_31 Mux32_A(.In0(wPCActual),.In1(wA),.Sel(wAluSrcA),.Out(wMux2Alu));
Mux2_31 Mux32_MDR(.In0(wAluResultReg),.In1(wMDRout),.Sel(wMemtoReg),.Out(wWriteData));
Mux2_31 Mux32_PC(.In0(wPcSiguienteDos),.In1(wAluResultReg),.Sel(wlorD),.Out(wMemAddress));
MemoriaRamRom
Mem(.Clk(Clk),.MemRst(Reset),.MemAddress(wMemAddress),.WriteData(wMux4Alu),.MemWrite(wMemWrite),.MemRead(wMemRead),.MemData(wMemData));
MuxCuatro Mux4_B(.AluSrcB(wAluSrcB),.InCero(wB),.InUno(RegCuatro),.InDos(wOutSignExt),.InTres(wShiftUno),.Out2Alu(wMux4Alu));
SignExtend SignExtension(.InSignExt(waddress),.OutSignExt(wOutSignExt)); //done
Control Ctl(.Clk(Clk), .Reset(Reset), .Op(wInstruccion), .PCWriteCond(wPCWriteCond),.PCWrite(wPcWrite),
.lorD(wlorD),.MemRead(wMemRead),.MemWrite(wMemWrite),.MemtoReg(wMemtoReg), .IRWrite(wIRWrite),
.PCSource(wPcSource), .ALUOp(wAluOp),.ALUSrcB(wAluSrcB), .ALUSrcA(wAluSrcA),.RegWrite(wRegWrite),.RegDst(wRegDst));
Registros A(.clk(Clk),.reset(Reset),.dIn(wReadDataA),.dOut(wA)); //done
Registros B(.clk(Clk),.reset(Reset),.dIn(wReadDataB),.dOut(wB)); //done
20
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Registros AluOut(.clk(Clk),.reset(Reset),.dIn(wAluResult),.dOut(wAluResultReg)); // done
Registros MDR(.clk(Clk),.reset(Reset),.dIn(wMemData),.dOut(wMDRout)); //done
Alu alu(.Shampt(waddress[10:6]),.DatoInA(wMux2Alu),.DatoInB(wMux4Alu),.Operacion(wAluOperacion),.AluResult(wAluResult),.Zero(wZero)); // done
//Alu alu(.DatoInA(wMux2Alu),.DatoInB(wMux4Alu),.Operacion(wAluOperacion),.AluResult(wAluResult),.Zero(wZero)); // done
AluControl AluCtl(.Opcode(wInstruccion),.ALUOp(wAluOp),.Funct(waddress [5:0]),.Operacion(wAluOperacion)); //done
Mux2 muxInstReg(.In0(wReadRegB),.In1(waddress [15:11]),.Sel(wRegDst),.Out(wWriteRegister));
endmodule
/*
* TB_uPMips.v
*
* Created on: 06/11/2010
* Author: Ricardo Dávila Castro
*/
`timescale 1ns/100ps
module TB_uPMips;
reg Clk, Reset;
input [31:0] InPort
initial begin
Clk = 1'b0;
forever #5 Clk = ~Clk;
end
initial begin
Reset = 1'b0;
#3 Reset = ~Reset;
#20 Reset = ~Reset;
end
uPMips uMips(.Clk(Clk),.Reset(Reset),.PortIn(InPort));
endmodule
Simulaciones
21
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Datos e Instrucciones en la memoria
1.- ArrMemory[0] <= 32'h 1C_01_00_08; ADDI , SUMA INMEDIATA , CON EL REGISTRO BASE , EL CUAL TIENE UN
CERO. RD = RS + CONST16±
2.-ArrMemory[1] <= 32'h 8C_01_00_0D; //Load LW RT = MEM32(RS + OFF16±)
3.-ArrMemory[2] <= 32'h 8C_02_00_0E; // Load LW RT = MEM32(RS + OFF16±) *no es rd ya que rd toca los valores va de [15:11]
4.- ArrMemory[3] <= 32'h 00_41_18_20;
22
//Add RD = RS + RT
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
5.- ArrMemory[4] <= 32'h AC_23_00_15; //Store SW MEM32(RS + OFF16±) = RT
6.- ArrMemory[5] <= 32'h 00_41_20_22; //SUB RD = RS – RT
7.- ArrMemory[6] <= 32'h 00_41_28_24; //and 000000 00_010 00001 _00101000_00000000;
23
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Datos en memoria después de haber realizado un store la dirección en hexadecimal es x19 , en decimal es d25, como se puede apreciar
en la siguiente grafica de señales., Se demuestra que los datos e instrucciones fueron agregados correctamente.
24
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
En la siguiente figura se demuestra que se escribió en los registros correctos los valores de:
la suma 5+4 =9 .
la resta 5-4= 1
Op AND 5 & 4 = 4. , existe un gran tiempo de escritura entre el reg 3 y 4 , ya que en ese tiempo se realizo un store en la memoria.
(Los valores de los operadores y del resultado son presentados en formato Hexadecimal.)
8.- ArrMemory[7] <= 32'h 00_41_30_26;
25
//xor 000000 00_010 00001 _00110000_00000000;
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
9.- ArrMemory[8] <= 32'h 00_02_40_EE; //shift 000000xx xxxttttt dddddccc 1c101110
10.- ArrMemory[9] <= 32'h 00_02_38_67; //shift 000000xx xxxttttt dddddccc c1101110
Valores en los registros usados par a las operaciones:
26
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
11.- ArrMemory[11] <= 32'h 08_00_00_1C;
27
//jump
00001000 00000000 00000000 00000000
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
12.- ArrMemory[12] <= 32'h 10_A1_00_02;
28
//beq
000100ss sssttttt iiiiiiii
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
/*DATOS EN MEMORIA */
ArrMemory[13] <= 32'h 04; //DATO EN 0A LO ESCRIBE EN EL REG 1
ArrMemory[14] <= 32'h 05;
ArrMemory[15] <= 32'h 03; //sw
ArrMemory[16] <= 32'h 01;
ArrMemory[17] <= 32'h 15;
ArrMemory[28] <= 32'h 10_A1_00_02;
ArrMemory[31] <= 32'h 78;
29
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Reporte de Xilinis
Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to R:/Ricardo/uMipsXilins/uPMips/xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.34 secs
--> Parameter xsthdpdir set to R:/Ricardo/uMipsXilins/uPMips/xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.34 secs
--> Reading design: uPMips.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
30
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "uPMips.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device
: "uPMips"
: NGC
: xc3s500e-4-fg320
---- Source Options
Top Module Name
: uPMips
Automatic FSM Extraction
: YES
FSM Encoding Algorithm
: Auto
Safe Implementation
: No
FSM Style
: lut
RAM Extraction
: Yes
RAM Style
: Auto
ROM Extraction
: Yes
Mux Style
: Auto
Decoder Extraction
: YES
Priority Encoder Extraction
: YES
Shift Register Extraction
: YES
31
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Logical Shifter Extraction
: YES
XOR Collapsing
: YES
ROM Style
: Auto
Mux Extraction
: YES
Resource Sharing
: YES
Asynchronous To Synchronous
: NO
Multiplier Style
: auto
Automatic Register Balancing
: No
---- Target Options
Add IO Buffers
: YES
Global Maximum Fanout
: 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication
: YES
Slice Packing
: YES
Optimize Instantiated Primitives : NO
Use Clock Enable
: Yes
Use Synchronous Set
: Yes
Use Synchronous Reset
: Yes
Pack IO Registers into IOBs
: auto
Equivalent register Removal
: YES
---- General Options
Optimization Goal
Optimization Effort
Library Search Order
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
32
: Speed
:1
: uPMips.lso
: NO
: as_optimized
: Yes
: AllClockNets
: YES
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Write Timing Constraints
: NO
Cross Clock Analysis
: NO
Hierarchy Separator
:/
Bus Delimiter
: <>
Case Specifier
: maintain
Slice Utilization Ratio
: 100
BRAM Utilization Ratio
: 100
Verilog 2001
: YES
Auto BRAM Packing
: NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
*
HDL Compilation
*
=========================================================================
Compiling verilog file "../SignExtend.v" in library work
Compiling verilog file "../Shift2Right.v" in library work
Module <SignExtend> compiled
Compiling verilog file "../Shift2LeftUno.v" in library work
Module <Shift2Right> compiled
Compiling verilog file "../Shift2Left.v" in library work
Module <Shift2LeftUno> compiled
Compiling verilog file "../Registros.v" in library work
Module <Shift2Left> compiled
Compiling verilog file "../RegisterFile.v" in library work
Module <Registros> compiled
Compiling verilog file "../PcCounter.v" in library work
Module <RegisterFile> compiled
Compiling verilog file "../MuxCuatro.v" in library work
33
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Module <PcCouter> compiled
Compiling verilog file "../Mux2_31.v" in library work
Module <MuxCuatro> compiled
Compiling verilog file "../Mux2.v" in library work
Module <Mux2_31> compiled
Compiling verilog file "../MemoriaRamRom.v" in library work
Module <Mux2> compiled
Compiling verilog file "../InstrutionRegister.v" in library work
Module <MemoriaRamRom> compiled
Compiling verilog file "../Control.v" in library work
Module <InstrutionRegister> compiled
Compiling verilog file "../AluControl.v" in library work
Module <Control> compiled
Compiling verilog file "../Alu.v" in library work
Module <AluControl> compiled
Compiling verilog file "../uPMips.v" in library work
Module <Alu> compiled
Module <uPMips> compiled
No errors in compilation
Analysis of file <"uPMips.prj"> succeeded.
=========================================================================
*
Design Hierarchy Analysis
*
=========================================================================
Analyzing hierarchy for module <uPMips> in library <work>.
Analyzing hierarchy for module <Shift2LeftUno> in library <work>.
Analyzing hierarchy for module <Shift2Left> in library <work>.
34
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Analyzing hierarchy for module <Shift2Right> in library <work>.
Analyzing hierarchy for module <MuxCuatro> in library <work>.
Analyzing hierarchy for module <PcCouter> in library <work>.
Analyzing hierarchy for module <RegisterFile> in library <work> with parameters.
REG_ANCHO = "100000"
REG_LARGO = "100000"
Analyzing hierarchy for module <InstrutionRegister> in library <work>.
Analyzing hierarchy for module <Mux2_31> in library <work>.
Analyzing hierarchy for module <MemoriaRamRom> in library <work>.
Analyzing hierarchy for module <SignExtend> in library <work>.
Analyzing hierarchy for module <Control> in library <work> with parameters.
S0 = "0000"
S1 = "0001"
S10 = "1010"
S11 = "1011"
S2 = "0010"
S3 = "0011"
S4 = "0100"
S5 = "0101"
S6 = "0110"
S7 = "0111"
S8 = "1000"
S9 = "1001"
35
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Analyzing hierarchy for module <Registros> in library <work>.
Analyzing hierarchy for module <Alu> in library <work>.
Analyzing hierarchy for module <AluControl> in library <work> with parameters.
BRANCH = "10"
DATATRANSFER = "00"
IMMEDIATE = "11"
REGISTER = "01"
Analyzing hierarchy for module <Mux2> in library <work>.
=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing top module <uPMips>.
Module <uPMips> is correct for synthesis.
Analyzing module <Shift2LeftUno> in library <work>.
Module <Shift2LeftUno> is correct for synthesis.
Analyzing module <Shift2Left> in library <work>.
Module <Shift2Left> is correct for synthesis.
Analyzing module <Shift2Right> in library <work>.
Module <Shift2Right> is correct for synthesis.
Analyzing module <MuxCuatro> in library <work>.
Module <MuxCuatro> is correct for synthesis.
36
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Analyzing module <PcCouter> in library <work>.
Module <PcCouter> is correct for synthesis.
Analyzing module <RegisterFile> in library <work>.
REG_ANCHO = 6'b100000
REG_LARGO = 6'b100000
Module <RegisterFile> is correct for synthesis.
Analyzing module <InstrutionRegister> in library <work>.
Module <InstrutionRegister> is correct for synthesis.
Analyzing module <Mux2_31> in library <work>.
Module <Mux2_31> is correct for synthesis.
Analyzing module <MemoriaRamRom> in library <work>.
INFO:Xst:1607 - Contents of array <ArrMemory> may be accessed with an index that does not cover the full array size.
Module <MemoriaRamRom> is correct for synthesis.
Analyzing module <SignExtend> in library <work>.
Module <SignExtend> is correct for synthesis.
Analyzing module <Control> in library <work>.
S0 = 4'b0000
S1 = 4'b0001
S10 = 4'b1010
S11 = 4'b1011
S2 = 4'b0010
S3 = 4'b0011
S4 = 4'b0100
S5 = 4'b0101
37
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
S6 = 4'b0110
S7 = 4'b0111
S8 = 4'b1000
S9 = 4'b1001
WARNING:Xst:2725 - "../Control.v" line 60: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 77: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 96: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 106: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 111: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 118: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 124: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 130: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 136: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 144: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 150: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "../Control.v" line 156: Size mismatch between case item and case selector.
Module <Control> is correct for synthesis.
Analyzing module <Registros> in library <work>.
Module <Registros> is correct for synthesis.
Analyzing module <Alu> in library <work>.
Module <Alu> is correct for synthesis.
Analyzing module <AluControl> in library <work>.
BRANCH = 2'b10
DATATRANSFER = 2'b00
IMMEDIATE = 2'b11
REGISTER = 2'b01
Module <AluControl> is correct for synthesis.
38
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Analyzing module <Mux2> in library <work>.
Module <Mux2> is correct for synthesis.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Shift2LeftUno>.
Related source file is "../Shift2LeftUno.v".
WARNING:Xst:647 - Input <DataIn<31:30>> is never used. This port will be preserved and left unconnected if it belongs to a toplevel block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Shift2LeftUno> synthesized.
Synthesizing Unit <Shift2Left>.
Related source file is "../Shift2Left.v".
Unit <Shift2Left> synthesized.
Synthesizing Unit <Shift2Right>.
Related source file is "../Shift2Right.v".
WARNING:Xst:647 - Input <DataIn<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level
block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Shift2Right> synthesized.
Synthesizing Unit <MuxCuatro>.
Related source file is "../MuxCuatro.v".
39
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Found 32-bit 4-to-1 multiplexer for signal <Out2Alu>.
Summary:
inferred 32 Multiplexer(s).
Unit <MuxCuatro> synthesized.
Synthesizing Unit <PcCouter>.
Related source file is "../PcCounter.v".
Found 32-bit register for signal <PCActual>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <PcCouter> synthesized.
Synthesizing Unit <RegisterFile>.
Related source file is "../RegisterFile.v".
WARNING:Xst:647 - Input <PortIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block
or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 32-bit 32-to-1 multiplexer for signal <ReadDataA>.
Found 32-bit 32-to-1 multiplexer for signal <ReadDataB>.
Found 32-bit tristate buffer for signal <PortOut>.
Found 1024-bit register for signal <RegFile>.
Found 32-bit 4-to-1 multiplexer for signal <RegFile_0$mux0000>.
INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <RegFile>. You may be trying to describe a RAM in a way
that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not
supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of
RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
inferred 1024 D-type flip-flop(s).
inferred 96 Multiplexer(s).
40
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
inferred 32 Tristate(s).
Unit <RegisterFile> synthesized.
Synthesizing Unit <InstrutionRegister>.
Related source file is "../InstrutionRegister.v".
Found 6-bit register for signal <instruction>.
Found 5-bit register for signal <rd>.
Found 5-bit register for signal <rs>.
Found 5-bit register for signal <rt>.
Found 11-bit register for signal <shamtFunct>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <InstrutionRegister> synthesized.
Synthesizing Unit <Mux2_31>.
Related source file is "../Mux2_31.v".
Unit <Mux2_31> synthesized.
Synthesizing Unit <MemoriaRamRom>.
Related source file is "../MemoriaRamRom.v".
Found 32-bit 64-to-1 multiplexer for signal <$varindex0000> created at line 46.
Found 2048-bit register for signal <ArrMemory>.
Found 32-bit comparator lessequal for signal <ArrMemory_0$cmp_le0000> created at line 39.
INFO:Xst:738 - HDL ADVISOR - 2048 flip-flops were inferred for signal <ArrMemory>. You may be trying to describe a RAM in a
way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not
supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of
RAM resources will lead to improved device usage and reduced synthesis time.
Summary:
41
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
inferred 2048 D-type flip-flop(s).
inferred 1 Comparator(s).
inferred 32 Multiplexer(s).
Unit <MemoriaRamRom> synthesized.
Synthesizing Unit <SignExtend>.
Related source file is "../SignExtend.v".
Unit <SignExtend> synthesized.
Synthesizing Unit <Control>.
Related source file is "../Control.v".
Found finite state machine <FSM_0> for signal <EstadoActual>.
----------------------------------------------------------------------| States
| 12
|
| Transitions
| 23
|
| Inputs
|9
|
| Outputs
| 15
|
| Clock
| Clk (rising_edge)
|
| Reset
| Reset (positive)
|
| Reset type
| synchronous
|
| Reset State
| 00000
|
| Power Up State | 00000
|
| Encoding
| automatic
|
| Implementation | LUT
|
----------------------------------------------------------------------Summary:
inferred 1 Finite State Machine(s).
Unit <Control> synthesized.
42
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Synthesizing Unit <Registros>.
Related source file is "../Registros.v".
Found 32-bit register for signal <dOut>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <Registros> synthesized.
Synthesizing Unit <Alu>.
Related source file is "../Alu.v".
Found 32-bit addsub for signal <AluResult$addsub0000>.
Found 32-bit shifter logical right for signal <AluResult$shift0000> created at line 22.
Found 32-bit shifter logical left for signal <AluResult$shift0001> created at line 23.
Found 32-bit xor2 for signal <AluResult$xor0000> created at line 14.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 2 Combinational logic shifter(s).
Unit <Alu> synthesized.
Synthesizing Unit <AluControl>.
Related source file is "../AluControl.v".
WARNING:Xst:647 - Input <Opcode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block
or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 4-bit 4-to-1 multiplexer for signal <Operacion>.
Summary:
inferred 4 Multiplexer(s).
Unit <AluControl> synthesized.
43
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Synthesizing Unit <Mux2>.
Related source file is "../Mux2.v".
Unit <Mux2> synthesized.
Synthesizing Unit <uPMips>.
Related source file is "../uPMips.v".
WARNING:Xst:653 - Signal <RegCuatro> is used but never assigned. This sourceless signal will be automatically connected to value
00000000000000000000000000000100.
Unit <uPMips> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same
physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
32-bit addsub
# Registers
11-bit register
32-bit register
5-bit register
6-bit register
# Comparators
32-bit comparator lessequal
# Multiplexers
32-bit 32-to-1 multiplexer
32-bit 4-to-1 multiplexer
32-bit 64-to-1 multiplexer
44
:1
:1
: 106
:1
: 101
:3
:1
:1
:1
:7
:2
:3
:1
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
4-bit 4-to-1 multiplexer
# Logic shifters
32-bit shifter logical left
32-bit shifter logical right
# Tristates
32-bit tristate buffer
# Xors
32-bit xor2
:1
:2
:1
:1
:1
:1
:1
:1
=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <Ctl/EstadoActual/FSM> on signal <EstadoActual[1:4]> with gray encoding.
------------------State | Encoding
------------------00000 | 0000
00001 | 0001
00010 | 0101
00011 | 1100
00100 | 1101
00101 | 0100
00110 | 0111
00111 | 1111
01000 | 0110
01001 | 0010
01010 | 0011
45
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
01011 | 1110
------------------Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\10.1\ISE.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
32-bit addsub
# Registers
Flip-Flops
# Comparators
32-bit comparator lessequal
# Multiplexers
1-bit 32-to-1 multiplexer
32-bit 4-to-1 multiplexer
32-bit 64-to-1 multiplexer
4-bit 4-to-1 multiplexer
# Logic shifters
32-bit shifter logical left
32-bit shifter logical right
# Xors
32-bit xor2
:1
:1
: 3268
: 3268
:1
:1
: 69
: 64
:3
:1
:1
:2
:1
:1
:1
:1
=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
46
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Optimizing unit <uPMips> ...
Optimizing unit <PcCouter> ...
Optimizing unit <InstrutionRegister> ...
Optimizing unit <MemoriaRamRom> ...
Optimizing unit <Registros> ...
Optimizing unit <Alu> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uPMips, actual ratio is 69.
FlipFlop Ctl/EstadoActual_FSM_FFd1 has been replicated 1 time(s)
FlipFlop Ctl/EstadoActual_FSM_FFd2 has been replicated 3 time(s)
FlipFlop Ctl/EstadoActual_FSM_FFd3 has been replicated 2 time(s)
FlipFlop Ctl/EstadoActual_FSM_FFd4 has been replicated 2 time(s)
FlipFlop InsReg/rd_4 has been replicated 1 time(s)
FlipFlop InsReg/rs_0 has been replicated 1 time(s)
FlipFlop InsReg/rt_0 has been replicated 1 time(s)
FlipFlop InsReg/shamtFunct_10 has been replicated 1 time(s)
FlipFlop InsReg/shamtFunct_6 has been replicated 1 time(s)
FlipFlop InsReg/shamtFunct_7 has been replicated 1 time(s)
FlipFlop InsReg/shamtFunct_8 has been replicated 1 time(s)
FlipFlop InsReg/shamtFunct_9 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
47
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Final Register Report
Macro Statistics
# Registers
Flip-Flops
: 3284
: 3284
=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name : uPMips.ngr
Top Level Output File Name
: uPMips
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: NO
Design Statistics
# IOs
48
: 66
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Cell Usage :
# BELS
#
BUF
#
GND
#
LUT2
#
LUT2_D
#
LUT2_L
#
LUT3
#
LUT3_D
#
LUT3_L
#
LUT4
#
LUT4_D
#
LUT4_L
#
MUXCY
#
MUXF5
#
MUXF6
#
MUXF7
#
MUXF8
#
VCC
#
XORCY
# FlipFlops/Latches
#
FDCE
#
FDE
#
FDR
#
FDRE
#
FDRS
#
FDSE
# Clock Buffers
#
BUFGP
# IO Buffers
49
: 5296
:1
:1
: 41
:5
:1
: 2284
: 26
: 28
: 665
: 52
: 63
: 40
: 1160
: 512
: 256
: 128
:1
: 32
: 3284
: 32
: 2472
: 128
: 536
: 12
: 104
:1
:1
: 33
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
#
IBUF
:1
#
OBUFT
: 32
=========================================================================
Device utilization summary:
--------------------------Selected Device : 3s500efg320-4
Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of IOs:
Number of bonded IOBs:
Number of GCLKs:
3277 out of 4656 70%
3284 out of 9312 35%
3165 out of 9312 33%
66
34 out of 232 14%
1 out of 24 4%
--------------------------Partition Resource Summary:
--------------------------No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
50
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Clk
| BUFGP
| 3284 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
--------------------------------------------------------------------------+----------------------------+-------+
Control Signal
| Buffer(FF name)
| Load |
-----------------------------------+----------------------------+-------+
Reset_IBUF_1(Reset_IBUF_1:O)
| NONE(pcCounter/PCActual_24)| 32
-----------------------------------+----------------------------+-------+
|
Timing Summary:
--------------Speed Grade: -4
Minimum period: 16.106ns (Maximum Frequency: 62.087MHz)
Minimum input arrival time before clock: 9.285ns
Maximum output required time after clock: 11.105ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================
51
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Timing constraint: Default period analysis for Clock 'Clk'
Clock period: 16.106ns (frequency: 62.087MHz)
Total number of paths / destination ports: 1818574 / 6440
------------------------------------------------------------------------Delay:
16.106ns (Levels of Logic = 10)
Source:
Ctl/EstadoActual_FSM_FFd4_1 (FF)
Destination:
pcCounter/PCActual_31 (FF)
Source Clock:
Clk rising
Destination Clock: Clk rising
Data Path: Ctl/EstadoActual_FSM_FFd4_1 to pcCounter/PCActual_31
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDRS:C->Q
11 0.591 1.108 Ctl/EstadoActual_FSM_FFd4_1 (Ctl/EstadoActual_FSM_FFd4_1)
LUT4_D:I0->O
21 0.704 1.132 Mux4_B/Mmux_Out2Alu2101_1 (Mux4_B/Mmux_Out2Alu2101)
LUT4:I3->O
67 0.704 1.277 Mux4_B/Mmux_Out2Alu191 (wMux4Alu<26>)
LUT4:I3->O
1 0.704 0.424 alu/AluResult<26>50_SW0 (N4311)
LUT4_D:I3->O
1 0.704 0.424 alu/AluResult<26>50 (alu/AluResult<26>50)
LUT4:I3->O
1 0.704 0.455 alu/AluResult<26>206_SW0 (N333)
LUT4:I2->O
1 0.704 0.424 alu/AluResult<26>105_SW0 (N253)
LUT4:I3->O
3 0.704 0.535 alu/AluResult<26>234 (wAluResult<26>)
LUT4:I3->O
1 0.704 0.424 wOr159 (wOr159)
LUT4:I3->O
1 0.704 0.455 wOr173 (wOr173)
LUT4:I2->O
32 0.704 1.262 wOr203 (wOr)
FDCE:CE
0.555
pcCounter/PCActual_0
---------------------------------------Total
16.106ns (8.186ns logic, 7.920ns route)
(50.8% logic, 49.2% route)
=========================================================================
52
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Total number of paths / destination ports: 2220 / 2220
------------------------------------------------------------------------Offset:
9.285ns (Levels of Logic = 4)
Source:
Reset (PAD)
Destination:
Mem/ArrMemory_63_31 (FF)
Destination Clock: Clk rising
Data Path: Reset to Mem/ArrMemory_63_31
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
408 1.218 1.381 Reset_IBUF (Reset_IBUF)
BUF:I->O
409 0.704 1.460 Reset_IBUF_1 (Reset_IBUF_1)
LUT4_D:I1->O
31 0.704 1.297 Mem/ArrMemory_32_not000111 (Mem/N0)
LUT4:I2->O
32 0.704 1.262 Mem/ArrMemory_63_not00011 (Mem/ArrMemory_63_not0001)
FDE:CE
0.555
Mem/ArrMemory_63_0
---------------------------------------Total
9.285ns (3.885ns logic, 5.400ns route)
(41.8% logic, 58.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Total number of paths / destination ports: 832 / 32
------------------------------------------------------------------------Offset:
11.105ns (Levels of Logic = 5)
Source:
Ctl/EstadoActual_FSM_FFd4 (FF)
Destination:
PortOut<31> (PAD)
Source Clock:
Clk rising
Data Path: Ctl/EstadoActual_FSM_FFd4 to PortOut<31>
53
Departamento de Electrónica, Sistemas e Informática (DESI)
EDCI G5 Diseño Digital II
Mariano Aguirre
Ricardo Dávila Castro
Gate Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDRS:C->Q
21 0.591 1.303 Ctl/EstadoActual_FSM_FFd4 (Ctl/EstadoActual_FSM_FFd4)
LUT3_D:I0->LO
1 0.704 0.275 Ctl/EstadoActual_FSM_Out51 (N852)
LUT3:I0->O
4 0.704 0.762 muxInstReg/Out<2>1 (wWriteRegister<2>)
LUT4:I0->O
9 0.704 0.824 RegFile/RegFile_30_and000011 (N13)
LUT4:I3->O
32 0.704 1.262 RegFile/RegFile_30_and0000_inv1 (RegFile/RegFile_30_and0000_inv)
OBUFT:T->O
3.272
PortOut_31_OBUFT (PortOut<31>)
---------------------------------------Total
11.105ns (6.679ns logic, 4.426ns route)
(60.1% logic, 39.9% route)
=========================================================================
Total REAL time to Xst completion: 99.00 secs
Total CPU time to Xst completion: 98.67 secs
-->
Total memory usage is 279608 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 18 ( 0 filtered)
Number of infos : 4 ( 0 filtered)
54
Departamento de Electrónica, Sistemas e Informática (DESI)