Lecture12.1 Copper Deposition (SemiTool)

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Copper Damascene Plating
1/5/06
Brandon Brooks
Process Development Engineer
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Outline
•Why Cu Interconnects?
•Damascene Process Flow
•Parameters Affecting Cu Interconnects
•Backside Clean and Bevel Etch
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Damascene Plating?
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Why Cu Interconnects?
Interconnect Metal Properties
Al
Cu
W
Melting Pt (°C)
660
1,083
3,410
Oxidation in Air
Rapid; Self-Sealing
Slow; Not Self-Sealing
Inert
2.82
1.77
5.6
3.0-3.3*
1.8-2.0
8-11
Self-Diffusion Coefficient (cm2s-1) @ 100 °C
2.1·10-20
2.1·10-30
Coefficient of Thermal Expansion (Unit/°C)
24·10-6
17·10-6
Resistivity (mW-cm)
Crystalline
As Deposited
* Alloy (Si, Cu)
Best!
Al
Cu
 Resistivity
 Melting Point
Thermal Expansion
 Electromigration
 Resistivity
 Melting Point
Thermal Expansion
 Electromigration
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4.3·10-6
Why Cu Interconnects?
Interconnect Metal Properties
Etch Properties
Etch Rate (Å/min)
Al
Cu
Ag
Cl & Br Plasmas
Cl & Br Plasmas
F & Cl Plasmas
5,000
500
5,000
Cu has a very slow etch rate
•Cu halides are solid at normal temperatures
Changing from Al to Cu interconnects requires new process flow
•Enter Damascene plating
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Damascene Process Flow
Typical Damascene Process Flow
1. Dielectric Deposition
2. Photoresist Deposition
3. UV Exposure
Today’s Main Topics
4. Develop Photoresist
5. Etch Dielectric
6. Remove Photoresist
7. Barrier Deposition
8. Seed Layer Deposition
9. Electrochemical Deposition (ECD)
10. Backside Clean and Bevel Etch
11. Anneal
12. Chemical Mechanical Polish (CMP)
13. Repeat Steps 1-10 for Every Metal Layer
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Damascene Process Flow
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Copper Interconnect Parameters
Key Factors Affecting Cu Interconnect Performance
1.
2.
3.
4.
Gap-Fill
CD Uniformity
Overburden
Anneal
AMD’s 9 Cu Levels
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Copper Interconnect Parameters: Gap-Fill
Key Parameters for Gap-Fill
1. Seed and Barrier Layers
1.
2.
Uniformity
Thickness
2. Plating Recipe
1.
2.
3.
Hot Start (Initiation)
Fill Current Density
Waveform
3. Plating Chemistry
1.
2.
Inorganic
Organic
0.12m, 8.3:1AR Trenches
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Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layers
Physical Vapor Deposition (PVD) Effects
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Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layer Uniformity
Edge Shadowing
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Optimized Seed Layer
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Copper Interconnect Parameters: Gap-Fill
Seed and Barrier Layer Thickness
0.30micron, 4.8:1 AR Vias
1500Å Total Seed Thickness
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0.30micron, 4.8:1 AR Vias
2000Å Total Seed Thickness
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Copper Interconnect Parameters: Gap-Fill
Plating Recipe Hot Start
2X Fill Rate on the 2V Hot Start
No Hot Start
2V Hot Start
0.180 m Line Width Trenches
48 Coulombs ECD
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Copper Interconnect Parameters: Gap-Fill
Plating Recipe Current Density
The Effect of Current Density upon Gap Fill
Optimum Fill
for feature D
Good
Current too Low
0.35μm, 4.3:1 AR Vias
Gap Fill
0.35μm, 4.3:1 AR Vias
Optimum Current
Bad
Low
0.18μm, 5.1:1 AR Trench
High
Current Density
Optimum Current
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0.18μm, 5.1:1 AR Trench
Current too High
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Copper Interconnect Parameters: Gap-Fill
Plating Recipe Waveform
Waveform
Cu Diffusion Additive Adsorption Bottom Up Fill
Direct Current (DC)
-
+
0
Pulse DC
+
-
0
Pulse Reverse (PR)
+
-
0
DC plating provides better additive adsorption
Pulsed plating provides better Cu diffusion
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Copper Interconnect Parameters: Gap-Fill
Plating Chemistry
Inorganic Components
Organic Components
1. Copper Sulfate (CuSO4)
2. Hydrochloric Acid (HCl)
3. Sulfuric Acid (H2SO4)
1. Suppressor (PEG)
2. Accelerator (SPS)
3. Leveler (Amine)
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Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
Low Copper
Copper Effect on Gap Fill
High Copper
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Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
-
Cl Effect on Suppressor
20
18
Chloride Effect on Gap-Fill
14
12
10
G ood
8
6
4
2
0
0
50
100
150
200
Cl Concentration ppm
Gap Fill
CVS Stripping
Peak Area (mC)
16
Bad
Low
H igh
Chloride (ppm )
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Copper Interconnect Parameters: Gap-Fill
Inorganic Plating Chemistry
pH 3
Acid Effect on Gap Fill
Good
Gap Fill
pH 2
pH 2
Bad
Low
High
Acid (g/l)
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Organic Effect on Gap Fill
• Accelerator
– Catalytic effect
– Requires very small amount of Cl– Increased current for a given potential
• Suppressor
– Suppresses deposition
– Requires Cl- to adsorb onto copper surface
– Decreases current for a given potential
• Leveler
– Suppresses deposition at high current density areas
– Very low concentration (diffusion limited)
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
Cyclic Voltammetric Stripping Analysis (CVS)
Stripping Region
A
A = VMS
I
B = VMS + Suppressor
C = VMS + Sup. & Accel.
Plating Region
C
B
V
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Copper Interconnect Parameters: Gap-Fill
Better
Worse
Organic Plating Chemistry
0.3
High Acid
150 g/l
30
Stripping Area
Stripping Area
25
0.2
Low Acid
(10g/l)
0.1
Worse
Better
High Acid
150 g/l
0
0.01 0.02 0.03 0.04 0.05
80 g/l H2SO4
10
0
0
1
2
3
Accelerator
Concentration
Suppressor
Concentration
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5
80 g/l
0
20
22
4
5
Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: Gap-Fill
Organic Plating Chemistry
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Copper Interconnect Parameters: CD Uniformity
Key Parameters for Current Density Uniformity
1. Chemistry
1.
2.
High Acid
Low Acid
2. CFD Reactor
1.
Electric Field Control
Intel: 8 Cu Levels
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Copper Interconnect Parameters: CD Uniformity
Generalized Electrochemical Schematic
Electrolytic Copper Deposition
Ammeter
V0
+
Current Density = Current
Surf. Area
Current Path
e- e-
e- e-
Electrolyte
Cu2+
Cu2+
Surface
Area
Cu0  Cu2++2e-
Cu2++2e-  Cu0
Anode
(Oxidation)
Cathode
(Reduction)
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Copper Interconnect Parameters: CD Uniformity
I edge
V

R elec
I center
Rcat
V

(R elec  R cat )
Cathode
(Thin)
Rcat  1/Seed Thickness
Rcat  Wafer Radius
= Surface
= AreaArea
Relec
Relec
Relec  1/Bath Conductivity
V
+
Electrolyte
Ranode= 0
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Anode
(Thick)
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Copper Interconnect Parameters: CD Uniformity
I edge  I center  I EC 
VRcat
Relec ( Relec  Rcat )
How To Make I EC Small?
Rcat
Cathode (Thin)
V
Current Density
Throughput
Rcat
Relec
Relec
V
+
Edge
I Loop
Center
I Loop
Electrolyte
Seed Layer Thickness
Wafer Radius
Relec
Ranode= 0
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Anode (Thick)
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Bath Conductivity
Copper Interconnect Parameters: CD Uniformity
Conductivity at Various Bath Conditions
Conductivity (mS/cm)
600
“High” Acid
500
400
511
300
200
100
“Low” Acid
247
70
0
10 g/l H2SO4
80 g/l H2SO4
175 g/l H2SO4
50 g/l Cu
50 g/l Cu
17 g/l Cu
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Copper Interconnect Parameters: CD Uniformity
Terminal Effect
0sec
Current Density
Plating Time
5sec
15sec
30sec
60sec
120sec
(0,0)
Wafer Radius
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Copper Interconnect Parameters: CD Uniformity
The Effect of Current Density upon Gap Fill
Optimum Fill
for feature D
Good
Current too Low
0.35mm, 4.3:1 AR Vias
Gap Fill
0.35mm, 4.3:1 AR Vias
Optimum Current
Bad
Low
0.18mm, 5.1:1 AR Trench
High
Current Density
Optimum Current
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0.18mm, 5.1:1 AR Trench
Current too High
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Copper Interconnect Parameters: CD Uniformity
Are the center and edge
receiving the same process?
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Copper Interconnect Parameters: CD Uniformity
Advanced Reactor Design: Multiple Anodes
Robust system that can handle multiple chemistries
Built for the future with the ability to handle shrinking die size
Cost effective ability to handle increasing wafer diameters
V1 and V2 adjusted until I EC  0 Independent of Rc and Relec
Cathode
+
V1
+
Anode
2
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Anode
1
37
V2
Copper Interconnect Parameters: CD Uniformity
Conventional Reactor
CFD Reactor
Wafer
Virtual
Anodes
Electrolyte
Dielectric
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Physical
Anodes
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Electrolyte
Copper Interconnect Parameters: CD Uniformity
Rotating Wafer
Overflow
Virtual Anode
Electrolyte
Bubble Trap
Dielectric
Concentric
Annular Anodes
Flow Inlet
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Copper Interconnect Parameters: CD Uniformity
Superposition of Electric Field
Normalized Voltage at Cathode (V)
Summed Field
Anode 2
Anode 3
Anode 4
-120
-100
-80
-60
-40
-20
0
20
Wafer Diameter (mm)
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40
40
60
80
Anode 1
100
120
Copper Interconnect Parameters: CD Uniformity
100 nm Seed layer, 1m deposition
SEMITOOL - CFD
Current Density (mA/cm^2)
511mS/cm
High Acid
Conventional
0sec
34
133%
30
<5%
5sec
15sec
30sec
60sec
120sec
26
22
18
Current Density (mA/cm^2)
70mS/cm
Low Acid
14
34
20%
30
<5%
26
0sec
22
18
120sec
14
0
25
50
75
100
125
150
0
25
Wafer Radius (mm)
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50
75
100
125
150
Copper Interconnect Parameters: CD Uniformity
Anode Current (Amps)
Dynamic Compensation for Constant Current Density
2.5
Anode 1
Anode 3
2.0
Anode 4
1.5
Anode 2
1.0
0
20
40
60
80
Deposition Time (sec)
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100
120
Copper Interconnect Parameters: Overburden
Key Parameters for Overburden
A. Local Overburden (Overplating) – Fill Step
1.
Chemistry
1.
2.
2.
3-Component
2-Component
Waveform
1. Direct Current
2. Pulse Reverse
B. Global Overburden – Cap Step
1.
Chemistry
1.
2.
2.
High Acid
Low Acid
CFD Reactor
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Copper Interconnect Parameters: Local Overburden
Step Up
No Step Up
Pulse Reverse POR
Direct Current POR
2-Component Organic Package
High Acid Electrolyte
3-Component Organic Package
Moderate Acid Electrolyte
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Copper Interconnect Parameters: Local Overburden
Insufficient Leveler
Overplating
Post-CMP Residual Cu
Optimized Organic Conditions
No Post-CMP Residual Cu
Planar Deposition
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Copper Interconnect Parameters: Global Overburden
Radial control of
Thickness Variation (Å)
Cu Thickness (Å)
800Å
600
400
200
0
-200
-400
-600
-800
-100mm
0
Wafer Diameter (mm)
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100
Copper Interconnect Parameters: Global Overburden
Thickness (A)
Raider CFD Profile Before & After 30s CMP
16,000
12,000
CFD Profile before CMP
8,000
4,000
Uniform Post-CMP Profile
Profile after 30s CMP
Thickness (A)
POR Profile Before & After 30s CMP
16,000
12,000
POR Profile before CMP
8,000
Profile after 30s CMP
4,000
Edge
Residual!
Wafer Diameter
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Early
Clearing!
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Copper Interconnect Parameters: Global Overburden
Normalized Thickness
CMP Profile Matching
1.1
1.08
1.06
1.04
1.02
1
0.98
0.96
-150
-100
-50
0
50
Wafer Radius (mm)
ECD Profile
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CMP Profile
48
100
150
Copper Interconnect Parameters: Anneal
Key Parameters for Anneal
1.
2.
3.
Temperature
Feature Size
Barrier Layer
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Copper Interconnect Parameters: Anneal
Effect of Temperature
As Deposited
Small Grains
Self Annealed
Large Grains
Thermally Annealed
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Copper Interconnect Parameters: Anneal
Effect of Feature Size
1.0m
Trenches
0.25m
Trenches
Furnace Anneal
Self-Anneal
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Copper Interconnect Parameters: Anneal
Effect of Barrier Layer
Ta Barrier Layer
•Strong Surface Interaction
•Reduced Migration
TiNx Barrier Layer
•Weak Surface Interaction
•Increased Migration
•Large Voids
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Copper Interconnect Parameters: Anneal
Optimum Anneal Condition
TiNx
Ta
TaNx
Grain
Growth
Void
Formation
Optimum
Anneal Temp
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Backside Clean and Bevel Etch
Why Backside Clean and Bevel Etch?
• Cu is a highly mobile ion
• Backside contamination can have adverse effects across the fab
• Unstable films on the edge of the wafer can cause surface damage at CMP
Objective
1.
Remove bulk Cu on the edge of the wafer
1.
2.
3.
2.
Delamination
Flaking
Yield Problems
Remove atomic Cu on the back of the wafer
1.
2.
3.
Common Photolithography
Common Metrology
Cu ion diffusion
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Backside Clean and Bevel Etch
Capsule 1 Chamber Cut Away
Capsule 1 Features
1.
2.
3.
4.
5.
Hardware control of bevel etch (BE)
0-4mm BE edge exclusion (EE) range
No front side protection needed
BE & backside clean simultaneously
Clean N2 purged microenvironment
Edge Exclusion Hardware
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Backside Clean and Bevel Etch
Capsule Dynamics
Front Side Inlet:
-DI H2O
-N2
Chamber Rotation
Wafer
Device Up
Seal
Back Side Inlet:
-Dilute Piranha Solution
-DI H2O
-N2
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Backside Clean and Bevel Etch
Capsule Dynamics
Front Side Inlet:
-DI H2O
-N2
Chamber Rotation
Wafer
Device Up
Seal
Back Side Inlet:
-Dilute Piranha Solution
-DI H2O
-N2
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Backside Clean and Bevel Etch
Precision Control of Chemical Wrap-Around
A concentric 1.5mm EE BE clears the notch
Critical Bevel Etch Parameters
1.
2.
3.
Concentricity
Complete Cu Clearing
Clearing the Notch
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Backside Clean and Bevel Etch
Precision Control of Concentricity
Concentricity Spec (a) ≤ 0.2mm
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Backside Clean and Bevel Etch
Precision Control of Copper Removal
No Copper on Edge Exclusion Zone
52º Tilt on SEM
No undercut
Target ECD 1.0µm
E Beam Spot
Magn
WD
10.0kV
3500x
17.1
2.0
10 µm
STI. Bevel Etch
1 µm ECD Copper
1.5 mm Edge Exclusion
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Profilometer Reading
<10 µm
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Summary
Why Cu Interconnects?
•Resistivity
•Reliability
Damascene Process Flow
•Photolithography to CMP
Parameters Affecting Cu Interconnects
•Gap-Fill
•Current Density Uniformity
•Overburden
•Anneal
•Backside Clean and Bevel Etch
•Bulk Cu on the Edge
•Atomic Cu on the Backside
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Acknowledgements
John Klocke – Cu Damascene Group Leader
Kevin Witt – Cu Damascene Business Development Leader
Tom Ritzdorf – Director of ECD Technology
Jake Cook – Marketing Communications
All Semitool personnel that have contributed data to this presentation
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