IP FLows over Optical and Wireless
“IP-FLOW”
UTC-based / Banyan-based
Switch and Wi-Fi Prototype
This work was supported in part by funds
from the European Commission (contract N° 002807)
Marie Curie Chairs (EXC)
prof. Yoram Ofek - DIT - University di Trento
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Participants
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Mario Baldi – Politecnico di Torino
(Michele Corra – Universita' di Trento)
Giorgio Fontana – Universita' di Trento
Renato LoCigno – Universita' di Trento
Yoram Ofek – Universita' di Trento
Danilo Severina – Universita' di Trento
Prof. Giovanni Soncini – Universita' di Trento
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(Deepak Agrawal – Universita' di Trento)
Paolo Larcheri – Universita' di Trento
Truong Thu Huong – Universita' di Trento
Guido Marchetto – Politecnico di Torino
Viet-Thang Nguyen – Universita' di Trento
Olga Zadedyurina – Universita' di Trento
prof. Yoram Ofek - DIT - University di Trento
2
Agenda
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Project overview and prototype-testbed objectives – Yoram Ofek – Universita' di Trento
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Terabit switch prototype – Giorgio Fontana – Universita' di Trento
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Terabit switch control plan and signaling – Michele Corra, Viet-Thang Nguyen – Universita' di Trento
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Torino software-based time-driven priority switch – Guido Marchetto, Mario Baldi - Politecnico di Torino
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Using Symmetricom GPS time card – Guido Marchetto – Politecnico di Torino
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GE to terabit switch interface – Truong Thu Huong – Universita' di Trento
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Terabit switch to wireless interface – Paolo Larcheri – Universita' di Trento
prof. Yoram Ofek - DIT - University di Trento
3
General Guidelines
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General prototype meeting at least every 3-month
Credit for all principle
Prototype activities is only part of a more general research activities
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Objective:
 To have some prototype demonstration by July, then
 To use the prototype to obtain more funding to expand:
 To connect Trento and Torino
 To develop and implement optoelectronic switching fabric
 To develop and implement GMPLS control plane
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Other activities: web page, papers, seminars, …
prof. Yoram Ofek - DIT - University di Trento
4
Prototype Functional Structure
UTC
UTC
UTC
(2)
(3)
UTC-based
Switch Controller
(3)
(4)
Wi-Fi
w/Smart
Antenna
UTC-based
(1)
GE
Network
Interface
Switching
Fabric
Prototype
UTC-based
GE Network
Interface
(4)
Wi-Fi
w/Smart
Antenna
(5)
(6) EPON
Optional extensions:
(5) Satellite interface
(6) Ethernet Passive Optical Network - EPON
prof. Yoram Ofek - DIT - University di Trento
5
Prototype Activity Chart
SW Responsible Person
Danilo
HW Responsible Person
Giorgio
UTC
UTC
(3)
(4) Wi-Fi w/Smart
Antenna:
UTC-based
Network Interface:
(2)
Giorgio, Nguyen, (Deepak, Michele)
GE:
Danilo, Paolo
12 Project – WL QoS
Danilo, Guido,
Paolo, Truong
UTC-based Switch Controller:
Giorgio,
Olga
(1)
Switching Fabric Prototype:
Giorgio, Olga
Torino NetGroup
Time-drive Priority
Main Demonstration: Streaming of Audio and Video
Flows through Wireless and Optical = IP-FLOW
between Trento and Torino
prof. Yoram Ofek - DIT - University di Trento
6
Action Plan
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Implementation: February-May 2005
 (1) Hardware implementation and testing (Giorgio, Olga)
 Software implementation primarily the scheduling operations, s.t.,
at predefined times in each UTC second – while gradually changing time scales – from milliseconds to
microseconds:
 (2) To change the cross-point by the switch controller (Nguyen, Deepak)
 (3) To send data to the switch (Truong, Guido)
To send data to Wi-Fi (Paolo, Danilo)
 (4) Wi-Fi with directional antennas (Paolo, Danilo)
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Integration and testing: May-July 2005
prof. Yoram Ofek - DIT - University di Trento
7
(1) Switching Fabric Prototype
MindSpeed
M21156
1
128
1
128-by-128
1280 Gbps
32
1
128
128-by-128
1280 Gbps
Electrical Interconnection
MindSpeed
M21151
1
128-by-128
1280 Gbps
1
128
32
128-by-128
1280 Gbps
1
128
128x128: 10 Tbps Switching Module
prof. Yoram Ofek - DIT - University di Trento
8
(1) Switching Fabric Prototype
M21151
144 x 144
Crosspoint
Switch
Laptop computer
Direct electrical
Coupling of GE?
M21151
144 x 144
Crosspoint
Switch
Electrical Interconnection
STEP 1: BASIC ELECTRONIC ANALOG & DIGITAL TESTING
M21151
21156
144 x 144
Crosspoint
Switch
Laptop computer
Direct electrical
Coupling of GE?
Oscilloscope
21156
M21151
144 x 144
Crosspoint
Switch
Error
Detector
Spectrum
Analyzer
Pattern
Generator
prof. Yoram Ofek - DIT - University di Trento
9
(1) Switching Fabric Prototype
TWO NODES with Alignment
GPS/Galileo
Time Source
UTC
UTC
GPS/Galileo
Time Source
Laptop computer
UTC TF
Alignment
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
Pipeline Forwarding
Switch Controller
Remote Packet
Data Source (Torino Design)
TF – Time Frame
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
M21151
144 x 144
Crosspoint
Switch
UTC
UTC
Laptop computer
M21151
Electrical Interconnection
M21151
Electrical Interconnection
UTC TF
Alignment
Pipeline Forwarding
Switch Controller
UTC
SIGNALING
VIA THE
NETWORK
UTC TF
Alignment
Laptop computer
UTC TF
Alignment
UTC
Laptop computer
Remote Packet
Data Source (Torino Design)
prof. Yoram Ofek - DIT - University di Trento
10
(1) UTC Based Switching Test Bed
GPS time/frequency
source.
GPS time/frequency
source.
Pack and Unpack data
with UTC.
Mindspeed demo board
Mindspeed demo board
High speed
data channels
Glue
logic
Glue
logic
M21151
M21151
144 x 144
Crosspoint
Switch
144 x 144
Crosspoint
Switch
Parallel
interface
Parallel
interface
rs232
USB2
BERT
3.2 Gb
prof. Yoram
- University
LowOfek
speed- DIT
control
channel di Trento
public Internet.
rs232
USB2
11
4 x GBIC
2 x gigabit ethernet
2 x gigabit ethernet
Pack and Unpack data
with UTC.
Mindspeed demo board
Mindspeed demo board
High speed
data channels
Glue
logic
Glue
logic
M21151
M21151
144 x 144
Crosspoint
Switch
144 x 144
Crosspoint
Switch
Parallel
interface
Parallel
interface
rs232
Low speed control channel
public Internet.
USB2
prof. Yoram Ofek - DIT - University di Trento
rs232
USB2
12
(1) Switching Fabric Prototype – Alignment
Time-of-Day
or UTC
Pipeline Forwarding
Switch Controller
Input 1
Output 1
Alignment
Idle time:
Safety margin
between two
time frames
Switching
Fabric
Input N
Output N
Alignment
Idle time:
Safety margin
between two
time frames
Tf
t+2
T f : Time frame
Tf
t+1
Tf
t
t-1
Tf
t-2
t-3
Time-of-Day or UTC
: Time frame payload – with a predefined number of data units
prof. Yoram Ofek - DIT - University di Trento
13
(1) Switching Fabric Prototype – Alignment
UTC alignment
problem:
The link delay is not
integer multiple of
time frames
UTC
Switch Controller
Select-out
Queue 1
1-to-3
DMUX
Queue 2
Queue 3
3-to-1
DMUX
To Fabric
Output signal
{
Input signal
Switch Controller
Select-in
Alignment Queues
UTC alignment principle:
At every time frame,
- packets from the receiver are stored in one queue and
- packets to the fabric are transferred from another queue
Thus, memory access BW = optical link BW
prof. Yoram Ofek - DIT - University di Trento
14
(1) Switching Fabric Prototype – testing plan
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Testing step 1: Static testing of the cross-point switches
Testing step 2: Optoelectronic transceiver to cross-point
Testing step 3: Bit synchronization testing
Testing step 4: GE to GE packet transmission
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Key issues:
 Bit synchronization
 UTC synchronization software latency
Discussion Notes:
• The synchro between two card can be done with internal generator or with
GPS clock and PGA logic card
• Synchro between two card: it is more important that the two card has the same
frequency than to know exactly what the frequency of them is
• MindSpeed works until 3Gb/s, but at this speed the distortion generates jitter.
It can be reduced by PLL. With PLL a continuous flow of packets is needed to
avoid silence that can cause loss of synchro.
• One flow in input can manage more than one flows in output.
prof. Yoram Ofek - DIT - University di Trento
15
(2) UTC-based Switch Controller
UTC
(2)
(1)
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UTC-based
Switch Controller
Switching
Fabric
Prototype
Down-load next switching configuration
UTC synchronization software latency
Which controller should be used? PC-based, ?
Using FPGA card with USB interface – up to 200 MHz
 How to connect single controller to 4 cross-point switches
prof. Yoram Ofek - DIT - University di Trento
16
(2) UTC-based Switch Controller
Discussion Notes:
• To use an external card with FPGA on board. The card can be connected to the Mindspeed Board with
bus and must be connected to a PC through COM or USB connection.
The controller must contain:
FPGA
USB controller or COM port
Programmable PLL to change the clock of FPGA
• The configuration of controller can be done with VHDL
• The LabView software can be user for these purpose, but it is only an user-interface.
• The speed of FPGA must manage the Mux (1to3) and DeMux(3to1)
prof. Yoram Ofek - DIT - University di Trento
17
(3) UTC-based Network Interface
UTC
UTC
(3)
UTC-based
Network
Interface
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(3)
(1)
Switching
Fabric
Prototype
UTC-based
Network
Interface
Which operating system should be used?
 FreeBSD or Linux
UTC to transmission response time – UTC to GE card?
prof. Yoram Ofek - DIT - University di Trento
18
(3) UTC-based Network Interface
Discussion Notes:
• The card for syncrho receive a clock from GPS and generate a pulse timing in the output with
frequency that can be changed
• Developed software is online.
• Each Pc must have an UTC card for the synchro
• If a server has two processor, the OS allows to manage them separately?
• Software FREEBSD: the system must manage the queue and programs to queues are written
for this OS. There is not export for Linux?
• FreeBSD can be more flexible, but it may be more difficult to manage.
prof. Yoram Ofek - DIT - University di Trento
19
(4) Wireless to Optical Interface
UTC
UTC
(3)
(4)
Wi-Fi
w/Smart
Antenna
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UTC-based
Network
Interface
(3)
(1)
Switching
Fabric
Prototype
UTC-based
Network
Interface
(4)
Wi-Fi
w/Smart
Antenna
Bandwidth mismatch scheduling
Clock distribution to Wi-Fi clients – mobile devices
…
Access point from ST Microelectronics
prof. Yoram Ofek - DIT - University di Trento
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(4) Wireless to Optical Interface
Discussion Notes:
• The flows that arrive to wireless network is synchro
• The AP of the wireless LAN can be synchronized among them
• The policy to allow user to access to the network can be partially centralized.
• Synchro among users is very difficult.
prof. Yoram Ofek - DIT - University di Trento
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