Object Oriented Programming –
Lessons Learned
Mike Mintz
Co-author
Hardware Verification with C++
mike@trusster.com
MARLUG - Mid-Atlantic Region Local Users Group
ANNUAL CONFERENCE - OCTOBER 12, 2006
Johns Hopkins University Applied Physics Lab – Laurel, MD
Overview
•
•
•
•
OOP Basics
The OOP Process
Summary
Q&A
2
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Why OOP?
A brief look back…
•
•
•
•
•
machine code
assembly code
procedural code
Information Hiding
Data Abstraction
0100100; 0111100;
MOV.W R3, #100
do_this(); do_that(value);
struct foo {int a; char b;}
do_action (void* opaque_ptr)
OOP is the main technique to manage
programming complexity in large projects.
3
mfm, www.trusster.com, OOP Lessons Learned, October 2006
What is OOP?
•
•
•
•
Structures inheriting from
structures
Can have data and/or function
members (called methods)
Can override or add behavior
(cannot subtract)
Can have access control
class base
public:
int some_data;
void method_one ();
virtual void method_two ();
class derived : public base
public:
int some_data;
void method_one ();
virtual void method_two ();
Source: Hardware Verification in C++, Chapter 1
4
mfm, www.trusster.com, OOP Lessons Learned, October 2006
The OOP Process
•
•
•
•
•
5
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Thinking OOP
Designing OOP
Classes in OOP
Connecting Classes
Coding OOP
Thinking OOP
•
•
•
•
Essential versus
Implementation complexity
Apparently Simple
Adaptability and Ends-in
design
Interface, Implementation
and base classes
6
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Designing OOP
•
•
•
•
•
OOP is much more than
syntax!
Clearly define
algorithms and actors
Beware of apparently
simple
Interface versus
Implementation
Layers, Layers, Layers
Verification Component Hierachy
verification top
test
test
component
watchdog
timer
irritator
testbench
C++
HDL
chip
Source: Hardware Verification in C++, page 177, page 50
7
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Classes
Memory Bank Objects
•
•
•
•
A class is what you want
it to be
Not everything is a class
Bring derivation and
virtual in as needed
Beware the second
system effect
8
mfm, www.trusster.com, OOP Lessons Learned, October 2006
c++
hdl
Your verification code
GPU
map ()
read ()
write ()
memory_cach
e
Memory bank lookup
memory_bank
memory_1
memory_bank
memory_2
memory_bank
memory_3
Source: Hardware Verification in C++, page 82
Connecting Classes
•
•
•
As important as classes
themselves
Symmetry of
connections
Thicket versus well
ordered mesh
Detailed BFM Agent Connections
To UART SFM
and chip
Channel
From chip and
UART BFM
uart::bfm_agent
Expected
uart::generator
Actual
uart::checker
Source: Hardware Verification in C++, page 294
9
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Coding OOP
UART Example: Objects and Connections
•
•
•
•
The goal is to put the “if
tests” in the obvious
place
Many tricks and idioms
exist
Coding style is always
evolving
Beware of coding
standards
testbench.v
uart::bfm
wishbone::driver
1655
UART
teal::memory::write()
wishbone
driver
uart::uart_16550_sfm
Wire
uart::bfm_agent
uart::uart_16550_sfm_agent
uart::generator_agent
uart::generator
uart::checker_agent
Agent
Transaction
uart::checker
uart::basic_test_component
uart_test_0
Source: Hardware Verification in C++, page 275
10
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Summary
•
•
•
•
OOP is a little bit syntax and
a large amount of attitude
Learning OOP is gradual
process, making mistakes is
in integral part
Just Do It!
See www.trusster.com for
forums, articles, etc.
11
mfm, www.trusster.com, OOP Lessons Learned, October 2006
12
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Deleted Scenes/Bonus Material
•
•
•
This section contains “extra” slides that will be
covered if time permits.
Compares Verilog and OOP
Goes into some examples of OOP
13
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Teal and Truss
•
•
•
What is Teal?
Comparing Verilog and OOP
What is Truss?
14
mfm, www.trusster.com, OOP Lessons Learned, October 2006
What is Teal?
•
•
•
•
•
•
A tiny, open source C++
to Verilog gasket
Two stage logging
Stable, independent,
random number
generators
Thread management
Memory interface
Parameter passing
dictionary
15
mfm, www.trusster.com, OOP Lessons Learned, October 2006
testbench
reg clk;
wire data;
DUT
void verification_top ()
{
vreg clk (“testbench.clk”);
vreg data (“testbench.data”);
for (;;) {
at (posedge (clk));
data = 1;
}
}
Comparing Verilog and OOP in C++
Verilog
Teal/C++
module
class or struct
task compute_crc ()
void compute_crc ();
function reg build()
reg build();
reg[7:0] clk;
reg clk (8);
Teal
$display (“Hello”);
vout << “hello” < endm;
Teal
clk <= 1;
clk = 1;
Teal
@ (posedge (clk))
at (posedge (clk))
Teal
fork/join
start_thread (function)/join_thread
Teal
$rand()
RAND_RANGE()
Teal
mc_scan_plusargs/vpi_ dictionary::find()
get_vlog_info
16
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Comments
Teal
What is Truss?
•
•
•
•
A small, open source,
framework for
verification
Provides “the Dance”
Is a Design Pattern – not
always code
Can be the basis for
your test system
17
mfm, www.trusster.com, OOP Lessons Learned, October 2006
The Dance
•
•
Top Level Dance
Test Component and Irritator Dances
18
mfm, www.trusster.com, OOP Lessons Learned, October 2006
The “Dance”
The Dance – Detailed Flow
The Dance
verification_top
Create
top
objects
Test
Watchdog
verification_top()
Testbench
testbench::new(std::string)
new()
watchdog::new(std::string)
your_test::randomize()
Build and randomize()
configure
testbench::randomize()
testbench::time_zero_setup()
watchdog::time_zero_setup()
time_zero_setup()
Perform top-level
randomization, for example,
chose interfaces or features
to be tested
Pull wires/registers up or
down before releasing the
reset line
your_test::time_zero_setup()
testbench::out_of_reset ()
Main
test
run
Build objects,
apply constraints
your_test::new(testbench*, watchdog*, std::string)
watchdog::out_of_reset()
out_of_reset()
your_test::out_of_reset()
Hold the reset line for
the minimal amount,
then release it. Return
when registers can be
accessed
testbench::write_to_hardware()
watchdog::write_to_hardware()
start()
Push the configurations
down to the hardware
your_test::write_to_hardware()
testbench::start()
wait_for_completion()
watchdog::start()
Exercise the
chip
your_test::start()
Test
results
testbench::wait_for_completion()
report(“final”)
your_test::wait_for_completion()
testbench::report(“Final Report”)
your_test::report(“Final Report”)
Timeout
path
report(“timeout”)
19
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Print which components
have completed
Legend
testbench
your_test
watchdog
Source: Hardware Verification in C++, page 97
Pause until the checkers
are finished
$PROJECT_HOME/verification/testbench/top/testbench.cpp
$PROJECT_HOME/verification/tests/your_test.cpp
$TRUSS_HOME/src/watchdog.cpp
Source: Hardware Verification in C++, page 119
Lower level “Dance” – Painfully Detailed
Test Component Dance – Detailed Flow
your::new(generator, bfm, checker)
The irritator dance
The test builds
your test component
from your_test::start()
your::time_zero_setup()
test_component::start()
Performs the same
function as the
top-level components
your::out_of_reset()
test_component::start_()
Start_ runs in a
thread!
your::write_to_hardware()
your_test_component::start_components_()
test_component::start()
Start your testbench
generator, bfm, checker
irritator::run_component_traffic_()
test_component::start_()
until irritator::stop_generation()
Your
test
your::start_components_()
Start your generator,
BFM, and checker
test_component::run_component_traffic_()
test_component::run_component_traffic_()
your::randomize()
your::generate_()
your_test_component::randomize()
your_test_component::generate_()
your_test_component::inter_generate_gap_()
test_component:wait_for_completion()
your_test_component:wait_for_completion_ ()
Set up and run your
“main traffic” method
Set up and run your
“main traffic” method
Wait for your
checker to complete
test_component::final_report (“Final Report”)
Pause the generate loop
Legend
you must implement
$PROJECT_HOME/verification/test_components/your_irritator.cpp
you may implement
$TRUSS_HOME/inc/test_component.h, and irritator.h
Legend
you must implement
$PROJECT_HOME/verification/test_components/your_test_component.cpp
base implementation provided
$TRUSS_HOME/inc/truss_test_component.h
called from the same named method in test
Source: Hardware Verification in C++, page 120
20
mfm, www.trusster.com, OOP Lessons Learned, October 2006
Source: Hardware Verification in C++, page 121
Summary
(long form)
•
•
•
•
•
OOP is a little bit syntax and a large amount of
attitude
Learning OOP is gradual process, making mistakes
is in integral part
Teal is a Verilog/C++ gasket
Truss is a verification framework
There are good examples in the book and on the
web
21
mfm, www.trusster.com, OOP Lessons Learned, October 2006
22
mfm, www.trusster.com, OOP Lessons Learned, October 2006