CS/EE 3700 : Fundamentals of
Digital System Design
Chris J. Myers
Lecture 9: Asynchronous Sequential Circuits
Chapter 9
Asynchronous Circuits
• Asynchronous sequential circuits do not use a
clock or flip-flops for state variables.
• Changes in state occur in response to changes on
the inputs.
• This chapter describes single input change (SIC)
fundamental-mode async. circuits.
• Only one input allowed to change at a time.
• Time between input changes must be sufficient for
the circuit to stabilize.
R
Y
y
Q
S
(b) Circuit with modeled gate delay
Next state
Present
state
y
SR = 00
01
10
11
Y
Y
Y
Y
0
0
0
1
0
1
1
0
1
0
(b) State-assigned table
Figure 9.1
Analysis of the SR latch
Present
state
Next state
SR = 00
01
10
11
Output
Q
A
A
A
B
A
0
B
B
A
B
A
1
(a) State table
SR
10
00
01
11
A 0
B 1
01
11
(b) State diagram
Figure 9.2
FSM model for the SR latch
00
10
Next state
Present
state
SR = 00 01 10
Output, Q
11
00
01
10
11
A
A
A
B
A
0
0
–
0
B
B
A
B
A
1
–
1
–
(a) State table
SR/Q
10/ –
00/0
01/0
11/0
A
B
00/1
10/1
01  –
11  –
(b) State diagram
Figure 9.3
Mealy representation of the SR latch
Terminology
• state table = flow table
• state-assigned table = transition table or
excitation table.
w1
z1
Outputs
Inputs
Combinational
circuit
wn
yk
zm
Yk
Next-state
variables
Present-state
variables
y1
Figure 8.90
Y1
The general model for a sequential circuit
D
Y
y
Q
C
(a) Circuit
Nextstate
Present
state CD = 00 01 10
y
Y Y
Y
11
Y
Q
0
0
0
0
1
0
1
1
1
0
1
1
(b) Excitationtable
Figure 9.4 The gated D latch
Nextstate
Present
state CD = 00 01 10
11
Q
A
A
A
A
B
0
B
B
B
A
B
1
(c) Flowtable
CD
0x
x0
11
A 0
B 1
10
(d) Statediagram
Figure 9.4 The gated D latch
0x
x1
Master
D
D
C
Clk Q
Figure 9.5
Q
Slave
ym
D
Q
Clk Q
ys
Q
Q
Circuit for the master-slave D flip-flop
Present
state
ym ys
Next state
CD = 00
01
10
11
Output
Q
Ym Y s
00
00
00
00
10
0
01
00
00
01
11
1
10
11
11
00
10
0
11
11
11
01
11
1
(a) Excitationtable
Present
state
Next state
CD = 00
01
10
11
Output
Q
S1
S1
S1
S1
S3
0
S2
S1
S1
S2
S4
1
S3
S4
S4
S1
S3
0
S4
S4
S4
S2
S4
1
(b) Flow table
Figure 9.6
Excitation and flow tables for Example 9.2
Present
state
Next state
CD = 00
01
10
11
Output
Q
S1
S1
S1
S1
S3
0
S2
S1
S1
S2
S4
1
S3
S4
S4
S1
S3
0
S4
S4
S4
S2
S4
1
(b) Flow table
Present
state
Next state
CD = 00
01
10
11
Output
Q
S1
S1
S1
S1
S3
0
S2
S1
–
S2
S4
1
S3
–
S4
S1
S3
0
S4
S4
S4
S2
S4
1
(c) Flow Table with unspecified entries
Figure 9.6
Excitation and flow tables for Example 9.2
CD
11
0x
x0
S1 0
S3 0
11
10
0x
0x
11
10
S2 1
S4 1
10
Figure 9.7
0x
x1
State diagram for the master-slave D flip-flopC
Y1
y1
Y2
y2
w1
w2
Figure 9.8
Circuit for Example 9.3
z
Present
state
y2 y1
Next state
01
10
11
Output
Y2 Y1
Y2 Y1
Y2 Y1
Y2 Y1
z
00
00
01
10
11
0
01
11
01
11
11
0
10
00
10
10
10
1
11
11
10
10
10
0
w 2 w 1 = 00
(a) Excitation table
Present
state
Next state
w2 w1 = 00
01
10
11
Output
z
A
A
B
C
D
0
B
D
B
D
D
0
C
A
C
C
C
1
D
D
C
C
C
0
(b) Flow table
Figure 9.9
Excitation and flow tables
Present
state
Next state
Output
w2 w 1 = 00
01
10
11
z
A
A
B
C
–
0
B
D
B
–
D
0
C
A
C
C
C
1
D
D
C
C
C
0
Figure 9.10
Modified flow table for Example 9.3
w2w1
00
01
A/0
10
1x
x1
Figure 9.11
01
00
11
00
C/1
B/0
1x
x1
D/0
State table for Example 9.3
00
Present
state
Next state
w 2 w 1 = 00
01
10
A
A
B
C
B
D
B
–
C
A
C
C
D
D
C
C
w2  dime
Figure 9.12
11
–
–
–
–
Output
z
0
0
1
0
w 1  nickel
Flow table for a simple vending machine
Steps in the Analysis Process
• Cut feedback paths and insert delay element.
– Input to delay element is next-state, and output is the
present-state.
– Cut set may not be unique.
• Derive next-state and output expressions from the
circuit.
• Derive the excitation table.
• Derive a flow table.
• Derive a state diagram, if desired.
Synthesis of Asynchronous
Circuits
•
•
•
•
•
•
•
Devise a state diagram.
Derive the flow table.
Minimize number of states.
Perform race-free state assignment.
Derive excitation table.
Obtain next-state and output expressions.
Construct a hazard-free circuit.
1
A/0
0
B/1
1
0
0
1
D/0
1
0
C/1
(a) State diagram
Next state
Present
State
w= 0
w= 1
Output
z
A
A
B
0
B
C
B
1
C
C
D
1
D
A
D
0
(b) Flow table
Figure 9.13
Parity-generating asynchronous FSM
Next state
Present
state
y 2y 1
w= 0
00
00
01
0
01
10
01
1
10
10
11
1
11
00
11
0
w= 1
Output
z
Y 2Y 1
(a) Poor state assignment
Figure 9.14
State assignment
Next state
Present
state
y 2y 1
w= 0
00
00
01
0
01
11
01
1
11
11
10
1
10
00
10
0
w= 1
Output
z
Y 2Y 1
(b) Good state assignment
Figure 9.14
State assignment
y1
w
y2
Figure 9.15
Circuit that implements an FSM
z
D
w
Figure 9.16
Q
z
Q
Synchronous solution for Example 9.4
0
A  0
0
1
1
B  1
0
C  1
1
1
D  2
0
0
H  0
1
1
G  3
0
Figure 9.17
0
F  3
1
1
State diagram for a modulo-4 counter
E  2
0
Nextstate
Present
state
w= 0
w= 1
Output
z
A
A
B
0
B
C
B
1
C
C
D
1
D
E
D
2
E
E
F
2
F
G
F
3
G
G
H
3
H
A
H
0
(a) Flowtable
Figure 9.18
Flow and excitation tables for a modulo-4 counter
Next state
Present
Output
Mod-8 output
z 2z 1
z 3z 2z 1
001
00
000
011
001
01
001
011
011
010
01
010
010
110
010
10
011
110
110
111
10
100
111
101
111
11
101
101
101
100
11
110
100
000
100
00
111
state
y 3y 2y 1
w = 0
000
000
001
w = 1
Y 3Y 2Y 1
(b) Excitation table
Figure 9.18
(c) Output for counting
the edges
Flow and excitation tables for a modulo-4 counter
Request1
Grant1
Device 1
Shared
resource
Arbiter
Request2
Grant2
Device 2
(a) Arbitration structure
Request (r)
Grant (g)
(b) Handshake signaling
Figure 9.19
Arbitration example
r 2r 1
01
11
00
A 00
B 01
00
10
10
00
01
C 10
10
11
Figure 9.20
State diagram for the arbiter
01
11
Nextstate
Present
Output
state r r = 00 01 10 11 g g
21
21
A
A
B
C
B
00
B
A
B
C
B
01
C
A
B
C
C
10
(a) Flowtable
A
Nextstate
Present
state r2r1 = 00 01 10 11 Output
gg
y2y1
Y2Y1
21
00
00 01 10 01
00
B
01
00 01
10 01
C
10
00 01 10
D
11
01 10
10
01
10
dd
(b) Excitationtable
Figure 9.21
Implementation of the arbiter
THIS CIRCUIT IS WRONG!
r1
g1
r2
y2
g2
Figure 9.22
The arbiter circuit
Present
state
Next state
Output
g2 g1
r 2 r 1 = 00
01
10
11
A
A
B
C
B
00
B
A
B
A
B
01
C
A
A
C
C
10
(a) Modified flow table
Present
state
y2 y1
Next state
r 2 r 1 = 00
01
10
11
Output
g2 g1
Y2 Y1
00
00
01
10
01
00
01
00
01
00
01
01
10
00
00
10
10
10
(b) Modified excitation table
Figure 9.23
An alternative for avoiding a critical race
10 – 0
0000
x1 01
B
0000
1x 10
C
01 0–
Present
state
Next state
Output g2 g1
r 2 r 1 = 00
01
10
11
00
01
10
11
B
B
B
C
B
00
01
–0
01
C
C
B
C
C
00
0–
10
10
(a) Flow diagram
Figure 9.24
Mealy model for the arbiter FSM
Present
state
Next state
r 2 r 1 = 00
y
01
Output
10
11
00
01
10
11
g2 g1
Y
0
0
0
1
0
00
01
d0
01
1
1
0
1
1
00
0d
10
10
(b) Excitation table
Figure 9.25
Mealy model implementation of the arbiter FSM
State Reduction
• Usually start with primitive flow table (i.e.,
only a single stable state per row).
• Asynchronous FSMs likely have many
unspecified (don’t care) entries.
• Two-step state reduction process:
– Apply partitioning procedure in which don’t
care entries must match.
– Merge rows exploiting don’t cares.
N
D
C 1
B 0
N
0
A 0
0
0
D 0
0
0
N
N
E 1
0
Figure 9.26
D
F 1
D
0
(a) Initial statediagram
Derivation of an FSM for the simple vending machine
D
Nextstate
Present
State DN = 00 01 10
A
A
B
B
D
C
A
B
–
D
D
E
E
A
F
A
E
–
C
–
C
F
–
F
11
–
Output
z
0
–
0
–
1
–
0
–
1
–
1
(b) Initial flowtable
Figure 9.26
Derivation of an FSM for the simple vending machine
Present
state
Figure 9.27
Next state
Output
DN = 00
01
10
A
A
B
C
B
D
B
–
C
A
–
C
D
D
E
C
E
A
E
–
11
–
–
–
–
–
z
0
0
1
0
1
First-step reduction of the vending machine FSM
Present
state
Next state
w 2 w 1 = 00
01
10
A
A
B
C
B
D
B
–
C
A
C
C
D
D
C
C
w2  dime
Figure 9.12
11
–
–
–
–
Output
z
0
0
1
0
w 1  nickel
Flow table for a simple vending machine
Merging Procedure
• May be many possibilities for row mergers.
• Two states Si and Sj are compatible if there
are no state conflicts for any input.
– both Si and Sj have same successor, or
– both Si and Sj are stable, or
– the successor of Si or Sj or both is unspecified.
• Si and Sj must also have same output when
specified.
Present
state
Next state
w 2 w 1 = 00
01
10
11
Output
z
A
A
H
B
–
0
B
F
–
B
C
0
C
–
H
C
1
D
A
D
–
–
E
1
E
–
D
G
E
1
F
F
D
–
0
G
F
–
G
–
–
0
H
–
H
–
E
0
Figure 9.28
A primitive flow table
A
B
C
D
H
G
F
E
Figure 9.29
Merger diagram (which preserves the Moore model)
Present
state
Next state
w 2 w 1 = 00
01
10
11
Output
z
A
A
A
B
D
0
B
B
D
B
C
0
C
–
A
–
C
1
D
A
D
B
D
1
Figure 9.30
Reduced Moore-type flow table
B
C
A
D
H
E
G
Figure 9.31
F
Complete merger diagram
State Reduction Procedure
1. Use partitioning procedure to eliminate
equivalent states in primitive flow table.
2. Construct merger diagram.
3. Choose subsets of equivalent states
including each state in only one subset.
4. Derive reduced flow table.
5. Repeat 2 to 4 until no reduction.
Present
state
Next state
Output
w 2 w1 = 00
01
10
11
z
A
A
F
C
–
0
B
A
B
–
H
1
C
G
–
C
D
0
D
–
F
–
D
1
E
G
–
E
D
1
F
–
F
–
K
0
G
G
B
J
–
0
H
–
L
E
H
1
J
G
–
J
–
0
K
–
B
E
K
1
L
A
L
–
K
1
Figure 9.32
Flow table for Example 9.8
Present
state
Figure 9.33
Next state
Output
w 2 w 1 = 00
01
10
11
z
A
A
F
C
–
0
B
A
B
–
H
1
C
G
–
C
D
0
D
–
F
–
D
1
E
G
–
E
D
1
F
–
F
–
H
0
G
G
B
J
–
0
H
–
B
E
H
1
J
G
–
J
–
0
Reduction obtained by using the partitioning procedure
B
A
C
H
F
J
Figure 9.34
Merger diagram
D
G
E
Present
state
Next state
Output
w 2 w 1 = 00
01
10
11
z
A
A
A
C
B
0
B
A
B
D
B
1
C
G
–
C
D
0
D
G
A
D
D
1
G
G
B
G
–
0
Figure 9.35
Reduction obtained from the merger diagram
A
B
D
Figure 9.36
Merger diagram
C
G
Present
state
Next state
Output
w 2 w 1 = 00
01
10
11
z
A
A
A
C
B
0
B
A
B
D
B
1
C
C
B
C
D
0
D
C
A
D
D
1
Figure 9.37
Reduced flow table for Example 9.8
Present
state
Next state
Output
w2 w1 = 00
01
10
11
z
A
A
G
E
–
0
B
K
–
B
D
0
C
F
C
–
H
1
D
–
C
E
D
0
E
A
–
E
D
1
F
F
C
J
–
0
G
K
G
–
D
1
H
–
E
H
1
J
F
–
–
J
D
0
K
K
C
B
–
0
Figure 9.38
Flow table for Example 9.9
Present
state
Figure 9.39
Next state
Output
w 2 w 1 = 00
01
10
11
z
A
A
G
E
–
0
B
F
–
B
D
0
C
F
C
–
H
1
D
–
C
E
D
0
E
A
–
E
D
1
F
F
C
B
–
0
G
F
G
–
D
1
H
–
–
E
H
1
Reduction resulting from the partitioning procedure
A
B
C
D
G
F
H
E
(a) Preserving the Moore model
A
H
C
G
E
D
F
B
(b) Complete merger diagram
Figure 9.40
Merger diagrams
Present
state
Output z
Next state
w 2 w 1 = 00
01
10
11
00
01
10
11
A
A
G
E
–
0
–
–
B
F
–
B
D
0
–
–
0
0
C
F
C
–
H
–
C
E
D
–
–
1
D
E
A
–
E
D
F
F
C
B
–
G
F
G
–
D
H
–
–
E
H
– 1
– –
– –
0
–
– 1
– –
Figure 9.41
0
–
–
–
–
1
1
1
0
An FSM specified in the form of a Mealy model
Present
state
Output z
Next state
w 2 w 1 = 00
01
10
11
00
01
10
11
A
A
B
D
A
0
–
1
1
B
C
B
B
D
0
1
0
0
C
C
C
B
A
0
1
0
1
D
A
C
D
D
–
–
1
0
Figure 9.42
Reduced flow table for Example 9.9
Present
state
Next state
Output
w 2 w 1 = 00
01
10
11
z
A
A
B
C
–
0
B
F
B
–
H
0
C
F
–
C
H
0
D
D
G
C
–
1
E
A
E
–
H
0
F
F
E
C
–
0
G
D
G
–
H
0
H
–
G
C
H
1
Figure 9.43
Flow table for Example 9.9
Present
state
Next state
Output
w2 w1 = 00
01
10
11
z
A
A
B
C
–
0
B
A
B
–
H
0
C
A
–
C
H
0
D
D
G
C
–
1
G
D
G
–
H
0
H
–
G
C
H
1
Figure 9.44
Reduction after the partitioning procedure
C
H
D
B
A
Figure 9.45
G
Merger diagram
Present
state
Output z
Next state
w 2 w 1 = 00
01
10
11
00
01
10
11
A
A
A
A
D
0
0
0
–
D
D
D
A
D
1
0
–
1
Figure 9.46
Reduced flow table for Example 9.10
State Assignment
• Impossible to ensure that a change of two or
more state variables occur at the same time.
• To achieve reliable operation, should make
state variables change one at a time.
• Hamming distance is number of bits
different in two bit strings.
• Ideal state assignment has Hamming
distance of 1 for all state transitions.
C = 10
Nextstate
Present
state w = 0 w = 1
y2y1
Y2Y1
00
00
01
01
10
01
Output
z
0
1
10
10
11
1
11
00
11
0
w= 0
A = 00
w= 1
w= 0
01
1
11
11
10
1
10
w= 1
B = 01
C = 11
w= 0
0
11
00
w= 0
Output
z
01
10
D = 11
(a) Corresponding to Figure 9.14 a
D = 10
Nextstate
Present
state w = 0 w = 1
y2y1
Y2Y1
00
00
01
w= 1
0
A = 00
w= 1
B = 01
(b) Corresponding to Figure 9.14 b
Figure 9.47
Transitions
C = 10
Nextstate
Present
Output
state r r = 00 01 10 11 g2g1
21
A
A B C B
00
B
C
A
A
B
B
C
C
B
C
01
00
10
10
01
10
00
A = 00
B = 01
01
11
(a) Transitions in Figure 9.21 a
Nextstate
Present
state r2r1 = 00 01 10 11 Output
gg
y2y1
Y2Y1
21
A
00
00 01 10 01
00
B
C
01
10
00 01 10 01
00 01 10 10
D
11
01 10
01
10
dd
10
C = 10
D = 11
01
00
10
01
10
00
A = 00
01
11
B = 01
(b) Using the extra state D
Figure 9.48
Transitions for the arbiter
Present
state
Next state
Output
r 2 r 1 = 00
01
10
11
g2 g1
A
A
B
C
B
00
B
A
B
D
B
01
C
A
D
C
C
10
D
–
B
C
–
10
Figure 9.49
Modified flow table
Transition Diagram
• Transition diagram illustrates all transitions
in a flow table.
• Good state assignment means no diagonals
in the transition diagram.
• Must embed the transition diagram onto a
k-dimensional cube.
• n state variables can be embedded onto an
n-dimensional cube.
Present
state
Next state
r 2r 1 = 00
01
10
11
Output
g2g1
A
1
2
4
3
00
B
1
2
4
3
01
C
1
2
4
5
10
Figure 9.50
Relabeled flow table
C = 10
1, 4
A = 00
C = 10
2, 4
1, 2, 3
1, 4, 2
B = 01
A = 00
(a) Transitions in Figure 9.50
2,4, 1
1, 2, 3, 4
(b) Complete transition diagram
C = 10
1, 4, 2
A = 00
Figure 9.51
B = 01
1, 2, 3, 4
B = 01
Transition diagrams
Deriving Transition Diagrams
• Derive relabeled flow table.
– Transitions through unstable states that lead to
stable state are given the same number.
• Represent each row of flow table by vertex.
• Join Vi and Vj by edge if they have same
number in any column.
• For any column in which Vi and Vj have
same number, label edge with that number.
Present
state
Next state
w 2 w 1 = 00
01
10
11
Output
z2z1
A
A
B
C
A
00
B
B
B
D
C
01
C
A
C
D
C
10
D
B
–
D
A
11
(a) Flow table
Present
state
Next state
w2 w1 = 00
01
10
11
Output
z2 z1
A
1
4
7
2
00
B
3
4
7
6
01
C
1
5
7
6
10
D
3
–
7
2
11
(b) Relabeled flow table
Figure 9.52
Flow tables
7
D = 10
C = 11
3, 7
D = 10
3, 7
2, 7
7
6, 7
1, 7
B = 11
2, 7
6, 7
4, 7
B
A = 00
4,7
B = 01
A = 00
(a) First transition diagram
D = 10
3, 7, 4
B = 11
6, 7
1, 7
C = 01
(c) Augmented transition diagram
Figure 9.53
C = 01
(b) Second transition diagram
2, 7, 4
A = 00
1, 7
Transition diagrams
Present
state
Output z2 z 1
Next state
w2 w1 = 00
01
10
11
00
01
10
11
A
A
D
D
A
00
00
11
00
B
B
B
D
C
01
01
11
01
C
A
C
B
C
–0
10
1–
10
D
B
B
D
A
–1
0–
11
00
(a) Modified flow table
Present
state
y2 y1
Next state
w2 w1 = 00
01
Output
10
11
00
Y2 Y1
01
10
11
z2 z1
A
00
00
10
10
00
00
00
11
00
B
11
11
11
10
01
01
01
11
01
C
01
00
01
11
01
–0
10
1–
10
D
10
11
11
10
00
–1
0–
11
00
(b) Excitation table
Figure 9.54
Realization of an FSM
Present
state
Nextstate
w2 w1 = 00
01
10
11
Output
z 2z 1
A
A
A
C
B
00
B
A
B
D
B
01
C
C
B
C
D
10
D
C
A
D
D
11
(a) Flow table
Present
state
Nextstate
w2 w1 = 00
01
10
11
Output
z 2z 1
A
1
2
6
4
00
B
1
3
7
4
01
C
5
3
6
8
10
D
5
2
7
8
11
(b) Relabeled flow table
Figure 9.55
FSM for Example 9.14
1, 4
A
6
B
1, 4
A
7
6
2
3
2
5, 8
E
3
5, 8 G 5, 8
D
C
3
F
7
D
7
B
C
(b) Augmented transition diagram
(a) Transition diagram
G
5, 8
7
D
E
5, 8
2
C
3
7
6
A
F
y2
3
1, 4
B
(c) Embedded transition diagram
Figure 9.56
Transition diagrams
y3
y1
Nextstate
Present
Output
state w w = 00 01 10 11 z2z1
2 1
A
A A C B
00
B
A
B
E
B
01
C
C
F
C
G
10
D
G
–
A
–
D
D
–
11
E
F
–
G
C
B
–
D
–
–
–
D
(a)Modifiedflowtable
Figure 9.57
Modified tables for Example 9.14
–1
01
1–
Present
state
y 3y 2y 1
Next state
w 2w 1 = 00
01
10
11
Output
z 2z 1
Y 3Y 2Y 1
A
000
000
000
100
001
00
B
001
000
001
011
001
01
C
100
100
101
100
110
10
D
010
110
000
010
010
11
E
011
–
–
010
–
–1
F
101
–
001
–
–
G
110
100
–
–
010
(b) Excitation table
Figure 9.57
Modified tables for Example 9.14
01
1–
5 , 8
C2
3
D2
7
B1
B2
1 , 4
1 , 4
C1
5 , 8
y2
D1
6
2
A1
Figure 9.58
A2
y3
y1
Embedded transition diagram if two nodes per row are used
Nextstate
Present
state
w2w1 = 00 01 10
11
Output
z 2z 1
A1
A1
A1
C1
B1
00
A2
A2
A2
A1
B2
00
B1
A1
B1
B2
B1
01
B2
A2
B2
D2
B2
01
C1
C1
C2
C1
D1
10
C2
C2
B1
C2
D2
11
D1
C1
A2
D1
D1
11
D2
C2
D1
D2
D2
11
(a) Modifiedflow table
Figure 9.59
Modified flow and excitation tables for Example 9.15
Present
state
y 3y 2y 1
Next state
w 2w 1 = 00
01
10
11
Output
z 2z 1
Y 3Y 2Y 1
A1
000
000
000
100
010
00
A2
001
001
001
000
011
00
B1
010
000
010
011
010
01
B2
011
001
011
111
011
01
C1
100
100
110
100
101
10
C2
110
110
010
110
111
10
D1
101
100
001
101
101
11
D2
111
110
101
111
111
11
(b) Excitation table
Figure 9.59
Modified flow and excitation tables for Example 9.15
State
assignment
Present
State
0001
Next state
Output
w2 w 1 = 00
01
10
11
z2 z1
A
A
A
E
F
00
0010
B
F
B
G
B
01
0100
C
C
H
C
I
10
1000
D
I
J
D
D
11
0101
E
C
–
–0
0011
F
–
B
0–
1010
G
–1
0110
H
1100
I
1001
J
–
– –
– D
– –
Figure 9.60
– –
A
–
– –
– B
C –
– A
D
State assignment with one-hot encoding
01
1–
00
Hazards
• In asynchronous circuits, undesirable
glitches must not occur.
• Glitches caused by structure of circuit and
propagation delays are called hazards.
• Designer must eliminate all hazards from an
asynchronous circuit.
1
0
0 0
1 1
(a) Static hazard
1
0
0 1
1 0
(b) Dynamic hazard
Figure 9.61
Definition of hazards
x2
p
x1
f
x2
q
x3
x1
(a) Circuit with a hazard
x3
x1 x2
00
01
0
1
f
x3
11
10
1
1
1
1
(b) Karnaugh map
Figure 9.62 An example of a static hazard
(c) Hazard-free circuit
Remove Static 1-Hazards
• Hazard exists whenever 2 adjacent 1s in a
K-map are not covered by a single product.
• To remove all static hazards, find a cover
that includes each pair of adjacent 1s.
p
D
ym
Ym
q
C
Ys
ys
Q
r
(a) Minimum-cost circuit
CD
ymys
CD
00 01 11 10
ymys
00 01 11 10
00
1
00
01
1
01
11 1
1
1
11 1
1
10 1
1
1
10 1
1
1
1
1
1
(b) Karnaugh maps Y
for
a
mandYs in Figure 9.6
Figure 9.63 Two-level implementation of master-slave D flip-flop
CD
ymys
CD
00
01
11
10
ymys
00
00
1
00
01
1
01
01
11
1
1
1
11
1
1
10
1
1
1
10
1
1
11
10
1
1
1
1
(b) Karnaugh maps for Ym and Ys in Figure 9.6a
ym
D
Ym
C
Ys
Q
ys
(c) Hazard-free circuit
Figure 9.63 Two-level implementation of master-slave D flip-flop
x3x4
x1x2
00
01
11
00
d
01
d
11
1
1
1
10
1
1
1
Figure 9.64
10
d
1
Function for Example 9.17
x1
p
x2
f
x1
q
x3
x2
(a) Circuit with a hazard
x3
x1 x2
00
01
11
10
0
0
0
0
1
1
0
1
1
1
(b) Karnaugh map
Figure 9.65
f
x3
Static hazard in a POS circuit
(c) Hazard-free circuit
b
x1
f
a
x2
c
x3
d
x4
(a) Circuit
One gate delay
x1
x2,x3,x4
a
b
c
d
f
Figure 9.66
Circuit with a dynamic hazard
(b) Timing diagram
Significance of Hazards
• A glitch in an asynchronous circuit can
cause the circuit to enter an incorrect state
and possibly become stable in that state.
• Next-state logic must be hazard-free.
• Synchronous circuits can have hazards as
long as they are stable by the setup time of
the flip-flops.
Vending Machine Controller
•
•
•
•
It accepts nickels and dimes.
A total of 15 cents to release candy.
No change given if 20 cents is deposited.
Coins deposited one at a time.
0
A  0
N
D
B  0
N
C  0
0
0
D  0
0
J  0
D
N
E  0
N
D
N
F  1
D
K  1
0
D
N
D
L  1
0
G  0
0
D
N
N
H  1
0
Figure 9.67
0
D
0
0
0
I  1
0
Initial state diagram for the vending-machine controller
Present
state
Next state
Output
DN = 00
01
10
11
z
A
A
B
C
–
0
B
D
B
–
–
0
C
J
–
C
–
0
D
D
E
F
–
0
E
G
E
–
–
0
F
A
–
F
–
1
G
G
H
I
–
0
H
A
H
–
–
1
I
A
–
I
–
1
J
J
K
L
–
0
K
A
K
–
–
1
L
A
–
L
–
1
Figure 9.68
Initial flow table for the vending-machine controller
Present
state
Next state
Output
DN = 00
01
10
11
z
A
A
B
C
–
0
B
D
B
–
–
0
C
G
–
C
–
0
D
D
E
F
–
0
E
G
E
–
–
0
F
A
–
F
–
1
G
G
H
F
–
0
H
A
H
–
–
1
Figure 9.69
First step in state minimization
A
B
C
H
D
G
F
Figure 9.70
Merger diagram
E
Present
state
Next state
DN = 00
01
10
11
Output
z
A
A
B
C
–
0
B
D
B
–
–
0
C
G
C
C
–
0
D
D
C
F
–
0
F
A
F
F
–
1
G
G
F
F
–
0
(a) Minimized flow table
Present
state
Next state
DN = 00
01
10
11
Output
z
A
1
2
4
–
0
B
5
2
–
–
0
C
8
3
4
–
0
D
5
3
7
–
0
F
1
6
7
–
1
G
8
6
7
–
0
(b) Relabeled flow table
Figure 9.71
Reduced flow tables
DN
00
A  0
01
01
B  0
00
00
D  0
00
01
10
F  1
10
G  0
01
10
01
10
Figure 9.72
C  0
00
00
01
10
State diagram for the vending-machine controller
B
5
D
3
C
4
7
8
2
7
6 , 7
G
A
1
F
(a) Transition diagram
110
4
5
B
010
3
D
011
4
2
C
111
8
7
100
G
101
4
6 , 7
A
000
1
F
001
(b) Embedded on the cube
Figure 9.73
Determination of the state assignment
Present
state
Next state
DN = 00
y3 y2 y 1
01
10
11
Output
z
Y3 Y2 Y1
A
000
000
010
100
–
0
B
010
011
010
–
–
0
C
111
101
111
111
–
0
D
011
011
111
001
–
0
F
001
000
001
001
–
1
G
101
101
001
001
–
0
100
–
–
110
–
0
110
–
–
111
–
0
Figure 9.74
Excitation table
DN
y y
1 2
DN
00
01
00
10
d
01
1
11
1
10
11
y y
1 2
00
01
11
00
d
d
d
10
d
d
01
d
d
d
1
1
d
1
11
1
1
d
1
1
d
1
10
1
1
d
1
y = 1
3
y = 0
3
(a) Map for Y 1
Figure 9.75
Karnaugh maps for the functions in Figure 9.74
DN
y y
1 2
DN
00
00
01
11
1
d
10
y y
1 2
01
11
10
00
d
d
d
1
01
d
d
d
1
1
d
1
01
1
1
d
11
1
1
d
11
d
10
10
d
00
y3 = 0
d
y = 1
3
(b) Map for Y 2
Figure 9.75
Karnaugh maps for the functions in Figure 9.74
DN
y y
1 2
DN
00
11
10
00
d
1
01
d
d
11
10
01
1
y y
1 2
00
01
11
10
00
d
d
d
1
01
d
d
d
1
d
11
1
1
d
1
d
10
1
d
y = 1
3
y3 = 0
(c) Map for Y 3
Figure 9.75
Karnaugh maps for the functions in Figure 9.74
Summary
• Analysis of asynchronous circuits.
• Synthesis of asynchronous circuits.
– State reduction
– State assignment
– Hazard-free logic design