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CS 325: CS Hardware and Software
Organization and Architecture
Computer Evolution and
Performance 1
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Outline
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Generations in Computer Organization
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Milestones in Computer Organization
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Von Neumann Architecture
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Moore’s Law
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CPU Transistor sizes and count
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Memory Hierarchy
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Performance
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Cache Memory
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Performance Issues and Solutions
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History – Generations in Computer
Organization
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Zeroth generation – mechanical computers (1642 – 1945)
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First generation – vacuum tubes (1945 –1955)
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Harwell CADET, TX-0
Third generation – integrated circuits (1965 –1980)
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ENIAC, Colossus
Second generation – transistors (1955 –1965)
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Blaise Pascal’s mechanical calculator
IBM System/360
Fourth generation – VLSI (Very Large Scale Integration ) (1980 - ?)
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Microprocessors
 Supercomputers
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History – Milestones in Computer
Organization

1642 – Blaise Pascal,
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c. 1670 – Baron Gottfried Wilhelm von Leibniz,
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Mechanical machine with gears used to add and subtract.
Mechanical machine with gears used to add, subtract, multiply, and
divide.
1834 – Charles Babbage,
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Analytical Engine
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Ada Lovelace wrote its “assembler”
1936 – Konrad Zuse,
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Z1
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Calculator made of electromagnetic relays
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History – Milestones in Computer
Organization

1940’s – John Atanasoff, George Stibbitz, Howard Aiken,
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
Binary arithmetic
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Capacitors for memory
COLOSSUS, the first electronic computer.
1946 – John Mauchley, John Presper Eckert,
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1943 – Alan Turing and British Government,
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Each worked independently on calculating machines with properties
such as:
ENIAC, vacuum tubes
1949 – Maurice Wilkes,
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EDSAC, first stored program computer.
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History – Milestones in Computer
Organization
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1952 – John von Neumann,
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von Neumann architecture – most current computers use this basic
design.
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1950’s – Researchers at MIT,
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Transistorized Experimental Computer Zero (TX-0), first computer to
use transistors (3600 transistors).
1960 – Digital Equipment Corporation (DEC),
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Stored program computer w/ shared memory for instructions and
data.
PDP-1, first mini computer
1961 – IBM,
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1401, popular small business computer.
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History – Milestones in Computer
Organization
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1962 – IBM,
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7094 and 709 using transistors.
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1963 – Burroghs,
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B500, first computer designed for a high-level language (Algol,
precursor to C).
1964 – Seymour Cray, Control Data Group,
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6600, 10x faster than IBM 7094
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Used mainly for scientific computing.
Highly parallelized CPU
1965 – PDP-8,
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First mass-market mini computer.
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Used a single bus.
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History – Milestones in Computer
Organization
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1964 – IBM,
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First computers with multiprogramming.
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Used integrated circuits (dozens of transistors on one “chip”).
8080, first general purpose computer on a chip.
1974 – Cray-1,
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1974 – Intel,
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System/360, family of compatible computers (low end to high end).
First vector computer (single instructions on vectors of numbers).
1978 – DEC,
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VAX, first 32-bit mini computer.
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History – Milestones in Computer
Organization
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1978 – Steve Jobs, Steve Wozniak,
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1981 – IBM,
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MIPS, first commercial RISC computer.
1987 – Sun Microsystems,
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IBM PC becomes the most popular personal computer.
 Used MS-DOS by Microsoft as OS.
 CPU developed by Intel.
1985 – MIPS (company),
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Apple personal computer
SPARC, popular RISC computer.
1990 – IBM,
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RS6000, first superscalar machine
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History – Milestones in Computer
Organization
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1993 – Intel,
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Pentium CPU released.
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32-bit, 60 Mhz
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3.2 million transistors
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$878
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1993 – NVIDIA is founded.
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1994 – Intel,
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Pentium 2 CPU released.
1999 – Intel,
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Pentium 3 CPU released.
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32-bit, 550 Mhz
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History – Milestones in Computer
Organization
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2003 – AMD,
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Athlon 64 CPU is released.
2005 – AMD, Intel,
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Dual core CPU’s released.
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Computer and CPU Organization
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Definition:
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The terms processor, CPU, and computational engine refer broadly to
any mechanism that drives computation.
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Von Neumann Architecture
 Stored

Program/Data concept
Characteristic of most modern CPUs
 Main
 ALU
memory stores programs (instructions) and data.
operates on binary data.
 Control
unit interprets instructions from memory and
passes information along to ALU.
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Von Neumann Architecture – Three
Basic Components
 CPU
 Memory
 I/O
facilities
Control units
 Busses
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All interact to form a complete computer
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Structure of Von Neumann
Architecture
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Milestones in Computer
Organization
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Moore’s Law:
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Number of transistors on a chip doubles every 18 months.
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Milestones in Computer
Organization
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Moore’s Law:
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Increased density of components on chip.
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Originally, thought number of transistors on a chip will double every
year.
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Since the 1970’s, development has slowed. Number of transistors
doubles every 18 months.
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Cost of chip has remained almost unchanged.
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Higher packing density means shorter electrical path, giving higher
performance.
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Smaller size gives increased flexibility.
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Reduced power and cooling requirements.
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Fewer interconnections increases reliability.
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CPU Transistor Sizes - Intel
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8086 – 29K transistors, 3µm
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80186 – 29K transistors, 2µm
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80286 – 134k transistors, 1.5µm
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80386 – 855k transistors, 1µm
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80486 – 1.6m transistors, 0.6µm
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Pentium 1 – 4.5m transistors, 0.35µm
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Pentium 2 – 7.5m transistors, 0.35µm
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Pentium 3 – 9.5m transistors, 0.25µm
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Pentium 4 – 42m transistors, 0.18µm
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Pentium m – 140m transistors, 0.13µm
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Pentium D – 230m transistors, 90nm
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Core 2 – 291m transistors, 65nm
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Current Intel architecture: Core I series “Haswell”
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I7: 1.4b transistors, 22nm
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Growth in CPU Transistor Count
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Memory Hierarchy Importance
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1980: No cache memory on CPU.
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1989: First Intel CPU that included cache memory.
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1995: 2-level cache on CPU.
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2003: 3-level cache on CPU.
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2013: 4-level cache on CPU.
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Intel Haswell architecture
w/ integrated Iris Pro Graphics
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How to Increase Performance?
 Pipelining
 On
board cache memory
 Branch
 Data
prediction
flow analysis
 Speculative
execution
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Performance Balance
 CPU
performance increasing
 Memory
capacity increasing
 Memory
speed lagging behind CPU performance
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Core Memory
 1950’s
1
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– 1970’s
core = 1 bit
Polarity determines logical “1” or “0”
 Roughly
 Up
1Mhz clock rate.
to 32kB storage.
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Semiconductor Memory
 1970’s
- Today
Fairchild
 Size of a single core
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i.e. 1 bit of magnetic core storage
Holds 256 bits
 Non-destructive
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SDRAM most common, uses capacitors.
 Much

faster than core
Today: 1.3 – 3.1 Ghz
 Capacity
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read, but volatile
approximately doubles each year.
Today: 64GB per single DIMM
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CPU (Logic) and Memory
Performance Gap
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Solutions
 Increase
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Make DRAM “wider” rather than “deeper”
 Change
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DRAM interface
Cache
 Reduce
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frequency of memory access
More complex cache and cache on chip
 Increase
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number of bits retrieved at one time
interconnection bandwidth
High speed buses
Hierarchy of buses
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Improvements in CPU Organization
and Architecture
 Increase
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Fundamentally due to shrinking logic gate size
 More gates, packed more tightly, increasing clock rate
 Propagation time for signals reduced
 Increase
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
size and speed of caches
Dedicating part of processor chip
 Cache access times drop significantly
 Change
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hardware speed of processor
processor organization and architecture
Increase effective speed of execution
Parallelism
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Problems with Clock Speed and
Logic Density
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Power
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Resistor-Capacitor (RC) delay
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Speed at which electrons flow limited by resistance and capacitance
of metal wires connecting them
Delay increases as RC product increases
Wire interconnects thinner, increasing resistance
Wires closer together, increasing capacitance
Memory latency
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Power density increases with density of logic and clock speed
Dissipating heat
Memory speeds lag processor speeds
Solution:
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More emphasis on organizational and architectural approaches
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Intel CPU Performance
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Increased Cache Capacity
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Typically two or three levels of cache between processor and main
memory.
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Chip density increased
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More cache memory on chip
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Faster cache access
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Pentium chip devoted about 10% of chip area to cache.
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Pentium 4 devotes about 50%.
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Increased Cache Capacity
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More Complex Execution Logic
 Enable
parallel execution of instructions
 Pipeline
works like assembly line
 Different
stages of execution of different instructions
at same time along pipeline
 Superscalar
allows multiple pipelines within
single processor
 Instructions
that do not depend on one another can
be executed in parallel
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Diminishing Returns
 Internal
organization of processors complex
 Can
get a great deal of parallelism
 Further significant increases likely to be relatively
modest
 Benefits
from cache are reaching limit
 Increasing
clock rate runs into power
dissipation problem
 Some
fundamental physical limits are being reached
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New Approach – Multiple Cores
 Multiple

processors on single chip
Large shared cache
 Within
a processor, increase in performance
proportional to square root of increase in complexity
 If
software can use multiple processors, doubling
number of processors almost doubles performance
 So, use
two simpler processors on the chip rather than
one more complex processor
 With

two processors, larger caches are justified
Power consumption of memory logic less than processing logic