University of Portland
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5000 N. Willamette Blvd.
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Phone 503 943 7314
Fax 503 943 7316
Design Document
Project Redwood: Heart Rate Monitor
Contributors:
Daniel Allenby
Preston Boyd
Kyle Yakubisin
Ross Yamaguchi
Approvals
Name
Dr. Hoffbeck
Date
Name
Date
Dr. Ward
Insert checkmark (√) next to name when approved.
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Revision History
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Rev.
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0.1
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24NOV09
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Author
P. Boyd
D. Allenby
P. Boyd
D. Allenby
D. Allenby
D. Allenby
D. Allenby
P. Boyd
D. Allenby
D. Allenby
K. Yakubisin
Reason for Changes
Initial draft
Rough draft
Editing changes
Editing changes
Completed to 0.9
Updates from 0.9 revision
Continued revisions from 0.91
Continued revisions from 0.92
Continued revisions from 0.93
Final revisions to 0.95
Final revisions and approved
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Table of Contents
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Summary.......................................................................................................................
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Introduction ..................................................................................................................
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Background .................................................................................................................. 3
Architecture .................................................................................................................. 4
General Description ................................................................................................................................4
Hardware Architecture ............................................................................................................................4
Power Supply Unit......................................................................... Error! Bookmark not defined.
Sp 02 Sensor................................................................................. Error! Bookmark not defined.
Analog Signal Processor .............................................................. Error! Bookmark not defined.
Digital Processor (MOSIS) ........................................................... Error! Bookmark not defined.
Seven-segment displays .................................................................................................................5
Design ........................................................................................................................... 6
System Block Diagram............................................................................................................................6
Hardware Design ....................................................................................................................................7
Sp 02 Sensor ....................................................................................................................................8
Analog Processing ...........................................................................................................................9
MOSIS Heartbeat Calculator and Output Controller ................................................................... 10
System Clock ................................................................................................................................ 18
Seven-segment displays .............................................................................................................. 19
Approach .............................................................................................................................................. 20
System Test Plan ................................................................................................................................. 20
Test #1: Average user wants to obtain his/her heart rate .......................................................... 21
Test #2: Users heart rate is outside of the acceptable range ..................................................... 21
Development Plan .....................................................................................................22
General Approach ................................................................................................................................ 22
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Assumptions ......................................................................................................................................... 23
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Risks ..................................................................................................................................................... 23
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Milestones .............................................................................................................................................
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Schedule .......................................................................................................................................... 25-29
Overview ........................................................................................................................................ 30
Critical Path ................................................................................................................................... 30
Resources............................................................................................................................................. 30
Conclusions ...............................................................................................................32
Appendices........................................................................................................... 33-34
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List of Figures.
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Figure 1. Block Diagram of.Heart Rate Monitor......................................... Error! Bookmark not defined.
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Figure 2. Team Redwood .
High Level Design...............................................................................................6
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Figure 3: Sp02 Sensor Operation..................................................................................................................8
Figure 4: Low Pass Filter Design………………………………………………………………………..……9
Figure 5: Schmitt Trigger Qualities (Texas Instruments) …………………………………………….……..9
Figure 6: Analog Design Components…………………………………………………………….………..10
Figure 7: MOSIS Heartbeat Calculator and Output Controller ……………………………………………11
Figure 8: MOSIS Divider unit ...................................................................................................................... 13
Figure 9. Division Algorithm. ....................................................................................................................... 14
Figure 10: BCD Algorithm ........................................................................................................................... 15
Figure 11. MOSIS Gate Logic Schematic. ................................................................................................. 16
Figure 12. MOSIS Gate Logic Schematic (chip) ....................................................................................... 17
Figure 13. System Clock. ............................................................................................................................ 18
Figure 14. Driver and Display configuration……………………………………………………………….. 19
Figure 15. Overall Development Process. ................................................................................................. 20
Figure 16. Team Redwood's Schedule ................................................................................................. 25-29
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List of Tables .
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. Process Timeframe. ................................................................................. 22
Table 1. Overall Development
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Table 2. Team Redwood’s.Risks................................................................................................................ 23
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Table 3. Team Redwood’s Milestones…………………………………………………………………….. 24
Table 4. Budget. .......................................................................................................................................... 31
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Summary
This document is written and designed for primary use by the faculty of the University of
Portland, the members of team Redwood, the team’s industry representative Andrew Owings
of Nike, and the fellow students in the Electrical Engineering/Computer Science Department of
the University of Portland.
Project Redwood is a Heart Rate Monitor that implements a custom designed CMOS VLSI
chip using MOSIS technology and a Nonin brand disposable heart rate sensor. University of
Portland students will be able to use this prototype to display a user’s heart rate. This design
document discusses comprehensive, low-level detailed workings of the hardware architecture
as well as the design. The document also provides a technical foundation of the
implementation used in Project Redwood.
Chapter 4, Architecture, offers an explanation of all parts of the system from start to finish. The
hardware section illustrates a high-level system block diagram (Figure 3), followed by
descriptions of all parts contained in the diagram. Chapter 5, Design Overview, contains the
bulk of information within the document, which primarily highlights the operation of the MOSIS
chip. While Chapter 4 describes each individual piece of the heart rate monitor, Chapter 5
states how each part will work and interface with the others.xxxxxxxxxxxxxxxxxxxxxxx
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Introduction
The purpose of this document is to present a clear detailed description of the architecture and
design of Project Redwood for any college level engineering student, as well as faculty. The
document is not only intended to create a clear vision for the design engineers of Project
Redwood, but also provides a detailed view of the project’s inner workings for the users of the
prototype. This document will give detailed descriptions of how the heart rate monitor works
and how each of the components interfaces with one another.
The document is broken down into various sections: the background section provides
motivation for the design and implementation of Project Redwood. The architecture section
describes the components of the hardware. The design chapter contains a hardware design
section which describes how individual parts work within each component. Finally, the
conclusion highlights the major themes of the document.
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Background
Heart rate (or pulse rate) is a term used to express the number of heartbeats per unit time,
generally represented in a beats per minute format. Heart rate monitors are used in daily
situations from aspiring athletes checking to see if they are overtraining, to doctors monitoring
their patients’ health. A person’s heart rate can indicate many things about their health, from
blood pressure irregularities to certain diseases like Heart Arrhythmia (irregular heartbeats).
The heart is a crucial element to life, which is why the majority of overnight hospital patients
are connected to electrocardiograph (EKG) machines monitoring their heart rate, because if
the heart fails, the rest of the body will follow.
The measuring of one’s heart rate generally consists of three major parts: an analog input
pulse train taken from the user, a conversion of this signal to digital format, and a digital signalprocessing unit, which will be represented by the MOSIS chip. The analog input will be
measured using a standard disposable fingertip sensor, similar to those found in hospitals. For
Team Redwood, the analog signal processing unit will be a circuit capable of taking an input
signal and first filtering out the noise, then amplifying and reshaping the signal so it can be sent
to the digital signal processor, which in turn will calculate heart rate in beats per minute.
The hardware performing the digital processing will be a 5V MOSIS technology chip. The
MOSIS chip is large array of MOSFET transistors arranged in a pattern to represent simple
logic gates such as AND or NAND. The MOSIS chip is first laid out in a program called B^2
Logic, where Team Redwood will design a schematic of the gates for the factory, and upon
completion, is sent to a sponsoring company for the manufacturing of a VLSI chip. VLSI
stands for Very Large Scale Integrated circuit. The chip will be composed of several thousand
transistors placed on a single integrated circuit. VLSI technology is used in almost all
electronics from computer processors to embedded systems. The VLSI chip will be fabricated
by the MOSIS Educational Program, which is based out of the University of Southern
California.
Finally, after all the calculations are completed, the data will be sent to three, seven-segmentdisplay, light emitting diodes, which will display the user’s heart rate in a beats per minute
format.
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Architecture
Team Redwood is designing and constructing a Heart Rate Monitor that will be used by
attaching a Sp02 sensor onto the user’s finger. Via optical methods the sensor is able to detect
a heartbeat from the user. Once the signal has been passed through a filter to eliminate noise,
it will be amplified and sequenced into a format that can then be sent to the MOSIS chip. The
MOSIS chip will then calculate the user’s heart rate which will be output to 3 seven-segment
light emitting diode displays.
General Description
The process of designing Team Redwood’s heart rate monitor will follow four steps in order to
obtain proper implementation (see Figure 1). The device is intended to be as user friendly as
the design constraints will allow.
Sp02 Sensor
Analog Signal
Processing
Seven-Segment
Displays
Digital
Processing
(MOSIS)
Figure 1. Block Diagram of Heart Rate Monitor
With the input of a 5V power source and a signal from a user, the sensor will generate an
analog output signal representing the user’s blood pressure. The signal will then be processed
into digital format by identifying spikes in the blood pressure, where each spike represents the
user’s heartbeat. The digital signal will be input to the MOSIS chip. The MOSIS chip will handle
all of the digital processing. The signal will then output three BCD digits to a decoder, which will
process it and make it available to the three seven-segment LED displays, and finally display
the user’s current heart rate as beats per minute.
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Hardware Architecture
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Power Supply: .
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The power supply will handle the demands of voltages to all the devices used, including
supporting the heart rate sensor and the rest of the circuitry, which will require a maximum
input of 15V to drive the LED’s. Also, a 3-Amp current source will be obtained from a lab
power supply to drive the device. The power supply will be connected to a standard wall outlet
generating 115-VAC at a frequency of 60 Hz, and selected for its specific values.
Sp02 Sensor:
The Sp02 sensor is an infrared LED and a photodiode. The photodiode is reverse-biased with
5V peak-to-peak voltage and connected to a source of amplification, the LED power will be
supplied by a DC source.
Analog Signal Processor:
The signal from the Sp02 sensor will be processed through a low pass filter in order to remove
the extraneous noise received in addition to the user’s heart rate, amplified using a 741
operational amplifier to gain an amplitude of 5V, and then sent into a Schmitt Trigger in order
to provide a square wave output signal which the MOSIS can then process. The desired
signal coming into the MOSIS is a 5V rectangular wave, with a pulse representing each heart
beat.
Digital Processor (MOSIS):
The MOSIS chip will receive its input from the analog processing unit. The function of using a
MOSIS chip being that the majority of the digital logic is located on one device. All inputs from
the analog processing unit (mentioned above) and outputs to the digital display are connected
to the MOSIS chip through buffers for protection. Following will be an in depth discussion of
the MOSIS chip design.
Seven-Segment Displays:
Three seven-segment displays will be used to display all possible heart rates the system can
output. The size of each viewing display is 5.69 cm by 3.25 cm (2.24in by 1.28in) for each digit,
which should be relatively easy to view by the user. Considering that the user should not be
more than five feet from the device at any time, a user with average vision should be able to
read the device with normal non-disruptive lighting conditions.
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System Block Diagram
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The basic components of Team Redwood’s project are displayed in Figure 2.
SpO2 Sensor
Analog Signal
Processing Circuits
MOSIS Chip
(DP, ALU, Output
Controller)
System
Clock
LED
Drivers
Seven-Segment
Displays
Figure 2. Team Redwood High Level Design.

The system will use a standard disposable Nonin brand Sp02 sensor to capture a signal
representing the light passing through the user’s hand. This signal that is captured will
show changes in blood pressure from the user. Those changes represent a heart beat
which can be determined and later processed.
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Next the signal from the sensor will be filtered and cleaned up to 5V pulses that represent
each heartbeat. The time between pulses and the duration of the pulses must be greater
than the period of the clock signal.
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The clock signal for the MOSIS is 960 Hertz. The clock rate was selected due to the range
of values that need to be calculated to reach certain requirements, range of accuracy
needed for the requirements, acceptable response time for the MOSIS chip to operate,
and being able to be obtained from an ECS-100 Series clock oscillator with a frequency of
1.2288 MHz.
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The MOSIS Chip will receive the output pulse signal from the analog circuitry, calculate
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the correct heartbeat, and deliver the output in the form of three, four-bit BCD digits to the
LED Drivers. .
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. will then take the BCD values from the MOSIS chip and convert them to
The LED Drivers
an acceptable. format for the seven-segment displays. The seven-segment displays will
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then illuminate the proper LED’s in order for the user to view their heart rate.
Power Supply
To supply power to the system, external lab power supplies will be used for the
implementation. The MOSIS and clock circuitry, as well as the analog components, will
require 5 VDC to operate, and the driver will require 15 VDC as well as -15 VDC for the
amplifier, which will be obtained from a lab power supply DC voltage source connected to a
standard wall outlet.
SpO2 Sensor
The Sp02 sensor records the efficiency of hemoglobin in blood that passes through a finger,
as read by a light emitting diode. This sensor outputs a signal containing a vast amount of
information, including hemoglobin efficiency, which will be highlighted in the Hardware Design
section.
Analog Signal Processing Circuits
The information from the fingertip sensor must then be characterized and processed by analog
circuits which will be made up of a filter and a Schmitt Trigger. Both of these components act
together in order to clean up the signal into a format that the MOSIS chip can accurately
process. Further detail can be found in chapter six.
MOSIS Chip
The convenience of using a MOSIS chip is that all digital logic is located on one device. All
analog inputs and outputs are connected to the MOSIS. The following Hardware Design
section contains an in depth discussion of the MOSIS chip design.
LED Drivers
The LED Drivers consist of three Texas Instruments SN74LS47N LED drivers that will take the
BCD output from the MOSIS and output a signal to the seven-segment displays to be read by
the user or other parties.
LED Seven-Segment Displays
For the display, three Lumex LDS-CD16RI’s will be used. The inputs will be taken from the
LED drivers and the heart rate will be shown on the displays.
System Clock
The clock circuitry will use 74LS TTL technology to divide down the clock signal from the ECS100 series oscillator to 960 Hz for the MOSIS chip.
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Sp02 sensors operate on the principles of pulse oximetry.
Oxyhemoglobin and
deoxyhemoglobin differ in their absorption of red and infrared light (spectrophotometry), the
volume of arterial blood in tissue and the light absorbed by the blood changes during the pulse
(plethysmography). A pulse oximeter determines Sp02 by passing red and infrared light into
an arteriolar bed and measuring changes in light absorption during the pulsatile cycle. Red
and infrared low-voltage light emitting diodes in the oximetry sensor serve as light sources; a
photo diode serves as the photo detector.
Figure 3: Sp02 Sensor operation
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Analog Processing
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A low-pass filter .is a filter that passes low-frequency signals but attenuates (reduces the
amplitude of) signals
. with frequencies higher than the cutoff frequency. For Team Redwood’s
design, this type of filter will be necessary to eliminate frequencies above a cutoff frequency of
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about 1 kHz. Since it is in the form of a triangle pulse train, the max fundamental frequency
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should be approximately 4 Hz. This can be accomplishing using values of R2 = 47Mohms, R1
= 1k, and C = 4.3pF, which are calculated using the formula 1/R2*C. Sometimes, a simple
gain amplifier (as opposed to the very-high-gain operation amplifier) is turned into a low-pass
filter by simply adding a feedback capacitor C. This feedback decreases the frequency
response at high frequencies via the Miller effect, and helps to avoid oscillation in the amplifier.
This will act as Team Redwood’s low pass filter, in order to achieve a specific gain by
regulating R1 values. The formula for gain in the 741 Operational Amplifier is simply -R2/R1,
where both values can be varied in order to achieve optimum gain.
Figure 4: Low Pass Filter
In electronics, a Schmitt trigger is a comparator circuit that incorporates positive feedback.
When the input is higher than a certain chosen threshold, the output is high; when the input is
below another (lower) chosen threshold, the output is low; when the input is between the two,
the output retains its value. Schmitt trigger devices are typically used in open loop
configurations for noise immunity and closed loop positive feedback configurations to
implement multivibrators. Team Redwood will be implementing an SN54HC14 Texas
Instruments Schmitt trigger in order to truncate the portions of the signal that are unusable to
the MOSIS chip.
Figure 5: Schmitt Trigger Qualities (Texas Instruments)
The effect of using a Schmitt trigger (B) instead of a Comparator (A), on an example signal (U).
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Team Redwood intends to use the block diagram in figure 6 to connect the analog processing
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together. This will allow for the proper output to be generated that will enable the MOSIS
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design to work effectively. It consists of the Sp02 Sensor, Low Pass Filter, and the Schmitt
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Trigger.
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Figure 6: Analog Design Components
MOSIS Heartbeat Calculator and Output Controller
The following is a basic block diagram of the MOSIS chip, later on a further explanation will be
provided for each of the blocks. In order to simplify the diagram it does not include clock
connections to components, but the clock is connected to the Divider Unit, the sampler, the
counters, and the registers.
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Buffer
11-Bit
Counter
11-Bit
Register
Divider Unit
Comparator
Binary to BCD
Converter
Clock
12-Bit
Register
10-Bit
Counter
Figure 7: MOSIS Heartbeat Calculator and Output Controller
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The Heartbeat Calculator and Controller Chip will only require two inputs, which will be a 1-bit
clock signal and a 1-bit Beat signal. The Beat signal will be a logic high signal each time a
heartbeat is detected from the sensor. The purpose of the chip will be to convert the beats into
a value that represents heartbeats per minute by counting the time between each rising edge
of the Beat signal. With the value of the beats obtained, a calculation takes place in the BCD
algorithm.
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The first process is the Sampler which consists of 2 D Flip-Flops and an AND gate. It is a
simple circuit that converts a step or constant value of logic 1 to a pulse of logic 1 for one clock
cycle. This will allow for a good reset signal for the rest of the circuit. The reason why the
sampler is needed is due to the inconsistency of input. More specifically when the input Beat is
set to one, it is impossible to guess how long the input will remain at 1. If we were to use this
signal for resetting the registers and counters, not only would the circuit be constantly resetting
throughout the duration of the logic 1 pulse, but it would effect the timing for the circuit. So
converting the input into a pulse of 1 that lasts one clock cycle allows for the circuit to be reset
in one clock cycle, and will not interfere with timing.
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Heart
Rate
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Along with the value stored in the 11-bit Register and other control signals from sub-circuits, an
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8-bit value will be output from the divider unit representing the desired output. The final BCD
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Converter, 12-bit Register, and 10-bit Counter are used to format the output for the drivers and
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control the approximately
. digits.1 second refresh rate of the displays. The output of the circuit is
then three 4-bit BCD
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
The next process is the 11-bit Counter. The 11-bit Counter counts from 0 to 2047. Under
normal operating conditions whenever a heartbeat is detected the counter is then reset to zero
and begins counting again. If the counter reaches 2047 the counter stops and holds 2047.
This triggers the control signal that will lead to the Divider Unit and cause the output to change
to zero. The reason for this is that if the time between heartbeats is too great such as when the
counter reaches 2047, then the heart rate is < 28 beats per minute, i.e. if heart rate detected is
less than 28 beats per minute then the heart rate is assumed to be 0. Another case that could
occur is if no user is connect to the system then the chip would still read zero bpm which is
acceptable as output since there is no input. Once a heartbeat pulse is sent to the counter the
counter is reset to zero and begins again.
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The 11-Bit Register which is tied directly to the 11-Bit Counter has the purpose of storing the
information from the 11-Bit Counter. More specifically when the 11-Bit Register receives the
heartbeat pulse signal, it grabs the current value of the count from the 11-Bit Counter. This
means the 11-Bit Register holds the value representing the time between heartbeats. The
value in this register is then used as input to the Divider Unit. This is the independent value of
the equation which will be later discussed. Also, buffer represents a delay of one clock cycle.
The heartbeat pulse (pulse signal from the Sampler) is delayed since the 11-Bit Register
induces a delay, so if the Divider Unit were to be reset on the same clock cycle as the
Register, it would grab the previous value instead of the current value of beats.

The output of the 11-Bit Register is also used to determine another control signal. A second
case the system could encounter is if the heart rate detected is too high. Regardless of the
cause for the high rate, the signal must be accounted for. A simple comparator is used to
check for that case. If the beats from the counter is less than or equal to 230 then the rate
detected is above 250 beats per minute. If this is the case the control signal from the circuit is
set to logic 1 and will be used to correct the output. If not corrected, the Divider Unit will output
values not only above the specifications listed in the Functional Specifications document and
accuracy is lost at those high rates. Therefore an error output is requested instead. The
reason for this threshold is due to a few factors: One is that in general the human heart will not
operate above 250 beats per minute without fibrillation and other problems, second is 250
being a common industry standard for medical equipment, and third is the larger number
would require more bits and circuitry to operate so this cutoff simplifies implementation.

The next section, which by far is probably the most complex, is the Divider Unit. The purpose
of the Divider Unit is to implement the following equation and determine the output value of the
system as an 8-bit binary number. The Beats value is the value of the beats counted between
heartbeats and is stored in the 11-bit Register, f0 is the system clock at 960 Hz.
Heartrate 
f 0  60 57600

Beats
Beats
Since f0 is 960 Hz for our system the equation can be simplified
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The following is a block diagram of the Divider Unit.
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IF HR=0
IF HR=E
16-Bit
Quotient
Register
32-Bit
Divisor
Register
32-Bit
Subtraction
8-Bit
Output
Register
32-Bit
Multiplexer
32-Bit
Remainder
Register
5-Bit
Counter
Figure 8: MOSIS Divider unit
A note about Figure 8 is that the clock and reset connections are not shown to simplify the
figure, but every register and counter is connected to the Reset input and clock.
To carry out the basic division process, the Divisor, Remainder, and Quotient Register is
needed along with the multiplexer and Subtraction circuit. The Subtraction circuit is just a full
adder with a carry in of 1 for the least significant bit; the input from the divisor is the inverse of
the real value. In effect it creates a subtraction circuit that can be used to carry out the process
that will be explained briefly. The multiplexer is used to determine the next value for the
Remainder Register which either does not change, or is the result of the Remainder minus the
Divisor.
Also in the Divider Unit is an 8-Bit Output Register and a 5-Bit Counter. The 8-Bit Register has
internal multiplexers that when given inputs from the external control signals and the division
circuits, are able to determine the correct output: either all 1’s which represent an error, all 0’s
which represent zero, or an 8-bit binary number that gives the heart rate of the user.
The 5-Bit Counter counts the number of cycles the divider circuit has gone through and when
the count reaches 16, a control signal is sent to the Output Register making the register
capture the current value from the Quotient Register, this will be the heart rate that has been
calculated.
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Heart
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Some additional features designed into the registers are as follows:
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. resets to 57600 for calculation purposes.
Remainder Register
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
Divisor Register resets to the Beats input and is a shift right register meaning each clock cycle
the register shifts its bits towards the least significant bit, enabling the new bit to load as zero.

Quotient Register resets to zero and is a shift left register meaning each clock cycle the bits
are shifted towards the most significant bit and the new bit is 1 if the value is positive or 0 if the
value is negative.
To understand the rest of the dividing circuits refer to figure 9, which shows the process which
the dividing circuits implement.
Start
1. Subtract the Divisor register from
the Remainder register and place
the result in the Remainder register.
Remainder < 0
Remainder ≥ 0
Test Remainder
2a. Shift the Quotient register to the
left, setting the most significant bit to 1
2b. Restore the original value by
adding the Divisor register to the
Remainder register and place the sum
in the Remainder register. Also shift
the Quotient register to the left, setting
the new least significant bit to 0
3. Shift the Divisor register right 1 bit
No: < 17 Repetitions
17th repetition?
Yes: 17 repetitions
Done
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. Figure 9: Division Algorithm
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After the Dividing.Unit is the Binary to BCD converter. In order to generate this circuit, Team
Redwood had to.understand how binary and decimal relate to each other. A circuit was
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PAGE 15
implemented inside the MOSIS chip in order execute the function of a binary to binary coded
decimal converter (BCD).
In the diagram below, each four-bit block (i.e. C1-C7) represents a conditional adder, which
adds 3 if the input is 5 or greater. For example: if the input into the block is a binary 6 (0110),
then the output is converted to a binary 9 (1001). If the input is less than 5, then the input is
copied to the output. In between each block is a one-bit shift left, which is seen by connecting
the bottom 3 outputs from the previous block with the next highest bit in the ten-bit word. As
seen in the following diagram, this process is repeated a total of 7 times before finally reaching
the BCD output.
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Figure 10: BCD Algorithm
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. chip there is a 10-Bit Counter and a 12-Bit Register. The 10-Bit Counter
Lastly, in the MOSIS
. from 0 to 1024 and repeats. Every time the counter reaches 1024 it sends
continuously counts
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a control signal to the register to update its value from the Binary to BCD Converter. This
functionality acts to refresh the output.
The display will update approximately every second instead of being attached to the varying
heart beats. This will allow for easy interpretation by the user. The following B^2 logic
screenshot is Team Redwood’s final MOSIS Logic Gate Schematic, which has been approved
as functional and ordered from the University of Southern California’s research laboratories.
Figure 11: MOSIS Gate Logic Schematic
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. mask layout of the MOSIS Chip.
The following is the
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Figure 12: MOSIS Gate Logic Schematic (chip)
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System Clock.
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The system clock will be implemented using 74LS TTL technology to divide down the clock
signal from the ECS-100 series oscillator to 960 Hz for the MOSIS chip. Figure 13 illustrates
how the System Clock will be implemented.
ECS-100 Clock
CLK
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Figure 13: System Clock
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. Drivers and Seven-Segment Displays
Seven-Segment Display
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The following figure shows how the Texas Instrument SN74LS47N drivers will be implemented
with the Lumex LDS-CD16RI Seven Segment displays using the output from the MOSIS chip.
Drivers
HR0_(0-3)
MOSIS Heart
Rate Calculator
and Output
Controller
HR1_(0-3)
HR2_(0-3)
TI Driver
TI Driver
TI Driver
Displays
7-Bit Signal
8
7-Bit Signal
8
7-Bit Signal
8
Figure 14: Driver and Display Configuration
The 7-segment display has 10 inputs (refer to datasheet), a common cathode input which
is grounded, and the rest are 7 bits from the driver. Any further inputs will be grounded
since they are decimals or commas. As for the driver, besides the ground and power
inputs, it will consist of 4 pins in and 7 pins out. If there are any issues with voltages
between the drivers and the display, a simple voltage divider circuit will be added to
convert 15V outputs to 10 V outputs and maintain 0V.
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Approach
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Team Redwood’s approach to designing the heart rate monitor (see Figure 15) is to assign
simple tasks to all four members in such a way that each individual is not overwhelmed by any
single workload. One team member has been responsible for the MOSIS chip design, and
has had the full support of the team in order to accomplish this goal in a timely manner. The
team has met all necessary deadlines by staying ahead of the workload and maintaining a
constant attitude of priority for this project. Once the design is complete, and Team Redwood
returns to work throughout the spring of 2010, the implementation of the design will begin in
order to produce a device by Founder’s Day.
Acquire Working
Heart Rate Finger
Sensor
Design Analog to
Digital Processing
Presentation
prepared by
Founder's Day
MOSIS CHIP must
be able to properly
process input
Figure 15. Overall development process diagram
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System Test Plan.
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After running tests on each of the individual segments of the project (Sp02 sensor, analog
processing, MOSIS chip, and seven-segment displays) and they are pieced together into the
final project, Team Redwood will perform the following tests to verify functionality.
Test #1: Average user wants to obtain his/her heart rate
In this test, the user turns on the prototype with no complications.
Initial Conditions:
1. The system is plugged in and ready to operate.
2. The user is currently wearing the device and cooperating.
Steps to run the test case:
1. The user has his/her finger in the Sp02 sensor.
2. Wait for the 2 second maximum time period for the heart rate to be displayed.
Expected behavior: The user observes his/her heart rate on the seven-segment displays,
which will be verified for accuracy using a commercial heart rate monitor.
Test #2: User’s heart rate outside of the acceptable range
In this test, the user’s heart rate is outside of the specified range, either too high (above 250
BPM) or too low (zero), which will be simulated using a function generator.
Initial Conditions:
1. The system is plugged in and ready to operate.
2. The device is plugged in to a function generator to simulate a user’s heartbeat.
Steps to run the test case:
1. The device is hooked up to a function generator, simulating a signal above 250 BPM.
2. Wait for the 2 second maximum time period for the heart rate to be displayed.
3. Observe system output.
4. The device is hooked up to a function generator, simulating a signal of 0 BPM.
5. Wait for the 2 second maximum time period for the heart rate to be displayed.
6. Observe system output.
Expected behavior: The user observes a blank display if heart rate is too high, and “000” if
too low.
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DESIGN
PROJECT REDWOOD
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Development Plan
Now that the design has been described, the following is Team Redwood’s development
process behind that design.
General Approach
Team Redwood’s approach to designing the device is to divide the workload amongst the four
team members and work on various sections of the project simultaneously, in order to finally
combine all project components together successfully. Team one (consisting of Kyle and
Preston) is working on the digital section and the output, whereas team two (Dan and Ross) is
working on the analog section of the project. Each team will work together in the labs until they
have gained proficient understanding of their sections, which they will then break off to
individuals to write up the documentation.
Team one’s main focus has been the MOSIS chip, with a hard deadline of November 25th.
With this being set, team two was given the task of picking up the majority of the
documentation, leaving team one with plenty of time to finish the MOSIS. On the other hand,
team two will be spending their spare time in the lab to obtain a working signal, so that upon
returning from winter break, we can start building and debugging the heart rate sensor to have
it working by Founder’s Day.
The development plan is similar to the development process from the Functional Specifications
document 1.0. The purpose of this section is to give a detailed plan on how Team Redwood
will design and implement the heart rate sensor in the following months.
Table 1. Overall Development Process Timeframe.
September October November December January February
Ross
2, 3
2, 3
4, 6
4, 6, 10
8
9
Kyle
2, 3
2, 3, 1
4, 1, 5
4, 10
7, 8
9
Dan
2, 3
2, 3
4, 6
4, 6, 10
8
9
Preston
2, 3
2, 3, 1
4, 1, 5
4, 10
7, 8
9
Key:
1 = Design MOSIS
2 = Research sp02 Sensors
3 = Functional Specification
4 = Design Document
5 = Test/Debug MOSIS
6 = Design analog circuit to take sp02 sensor input and convert to digital
7 = Burn CPLDs
8 = Combine digital and analog parts of the project
9 = Test/Debug completed heart rate sensor
10 = Order parts
UNIVERSITY OF PORTLAND
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March
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9
9
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April
11, 12
11, 12
11, 12
11, 12
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11= Prepare Founder’s Day presentation
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12 = Final Report Document
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Assumptions
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PAGE 23
It is an assumption that the user is at or near sea level, breathing normal room
temperature air, and operating at a measurement of one atmosphere causing
them to maintain a normal heartbeat. Therefore these environmental conditions
may be disregarded for the design.
Risks
The following are key risks currently seen by Team Redwood, described in the following table,
as well as the severity and likelihood of each problem. Immediately following the table is a
more in depth description of each risk.
Table 2. Team Redwood’s Risks
Risk
Severity
Likelihood
Analog Signal Processing
Moderate
Moderate
Digital Signal Processing
Low
Low
Fingertip Sensor
High
Moderate
Analog Signal Processing:
Since the acquired finger sensor that is being utilized in the design is receiving its signal from a
biological source, there is a high chance that the signal will be extremely noisy. That noise will
in turn make the signal more difficult. There are a few design tools available for
implementation, which would aid in reducing/eliminating noise (i.e. Schmitt Trigger design).
Digital Signal Processing:
In order to display the user’s heart rate on the three seven-segment displays there is some
digital processing that must be done on the MOSIS chip. Without this digital processing there
is no way for calculations of the heart rate to be produced. However, these are inherently
simple calculations provided a clean input signal for the chip, which could be performed using
a CPLD as a backup device. The risk is that Team Redwood will receive the MOSIS chip late,
or damaged. Fortunately the likelihood of this risk is low.
Fingertip Sensor:
The fingertip sensor Team Redwood is intending on designing the project around has been
more than difficult. The complex signal received from the Sp02 sensor being more than just a
BPM signal, must be filtered prior to processing. If a replacement is necessary, an EKG
design will be implemented as a simple substitution. Should there be an unsolvable problem
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
CONTACT: DAN ALLENBY
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with the heart rate sensor, this will cause a high severity of risk to the project; fortunately the
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likelihood of failure is only moderate.
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Milestones
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Description
PAGE 24
Completion
Date
1
Functional Spec 1.0
16 OCT 09
2
Preliminary MOSIS to Dr. Osterberg
30 OCT 09
3
Order all parts
14 NOV 09
4
Test/Debug complete MOSIS
17 NOV 09
5
Final MOSIS to Dr. Osterberg
24 NOV 09
6
Design 1.0
11 DEC 09
7
Analog filtering circuit built
22 JAN 10
8
Burn CPLDs
29 JAN 10
9
Preliminary System Testing
10 FEB 10
10
System Integration Complete
24 FEB 10
11
Testing/Debugging Complete
12 MAR 10
12
Display Case Assembled
22 MAR 10
13
Founder’s Day Presentation
13 APR 10
14
Final Report 1.0
23 APR 10
Table 3. Team Redwood’s Milestones

Functional Spec 1.0: An overview picture on how the team plans to design and build the
heart rate sensor. Once completed it must be approved by a faculty and industry
representative before being approved to 1.0.

Final MOSIS to Osterberg: The logical design of the MOSIS IC is completed and tested,
then submitted to Dr. Osterberg before being submitted to manufacture.

Analog filtering circuit built: The circuitry described in the design section that is used to
take the analog input from the Sp02 sensor and convert it to a format that the MOSIS can
handle.

Burn CPLDs: Burn CPLDs with the logic created from our MOSIS file so that we may test
and debug the project before the MOSIS arrives.
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Preliminary Testing: Test each section of the project individually to see that everything
.
works before integrating the project together.
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System Integration Complete: All parts/milestones aforementioned will be combined and
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be ready for testing/debugging.
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PAGE 25

Testing/Debugging Complete: The build is tested and debugged to fix any errors and is
working as stated in the design document.

Display Case Assembled: After debugging is completed, final “touch-ups” will be made to
make a presentable project for Founder’s Day.

Founder’s Day Presentation: The completed prototype will be presented by the team to
the University Community and industry representatives.

Final Report 1.0: The final report will be submitted and presented in a formal document to
be approved by the faculty advisors and industry representatives.
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Schedule
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Figure 16. Team Redwood’s Schedule
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CONTACT: DAN ALLENBY
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Schedule Overview
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Team Redwood's.schedule has much overlap due to the fact that many things can be done
simultaneously, and
. do not require other sections to be completed to move forward. While one
team is working on the MOSIS, the other team can be working on the analog sensor and
.
determining its output. The challenge is that everything needs to be assembled in a timely
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matter so that all sections are completed at the same time to combine the necessary parts
together to create a finished project.
Critical Path
Our project has a few dependencies that all add up to one large one. For example, the CPLDs
cannot be programmed without the MOSIS being completed, which in turn leads to the final
project being held up due to having an incomplete MOSIS. Also, without the analog signal
processing circuit built, we cannot run the MOSIS, so that needs to be completed on a timely
matter or else the entire project will be not be finished on time. Each section pulls its own
weight in responsibility, so all of them must be completed on their own for the project to be
successful.
Resources
Personnel:

Daniel Allenby: Team leader, analog processing

Preston Boyd: Executive editor, LCD display

Kyle Yakubisin: MOSIS, web-site maintenance

Ross Yamaguchi: Heart rate finger sensor
UNIVERSITY OF PORTLAND
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CONTACT: DAN ALLENBY
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Preliminary Budget:
. team is allotted a certain amount of money, based on individual needs,
Each senior design
.
and availability. Table 4 lists the approximate parts required for Team Redwood to produce a
.
working heart rate monitor.
.
Table 4. Budget
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DESIGN
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Line
Category
1
1.1
1.2
1.3
1.4
1.5
Materials
Hardware
Hardware
Hardware
Hardware
Materials
1.6
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Number
7-Segment LED Display
Power Supply
LED Driver chip
ECS-100 Oscillator
Miscellaneous/Printing
Analog Signal Processing
Block
Rate
Amount
# of parts
3
1
5
2
1
Subtotal
10.84
50.00
1.44
1.88
32.52
50.00
7.20
3.76
10.00
4
5.00
20.00
TOTAL
123.48
Equipment:





All of the resources available in the Shiley Engineering building, room 306, and the rest of
Shiley Hall
DMM
Oscilloscope
Solder
Soldering iron
Facilities:


Shiley room 306 will be used to construct all parts of the prototype
Shiley room 208 will be used to construct all digital logic circuits
UNIVERSITY OF PORTLAND
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CONTACT: DAN ALLENBY
DESIGN
PROJECT REDWOOD
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Conclusions
This document described the design of Team Redwood’s heart rate monitor. The architecture
of the design explained in Chapter 4 broke the project into its major components, which was
then further explained in the design overview in Chapter 5. The functionality of the hardware
was discussed as parts of the MOSIS chip, and the display was identified using the seven
segment displays. Combining each component together yields a product that will successfully
output a user’s heart rate in beats per minute.
UNIVERSITY OF PORTLAND
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DESIGN
PROJECT REDWOOD
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Appendix
A: Glossary
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BCD: Binary Coded Decimal
BPM: Beats Per-Minute
CMOS: Complementary Metal Oxide Semiconductor
CPLD: Complex Programmable Logic Device
DMM: Digital Multi-Meter
EKG: Electrocardiography
HRM: Heart Rate Monitor
LED: Light Emitting Diode
MOSFET: Metal–Oxide–Semiconductor Field-Effect Transistor
MOSIS: Metal Oxide Semiconductor Implementation Service
VAC: Volts-Alternating Current
VDC: Volts-Direct Current
VLSI: Very Large Scale Integration
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Appendix B: Parts
http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=852334&k=%20X102-ND
http://search.digikey.com/scripts/DkSearch/dksus.dll?vendor=0&keywords=67-1494-ND+
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=296-3712-5-ND
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