Lecture 1b - Review
Kishore C Acharya
Building Semiconductor Devices
• To build semiconductor devices # of carriers
present in the semiconductor must be
increased by adding impurities from Group
III and Group V elements from periodic
table
• Typical impurities
– Group III: Boron
– Group V: Phosphorous
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Increasing Carrier concentration
by Doping
• np = ni2
– n- elrctron concentration, p- hole concentration
– ni = Intrinsic carrier concentration=1010/cc for silicon
• For N type semi conductor
– n = Nd donor concentration [1014 to 1018 /cc] – majority carrier
– p = ni2 /Nd – minority carrier
• For P type semi conductor
– p = Na acceptor concentration [1014 to 1018 /cc] – majority carrier
– n = ni2 /Na – minority carrier
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Energy Levels of Silicon
Vacuum Level
Eground = 0 eV
Conduction Band
Ec = -4.05 eV
Efn = Ec + Eg/2 + kT Ln(Nd/ni)
Ec = Edge of conduction band
Ev = Edge of Valence band
Efp = Fermi Level for P type
Efn = Fermi Level for N type
Eg = Energy gap
kT = 0.025 eV at T = 300º K
Ln(10) = 2.3
Ei = -4.6eV
Ec + Eg/2
Egap = | Eg |, Eg = -1.1 eV
Efp = Ec + Eg/2 + kT Ln(ni/Na)
Ev = -5.15 eV = Ec + Eg
Valence Band
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Fermi Level Calculation Example
For Silicon ni = 1010 /cc
For P type Semiconductor let Na = 1014 /cc
Efp = Ec + Eg/2 + kT Ln(ni/Na)
At t = 27º C, T = 300º K
Efp = -4.05 - .55 + 0.025 Ln(1010 / 1014)
= -4.83 eV
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Fermi Level Calculation Example
For Silicon ni = 1010 /cc
For N type Semiconductor let Nd = 1016 /cc
Efn = Ec + Eg/2 + kT Ln(Nd/ni)
At t = 27º C, T = 300º K
Efn = -4.05 - .55 + 0.025 Ln(1016 / 1010)
= -4.25 eV
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MOS Diode Structure
Vint = (Efm – Efs)/q, Vint =0 once thermodynamic equilibrium is achieved
Vint readjust the charge distribution so that
Efm = Efs , where Efm and Efs are the Fermi Level
of metal and semiconductor respectively
M
e
t
a
l
Oxide
P or N type Semiconductor
Vdiode
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Metal Selection
• Typical
– Aluminum (Al), Ef = -4.1 eV
– N+ poly silicon, Ef = -3.95 eV
• Newer Material
– For N type: Select Efn = -.411  0.2 eV
• titanium, tantalum, zirconium, and hafnium
– For P type: Select Efp = - 5.2  0.2 eV
• platinum, palladium, nickel, cobalt, and ruthenium
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Ideal MOS Diode( Efm = Efp)
Eground = 0
Metal
Oxide
Ptype Semiconductor
Ec
Vdiode = 0
Ei
Efm
Efp
Ev
Difficult to find Matching Metal so that Efm = Efp
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Electron Accumulation for
Vdiode >0 (Inversion)
Vacuum Level
Eground = 0
Metal
Ptype Semiconductor
Vacuum Level
Oxide
Electron accumulation
Causes band bending
Ec
Ei
Efm
Efp
Ev
Vdiode >0
Efm
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Hole Accumulation for Vdiode<0
(Depletion)
Vacuum Level
Eground = 0
Metal
Ptype Semiconductor
Vacuum Level
Oxide
Ec
Efm
Vdiode<0
Ei
Efm
Efp
Ev
Hole accumulation
causes bending
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Real MOS Diode
Vacuum Level
Metal
Eground = 0
Oxide
Ptype Semiconductor
Wfm
Electrons accumulate
After equilibrium
Ec
Wfp
Wfm
Ei
Efp
Ev
Real MOS Diode Efm  Efp
Vint = Efm – Efs generates
fields that readjusts charge
distribution so that Vint = 0
After Equilibrium Efm = Efp
Since Efm went down, it is
similar to applying a positive
Voltage to the metal side.
Electrons accumulated at the
surface and the band on the
semiconductor side became
curved
Wfm = | Efm |
Before Equilibrium
After Equilibrium
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Real MOS Diode Wfm > Wfn
Vacuum Level
Eground = 0
Metal
N type Semiconductor
Vacuum Level
Oxide
Wfm
Ec
Efn
Efm
Ec
Efn
Ei
Wfn
Wfn
Ei
Ev
Wfm = | Efm |
Before Equilibrium
After Equilibrium
Ev
Holes accumulate after equilibrium
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Vs
Cutaway View of MOS transistors
Vg
Vd
Metal
Oxide
Gate
Source
Drain
P+, p=1016
Polysilicon
P+, p=1016
Vs > Vg > Vd
Substrate : N type, n = 1014, p = 106
Bulk
PMOSFET
Bulk must be reverse biased
If Source and Bulk are connected
reverse bias condition is met
Alternative:
Do not connect Bulk and Source
Connect bulk to Vdd
For Conduction Vs > 0 & Vgs  Vt a negative threshold voltage about –1v
This gate voltage is necessary to create a P channel under the oxide layer
Source: Place where carriers originate
Drain: Place where carriers are collected
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Vs
Vg
Vd
Gate
Source
Drain
N+, n=1016
N+, n=1016
Vd > Vg > Vs
Substrate : P type, p = 1014, n = 106
Bulk
NMOSFET
Source: Place where carriers originate
Drain: Place where carriers are collected
Bulk must be reverse biased
If Source and Bulk are connected
reverse bias condition is met
Alternative:
Do not connect Bulk and Source
Connect bulk to ground
For conduction Vd < 0 and Vgs  Vt a positive threshold voltage about 1v
This gate voltage is necessary to create a N channel under the oxide layer
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Carrier and Current flow in MOS
Transistors
Type
Carrier
Carrier Flow
Current flow
PMOS
Hole
S -> D
S -> D
NMOS
Electron
S -> D
D -> S
Direction of Current flow must be consistent with carrier flow
Current always flows from higher to lower potential
For consistency
PMOS- Source must be at higher potential than drain
NMOS - Drain must be at higher potential than source
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Minimum Size MOS Transistor
Channel
P+ or N+
Active Region
P+ or N+
N or P type Semiconductor
Bulk or Substrate

Wminimum


2

2
2


5
2
Lw
Lminimum
 Is called the technology parameter = L/2. All sizes are integer multiple of 
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Condition for Conduction
• Bulk must be reverse biased
– Direct connection (P to Gnd, N to Vdd)
– Connect bulk to one active which becomes source and
proper source connection will reverse bias bulk
• Channel must be created under the oxide layer
– Apply a gate voltage of proper polarity exceeding a
threshold
• Circuit must be connected so that current flow is
consistent with carrier flow
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Quantitative criteria for
conduction
• For NMOSFET
– Vds = Vd – Vs > 0
– Vgs = Vg – Vs  Vtn
– Vbs = Vb – Vs  0
(Vtn > 0, Typical 1V)
• For PMOSFET
– Vds = Vd – Vs < 0
– Vgs = Vg –Vs < Vtp
– Vbs = Vb – Vs  0
(Vtp < 0, Typical –1 V)
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Circuit Symbol
Channel (N)
Channel (P)
Source/Drain
Gate
Bulk (P)
Drsain/Source
NMOSFET
Bulk is P Channel is N
Leakage current (P to N) Bulk to Channel
Source/Drain
Gate
Bulk (N)
Drsain/Source
PMOSFET
Bulk is N Channel is P
Leakage current (P to N) Channel to Bulk
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