EEL4930/5934
Reconfigurable Computing
The state-of-the-art Reconfigurable Computing equipment
available for this course is made possible by a generous grant
from the Rockwell Collins Growth Relationship Grant
Program and an equipment/software donation from Nallatech.
Instructors
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Dr. Greg Stitt
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gstitt@ece.ufl.edu
http://www.gstitt.ece.ufl.edu
Office Hours 3-4 M,W (Benton 323)
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Also, by appointment
Dr. Herman Lam
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hlam@ufl.edu
http://www.hlam.ece.ufl.edu
Larsen 225
Course Website
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2 sites
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http://www.gstitt.ece.ufl.edu/courses/eel4930_5934/
 Linked off my website
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WebCT Vista/E-learning
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http://lss.at.ufl.edu/
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Select e-learning
Login with GatorLink account
Used for posting grades, class discussions
Email Policy
 When sending an email, include the class name in
brackets
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e.g. [EEL5932] Question about project 2
For emails to entire class, use e-learning
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Announcements will be posted both on class website and
e-learning site
Grading
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EEL4930/5934 Grading:
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Mid-term 1: 20% (Wednesday, October 3)
Mid-term 2: 20% (Wednesday, October 31)
Final exam: 20%
Labs/Homework: 10%
Project: 30%
Final grade: curved average of all components
5934 will have different tests, homeworks, and
project
Lab Assignments
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Linked off main website and e-learning
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http://www.hlam.ece.ufl.edu/EEL4930_5934LabsProj/
Intended to familiarize with FPGA
boards, VHDL
Initials labs will be individual
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Will allow groups when using boards
Research Project
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Groups
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Size to be determined based on enrollment
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Likely 2-3 per group
Topic subject to instructor approval
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Will give examples
Good idea - find algorithm in your area, use RC to
improve performance
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Imaging processing, bioinformatics, CAD, etc.
If interested in research, make an appointment
with me
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Will try to find a project that will helps towards degree
Reading Material
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Textbook: The Design Warrior’s Guide
to FPGAs
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Supplemented by research papers
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C. Maxfield
ISBN: 978-0750677045
Check class website for daily requirements
Will also post slides when used
Optional books also listed in syllabus
Prerequisites
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Digital design
Architecture
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Controller/Datapath
Memory Heirarchy
Pipelining
More listed in syllabus
Assumes no knowledge of
reconfigurable computing
Goals
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Understanding of issues related to RC
(reconfigurable computing)
Detailed investigation of a specific
problem
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Project/Research Paper
Publish!
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Best submissions will be submitted
Academic Dishonesty
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Unless told otherwise, labs and homework
assignments must be done individually
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Groups must obtain permission to use larger size
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May be allowed for difficult projects
Collaboration is allowed (and encouraged), but within
limits
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All assignments will be checked for cheating
Can discuss problems, how to use tools etc.
Cannot show code, solutions, etc.
Cheating penalties
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First instance - 0 on corresponding assignment
Second - 0 for entire class
Attendance Policy
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Attendance is optional, but highly
recommended
If you are sick, stay at home!
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If obviously sick, you will be asked to leave
Missed tests cannot be retaken, except
with doctor’s note
What is Reconfigurable Computing?
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Reconfigurable computing (RC) is the
study of architectures that can adapt
(after fabrication) to a specific
application or application domain
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Involves architecture, design strategies,
tool flows, CAD, languages, algorithms
What is Reconfigurable Computing?
Alternatively, RC is a way of implementing circuits
without fabricating a device
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Essentially allows circuits to be implemented as “software”
“circuits” are no longer the same thing as “hardware”
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Microprocessor
Binaries
RC devices are programmable by downloading bits - just like
software
a
b
001010010
FPGA Binaries
(Bitfile)
001010010
Bits
loaded
into
program
memory
0010
…
Processor
Processor
Bits
loaded
into
CLBs,
SMs, etc.
0010
…
FPGA
Processor
x
c
y
Why is RC important?
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Tremendous performance advantages
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Implements applications as custom circuit
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In some cases, > 100x faster than microprocessor
Alternatively, similar performances as large cluster
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But much smaller
Example:
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Software executes sequentially
RC executes all multiplications in parallel
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for (i=0; i < 16; i++)
y += c[i] * x[i]
Additions become tree of adders
Even with slower clock, RC is much faster
Performance difference even greater for larger input
sizes
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SW time increases linearly
RC time is basically O(log2(n)) - If enough area is available
When should RC be used?
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When it provides the cheapest solution
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Generally, depends on volume of devices
Total cost = NRE + Volume*unit_cost
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NRE: non-recurring engineering cost
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One-time cost involved in creating design
Volume: expected units to be sold
Unit cost: cost of each individual unit
RC is typically more cost effective for low
volume devices
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RC: low NRE, high unit cost
ASIC: very high NRE, low unit cost
When should RC be used?
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When circuit may have to be modified
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Can’t change ASIC - hardware
Can change circuit implemented in FPGA
Uses
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When standards change
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Codec changes after devices fabricated
Allows addition of new features to existing devices
“Partial reconfiguration” allows virtual fabric size analagous to virtual memory
Without RC
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Anything that may have to be reconfigured is
implemented in software
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Performance loss
RC Markets
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Embedded Systems
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RC achieves performance close to ASIC,
sometimes at much lower cost
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Many embedded systems still use ASIC due to high
volume
Reconfigurablilty!
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If standards changes, architecture is not fixed
Can add new features after production
RC Markets
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High-performance computing - HPC
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Cray XD-1
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SGI Altix
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12 AMD Opterons, FPGAs
64 Itaniums, FPGAs
IBM Chameleon
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Cell processor, FPGAs
RC Markets
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General-purpose computing???
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Ideal situation: desktop machine/OS uses RC to
speedup up all applications
Problems
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RC can be very fast, but not for all applications
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Generally requires parallel algorithms
Coding constructs used in many applications not
appropriate for hardware
Subject of tremendous amount of past and likely
future research
CHREC
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NSF Center for High-Performance
Reconfigurable Computing
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http://www.chrec.ufl.edu/