Plenary, Device Research Conference, June 22, 2015, Ohio State
Transistors for VLSI, for Wireless:
A View Forwards Through Fog
Mark Rodwell, UCSB
Low-voltage devices
P. Long, E. Wilson, S. Mehrotra, M. Povolotskyi, G. Klimeck: Purdue
III-V MOS
C.-Y. Huang, S. Lee*, A.C. Gossard,
V. Chobpattanna, S. Stemmer, B. Thibeault, W. Mitchell : UCSB
InP HBT:
J. Rode**, P. Choudhary, A.C. Gossard, B. Thibeault, W. Mitchell: UCSB
M. Urteaga, B. Brar: Teledyne Scientific and Imaging
Now with: *IBM, **Intel
1
Co-authors
In(Ga)As MOS
Cheng-Ying
Huang
Sanghoon
Lee
THz InP HBT
Varista
Chobpattanna
Prof. Susanne
Stemmer
Steep FET design
Pengyu
Long
Evan
Wilson
Johann
Rode
III-V EPI
Prof. Michael Prof. Gerhard
Povolotski
Klimeck
..and at Teledyne (HBT):
Prof. Art
Gossard
Prateek
Choudhary
Process
Brian
Thibeault
Bill
Mitchell
Miguel Urteaga, Bobby Brar
2
What's a Professor to do ?
Transistors approaching scaling limits
Process technology: it's getting hard.
extreme resolution, complex process, many steps
exhausted students
How can we steer the future of VLSI, of wireless ?
Beyond yet another new semiconductor (be it 3D or 2...)
let's explore other options.
3
VLSI
44
What does VLSI need ?
Small transistors: plentiful, cheap
Small transistors→ short wires
small delay CVDD /I
low energy CVDD2/2
Small-area electronics is key
3
10
60
mV/decade
2
10
800
600
1
10
400
0
10
d
Low leakage current
thermal: Ioff > Ion*exp(-qVDD/kT)
want low VDD yet low Ioff.
I , Amps/meter
1000
200
Want:
0
Large dI/dV above threshold
0
Steeper than thermal below threshold
-1
10
0
0.1 0.2 0.3 0.4 0.5
V
gs
0.1 0.2 0.3 0.4 0.5
V
gs
5
First: Steep-subthreshold-swing transistors
1000
800
60
mV/decade
100
600
10
400
1
d
I , Amps/meter
1000
200
0.1
0
0
0.1 0.2 0.3 0.4 0.5
V
gs
0
0.1 0.2 0.3 0.4 0.5
V
gs
Characteristics steeper than thermal→ lower supply voltage
6
Tunnel FETs: truncating the thermal distribution
Normal
T-FET
J. Appenzeller et al.,
IEEE TED, Dec. 2005
Source bandgap truncates thermal distribution
Must cross bandgap: tunneling
Fix (?): broken-gap heterojunction
7
Tunnel FETs: are prospects good ?
Useful devices must be small
Quantization shifts band edges→ tunnel barrier
Band nonparabolicity increases carrier masses
Electrostatics: bands bend in source & channel
What actual on-current might we expect ?
8
Tunneling Probability
Transmissi on Probabilit y (WKB, square barrier)
P  exp( 2Tbarrier ), where  
2m * Ebarrier

Assume : m*  0.06  m0 , Eb  0.2 eV
Then :
P  33% for a 1nm thick barrier
 10% for a 2nm thick barrier
 1% for a 4nm thick barrier
For high Ion, tunnel barrier must be *very* thin.
~3-4nm minimum barrier thickness:
P+ doping, body & dielectric thicknesses
9
T-FET on-currents are low, T-FET logic is slow
NEMO simulation:
1.5
0.4
1
0.3
0.5
0
-0.5
-1
2
10
0.2
0.1
0
3.0%
-0.1
-1.5
5
10
15
20
25
position, nm
Experimental:
InGaAs heterojunction HFET;
drain current, A/m
2
0.5
Energy(eV)
Energy, eV
GaSb/InAs tunnel finFET: 2nm thick body, 1nm thick dielectric @ er=12, 12nm Lg
-0.2
-3
10
-2
-1
10
10
10
Transmission
0
60mV/dec.
1
10
0
10
10
-1
10
-2
10
-3
10
-4
10
-5
10 mA/mm
0
0.1 0.2 0.3 0.4 0.5 0.6
gate-source bias, volts
~15 mA/mm @0.7V
Dewey et al,
2011 IEDM,
2012 VLSI Symp.
Low current
→ slow logic
10
Resonant-enhanced tunnel FET
Avci & Young, (Intel) 2013 IEDM
2nd barrier: bound state
dI/dV peaks as state aligns with source
improved subthreshold swing.
Can we also increase the on-current ?
11
Electron anti-reflection coatings
Tunnel barrier:
transmission coefficient < 100%
reflection coefficient > 0%
want: 100% transmission, zero reflection
familiar problem
Optical coatings
reflection from lens surface
quarter-wave coating, appropriate n
reflections cancel
Microwave impedance-matching
reflection from load
quarter-wave impedance-match
no reflection
Smith chart.
12
T-FET: single-reflector AR coating
drain current, A/m
0.5
Energy(eV)
0.4
0.3
0.2
0.1
0
-0.1
TFET
TFET+ one barrier
-0.2
-3
10
10
2
10
1
10
0
60mV/dec.
-1
10
-2
10
-3
10
-4
10
-5
TFET
+one barrier
10
-2
-1
10
10
10
Transmission
0
0 0.1 0.2 0.3 0.4 0.5
gate-source bias, volts
Peak transmission approaches 100%
Narrow transmission peak; limits on-current
Can we do better ?
13
Limits to impedance-matching bandwidth
Microwave matching:
More sections→ more bandwidth
Is there a limit ?
Transmission, dB
1
1, 2, 3 sections
0
-1
-2
-3
-4
-5
-6
-7
Bode-Fano limits
0
5
10
15
20
Frequency, GHz
R. M. Fano, J. Franklin Inst., Jan. 1960
Bound bandwidth for high transmission   1 



ln
d


example: bound for RC parallel load→  
2 
||

||
RC


Do electron waves have similar limits ? 0
Yes ! Schrödinger's equation is isomorphic to E&M plane wave.
Khondker, Khan, Anwar, JAP, May 1988
T-FET design→ microwave impedance-matching problem
Fano: limits energy range of high transmission
Design T-FETs using Smith chart, optimize using filter theory
Working on this: for now design by random search
*E / h  f ,   V ,   I , probabilit y current  power, where  ( x)  ( / jm*)( / x) 14
T-FET with 3-layer antireflection coating
10
0.25
2
Simulation
2
1
10
0.5
0
drain current, A/m
1
Energy(eV)
Energy, eV
1.5
3-layer
0-layer
0.2
0.15
-0.5
-1
0
10
-1
10
-2
60mV/dec.
triple layer
-3
single layer
-4
P-GaSb/N-InAs
tunnel FET
10
10
10
-1.5
5
10
15 20 25
position, nm
30
35
0.1
-5
10
-3
10
-2
10
-1
10
Transmission
Interim result; still working on design
0
10
0
0.1 0.2 0.3 0.4 0.5
gate-source bias, volts
0.6
15
Source superlattice: truncates thermal distribution
Proposed 1D/nanowire device:
M. Bjoerk et al., U.S. Patent 8,129,763, 2012.
Gnani, 2010 ESSDERC
E. Gnani et al., 2010 ESSDERC
Gnani, 2010 ESSDERC:
simulation
16
Long et al., EDL, Dec. 2014
Planar (vs. nanowire) superlattice steep FET
Planar superlattice FET
superlattice by ALE regrowth
easier to build than nanowire (?)
Performance (simulations):
~100% transmission in miniband.
0.4 mA/mm Ion , 0.1mA/mm Ioff ,0.2V
Ease of fabrication ?
Tolerances in SL growth ?
Effect of scattering ?
simulation
17
What if steep FETs prove not viable ?
Steep FETs will not be easy.
1000
800
60
mV/dec.
100
600
10
400
1
d
I , Amps/meter
1000
200
0.1
0
0
0.1 0.2 0.3 0.4 0.5
0
0.1 0.2 0.3 0.4 0.5
V
gs
V
gs
Instead, increase dI/dV above threshold.
dI/dV: a.k.a. transconductance, gm.
Reduced voltage, reduced CV2
First: III-V MOS as (potential) high-(dI/dV) device
18
Why III-V MOS ?
III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering
→ higher current. Then trade for lower voltage or smaller FETs.
Problems: Low m*→ less charge. Low m* → more S/D tunneling.
Narrow bandgap→ more band-band tunneling, impact ionization.
19
In(Ga)As: low m*→ high velocity → high current (?)
Ballistic on-current:
Natori, Lundstrom, Antoniadis (Rodwell)
 mA   Vgs  Vth 

  
J  K1   84
 mm   1 V 
K1 
1  (c

g  m mo
1
normalized drive current K
,
1
cequiv


Tox
e ox
Tchannel
2e semiconductor

3/ 2
In(Ga)As thin {100} Si
0.3

g  # valleys
1/ 2
*
dos,o / cequiv )  g  ( m / mo )
0.35
More current
unless dielectric,
and body,
are extremely thin.
*
3/ 2
g=2
g=1
0.25
0.2
0.15
0.4 nm
0.1
0.6 nm
0.05
EET=T e
0
0.01
/e +T
ox SiO2
ox
e
/2e
channel SiO2
0.1
m*/m
EET=1.0 nm
channel
1
o
20
-2
10
Dot : Reverse Sweep
Solid: Forward Sweep
Lg = 1 mm
10
1
10
0
10
-1
10
-2
10
-3
-3
10
-4
10
-5
10
-6
10
-7
10
-8
SSmin~ 61 mV/dec.
(at V
DS
= 0.1 V)
SSmin ~ 63 mV/dec. 10-4
(at V
= 0.5 V)
10
10
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DS
-5
2
Current Density (mA/mm)
-1
10
|Gate Leakage| (A/cm )
Excellent III-V gate dielectrics
2.5nm ZrO2
1nm Al2O3
2.5nm InAs
V. Chobpattanna,
S. Stemmer
FET data: S Lee, 2014 VLSI Symp.
Gate Bias (V)
61 mV/dec Subthreshold swing at VDS=0.1 V
Negligible hysteresis
21
Record III-V MOS
1
Lg = 25 nm
3.0
10
I
=
500
m
A/
m
m
at
I
=100
nA/
m
m
on
off
0
10 and V =0.5V
2.5
D
-1
10 SS~ 72 mV/dec.
2.0
-2
10 SS~ 77 mV/dec.
-3
1.5
10
-4
10
1.0
-5
10
0.5
-6
10
-7
10 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.50.0
Lg~25 nm
gm (mS/mm)
Current Density (mA/mm)
S. Lee et al., VLSI 2014
N+ S/D
Vertical Spacer
Ion (mA/mm)
Gate Bias (V)
0.50
VDS = 0.5 V
0.45
Ioff=100 nA/mm
0.40
record
for III-V
0.35
0.30
0.25
0.20
0.15
0.10
10
S. Lee, VLSI 2014
J. Lin, IEDM 2013
T. Kim, IEDM 2013
Intel, IEDM 2009
J. Gu, IEDM 2012
D. Kim, IEDM 2012
= best UTB
SOI silicon
100
Gate Length (nm)
22
Double-heterojunction MOS: 60 pA/mm leakage
Lg-30nm
Lg-30nm
C. Y. Huang et al., IEDM 2014
•
•
•
Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm
100:1 smaller Ioff compared to InGaAs spacer
BTBT leakage suppressedisolation leakage dominates
23
III-V MOS
@ Lg = ???
Huang et al.,
this conference
Courtesy of
S. Kraemer (UCSB)
24
High-current III-V PMOS
Silicon PMOS: Wang et al., IEEE TED 2006 (Intel)
III-V: S. Mehrotra (Purdue), unpublished
nm thickness [110]-oriented PMOS channels→ low transport mass
simulation
Very low m*
Current approaching NMOS
finFETs are naturally [110]
25
Minimum Dielectric Thickness & Gate Leakage
Thin dielectrics are leaky
Transmissi on Probabilit y P  exp( 2Tbarrier ), where    1 2m * Ebarrier
High-er materials have lower barriers
eV from vacuum level
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
E
c
Si
E
v
InGaAs HfO
2
e ~20
r
TiO
2
e ~40
r
-6
normalized drive current K
→ 0.5-0.7nm minimum EOT
constrains on-current
electrostatics degrades with scaling
→ fins, nanowires
1
0.35
g=2
g=1
0.3
0.25
0.2
0.15
0.4 nm
0.1
0.6 nm
0.05
EET=T e /e +T
e /2e
ox SiO2 ox
channel SiO2
channel
0
0.01
0.1
m*/m
o
EET=1.0 nm
1
26
Quick check: scaling limits
NEMO ballistic simulations
finFET: 5 nm physical gate length.
Channel: <100> Si, 0.5, 1, or 2nm thick dielectric: er=12.7, 0.5 or 0.7 nm EOT
Dielectric: 0.5 nm EOT
Dielectric: 0.7nm EOT
subthreshold swing, mV/decade
80
5nm gate length
<100> Si finFET
75
thermionic+
tunneling
thermionic+
tunneling
70
thermionic
only
65
thermionic
only
simulation
60
0
0.5
1
1.5
2
body thickness, nm
2.5 0
0.5
1
1.5
2
body thickness, nm
2.5
Given EOT limits, ~1.5-2nm body is acceptable.
Source-drain tunneling often dominates leakage.
27
Do 2-D semiconductors help ?
 mA   Vgs  Vth 

  
J  K   84
 mm   1 V 
where K 
1  (c
3/ 2
,
g  (m1/ 2 / mo1/ 2 )
1/ 2 1/ 2
dos,o / cequiv )  g  ( m m || / mo ) 
3/ 2
normalized drive current K
Silicon
0.2
0.15
0.4 nm
0.1
0.6 nm
0.05
EET=1.0 nm
0.1
m*/m
1
o
normalized drive current, K
1
0.4 nm
0.25
g=6
isotropic
0.6 nm
0.3
EET=1.0 nm
0.2
0.15
0.1
0.05
0
0.01
0.1
normalized effective mass m*/m
1
o
1
0.35
normalized drive current, K
Ballistic drive currents don't win either
high m*, and/or high DOS
mobility sufficient for ballistic ?
0.25
0.35
MoS2
If oxides won't scale, we must make fins
with 2D, can we make fins ?
later, will need to make nanowires...
g=2
isotropic
0.3
0
0.01
Phosphorene
3D: Is body thickness a scaling limit ?
recall the previous slide
1
0.35
0.3
0.25
EET=1.0 nm
0.4 nm
0.6 nm
g=1
transverse mass
=2.6*m
o
0.2
0.15
0.1
0.05
EET=T e /e +T
e /2e
ox SiO2 ox
channel SiO2
channel
0
0.01
0.1
normalized longitudinal transport mass m /m
L
1
o
28
When it gets crowded, build vertically
Los Angeles: sprawl
2-D integration:
wire length # gates1/2
Manhattan: dense
3-D integration:
wire length #gates1/3
LA is interconnect-limited
1) Chip stacking (skip)
2) 3D transistor integration
29
Corrugated surface→ more surface per die area
30
Corrugated surface→ more current per unit area
Cohen-Elias et al.,
UCSB
2013 DRC
J .J. Gu et al., 2012 DRC,
Purdue
2012 IEDM
31
3D→shorter wires→less capacitance→less CV2
All three have same drive current, same gate width
Tall fin, "4-D": smaller footprint→ shorter wires
32
10
10
1
0
-1
0
0.1
0.2 0.3
V
gs
0.4
0.5
4
10
3
10
2
10
1
10
0
10
-1
0
0.1
0.2 0.3
V
gs
0.4
0.5
d
10
10
I , Amps per meter of FET footprint width
10
2
60
mV/decade
d
3
I , Amps per meter of FET footprint width
10
d
I , Amps per meter of FET footprint width
Corrugation: same current, less voltage, less CV2
10
4
10
3
10
2
10
1
10
0
10
10:1
corrugation
-1
0
0.1
0.2 0.3
V
gs
0.4
0.5
33
Industry is moving to taller fins.
http://techreport.com/review/26896/intel-broadwell-processor-revealed
34
Fixing source-drain tunneling by increasing mass ?
Source-drain tunneling leakage:
I off  exp( 2Lg ), where    1 2m * (qVth )
Fix by increasing effective mass ?
Lg  constant  m*  1 / L2g
This will decrease the on-current:
(also increases transit time)
normalized drive current K
1
0.35
g=2
g=1
0.3
long gate→ big
0.25
0.2
0.15
0.4 nm
0.1
0.6 nm
0.05
EET=T e
0
0.01
/e +T
ox SiO2
ox
e
/2e
channel SiO2
0.1
m*/m
?
!
EET=1.0 nm
shorter gate→ smaller
less current
wider→ more current
big again !
channel
1
o
35
Fixing source-drain tunneling by corrugation
Transport distance > gate footprint length
Only small capacitance increase
36
RF/Wireless
37
mm-Waves: high-capacity mobile communications
wide, useful bandwidths from 60 to ~300 GHz
Needs→ research:
RF front end: phased array ICs, high-power transmitters, low-noise receivers
IF/baseband: ICs for multi-beam beamforming, for ISI/multipath suppression, ...
38
mm-Wave CMOS won't scale much further
Gate dielectric can't be thinned
→ on-current, gm can't increase
Shorter gates give no less capacitance
dominated by ends; ~1fF/mm total
normalized drive current K
1
0.35
0.3
g=1
0.25
0.2
0.3 nm
0.15
0.4 nm
0.1
0.6 nm
0.05
EET=T e
0
0.01
/e +T
ox SiO2
ox
e
/2e
channel SiO2
0.1
m*/m
EET=1.0 nm
channel
1
o
Maximum gm, minimum C→ upper limit on ft.
about 350-400 GHz.
Tungsten via resistances reduce the gain
Inac et al, CSICS 2011
Present finFETs have yet larger end capacitances
39
III-V high-power transmitters, low-noise receivers
Cell phones & WiFi:
GaAs PAs, LNAs
mm-wave links need
high transmit power,
low receiver noise
0.47 W @86GHz
H Park, UCSB, IMS 2014
0.18 W @220GHz
T Reed, UCSB, CSICS 2013
1.9mW @585GHz
M Seo, TSC, IMS 2013
40
Making faster bipolar transistors
to double the bandwidth:
change
emitter & collector junction widths
decrease 4:1
current density (mA/mm2)
increase 4:1
current density (mA/mm)
constant
collector depletion thickness
decrease 2:1
base thickness
decrease 1.4:1
emitter & base contact resistivities
decrease 4:1
Teledyne: M. Urteaga et al: 2011 DRC
Narrow junctions.
Thin layers
High current density
Ultra low resistivity contacts
41
THz HBTs: The key challenges
Obtaining good base contacts
RC parasitics along finger length
in full HBT process flow
(vs. in TLM structure)
metal resistance, excess junction areas
-5
10
P-InGaAs
Contact Resistivity, cm
2
-6
10
-7
10
-8
10
3THz target
B=0.8 eV
-9
10
0.6 eV
0.4 eV
0.2 eV
step-barrier
Landauer
-10
10
18
19
20
21
10
10
10
10
-3
Hole Concentration, cm
Baraskar et al, Journal of Applied Physics, 2013
42
THz InP HBTs
blanket Pt/Ru base contacts:
resist-free, cleaner surface
→ lower resistivity
J. Rode, in review
43
THz HEMTs: one more scaling generation ?
First Demonstration of Amplification at 1 THz Using 25nm InP High Electron Mobility Transistor Process
Xiaobing Mei, et al, IEEE EDL, April 2015 doi: 10.1109/LED.2015.2407193
44
nm & THz electronics
45
Electron devices: What's next ?
Problems:
oxide, S/D tunneling
lithography
interconnect energy
~ l/n
deep UV
absorption
Why transistors are best:
our best
tools are:
..electrostatic
control of charge
& static dissipation
...and communicating
by E&M waves
http://en.wikipedia.org/wiki/Standard_Model
Opportunities:
low voltages
high currents
nm via 3D
RF→ THz
46
(backup slides follow)
47