Chapter 6
Delay Testing
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 1
What is this chapter about?
Introduce delay test concepts, models, and
test generation
 Provide overview of common delay test
approaches


Focus on




Delay test application
Delay fault models
Test generation
High quality delay tests
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 2
Introduction to Delay Testing
Introduction
 Delay Testing Approaches
 Circuit and Delay Models
 Delay Test Application
 Transition Fault Test
 Path Delay Test
 Constrained Delay Test
 Conclusions

EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 3
Introduction
 Goal
of Delay Testing
 Primary: Verify circuit timing (e.g. clock
frequency) over supply voltage and
temperature range
 Secondary: Identify marginal circuits that
meet specifications
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 4
Delay Testing Approaches (1)

Random
 Apply random patterns at rated clock speed
 Advantages
– Can generate patterns on-chip (BIST)
– Applied as in normal operation
– Fortuitous detection of unmodeled faults
 Disadvantages
– Poor coverage of long paths
– Higher than normal circuit activity (power, noise)
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 5
Delay Testing Approaches (2)

Functional
 Apply functional patterns at rated clock speed
 Advantages
– Most accurate test
– Chip operating in normal mode
– Fortuitous detection of unmodeled faults
 Disadvantages
– Poor coverage, coverage difficult to compute
– High test pattern development cost
– High test application cost without large on-chip
cache/memory
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 6
Delay Testing Approaches (3)

Structural
 Use delay fault models and circuit structure to
generate tests
 Advantages
– Automatic test pattern generation
– High fault coverage
– Easier diagnosis
 Disadvantages
– Simplifying assumptions in delay fault model
– Design for testability (DFT) required for high coverage
– Test application very different than normal operation
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 7
…
x1
x2
…
Huffman Sequential Circuit Model
xn
z1
z2
zm
Yl
…
yl
…
Y1
Y2
Flip-Flops
y1
y2
…
…
Combinational
Logic
Primary Inputs (PI)
x1, x2,…
 Primary Outputs
(PO) z1, z2,…
 Pseudo Primary
Inputs (PPI) y1, y2,…
 Pseudo Primary
Outputs (PPO) Y1,
Y2,…

clock
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 8
Design Assumptions

Structural delay test of synchronous
sequential digital circuits
 Delay test of the logic circuits
– Gate level primitives, including latches and flip-flops
 Most flip-flops and latches are scanned
 Embedded memory modeled as black boxes
– Test them separately

Same assumptions used in most commercial
ATPG tools
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 9
Circuit Delay Models (1)
Some delay fault models need circuit delays
 Gate delay

 Delay from gate input to output
 Can have different delays for rising or falling
transitions, different inputs to outputs
 Interconnect delay lumped with gate

Gate transport delay
 Gate delay without interconnect delay

Interconnect propagation delay
 Separate delay to each net fanout (gate input)
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 10
Circuit Delay Models (2)
 Inertial
delay
 Minimum pulse width that propagates
through a gate
 Used to analyze glitch generation and
propagation
 Min-max
delay
 Abstraction of process variation
 Gate and interconnect delay correlations
usually not available
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 11
Delay Test Application (1)
Launch transitions into circuit from PIs and
PPIs (referred to collectively as PIs)
 Capture circuit response at POs and PPOs
(collectively POs) at specified time
 Compare results with correct response
 Two-pattern test

 Required to launch transitions
 First (initialization) vector initializes circuit
 Second (test) vector launches transitions
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 12
Delay Test Application (2)

How to hold two test vectors in scan chains?
 Enhanced scan – holding latch on output of flipflop
– Scan first vector in, transfer to holding latches, scan
second vector in, enable on latches launches transitions
– Expensive in area and delay, so uncommon
 Launch-on-shift (LOS) – also known as skewed
load, launch-off-shift
 Launch-on-capture (LOC) – also known as
broadside test, launch-off-capture
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 13
Transition Fault Model

Assumes a large/gross delay is present at a circuit
node
 Slow-to-rise (STR), slow-to-fall (STF)


Irrespective of which path the effect is propagated,
the gross delay defect will be late arriving at an
observable point
Most commonly used in industry
 Simple and number of faults linear to circuit size
 Also needs 2 vectors to test

Node x slow-to-rise (x-STR) can be modeled simply
as two stuck-at faults
 First time-frame: x/1 needs to be excited
 Second time-frame: x/0 needs to be excited and propagated
EE141
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Ch. 6 - Delay Testing – P. 14
Launch-on-Shift Approach
Last scan-in
shift cycle
Scan
enable
Launch cycle
Capture cycle
1 Scan-in
0
A
B
EE141
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1
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 15
Launch-on-Shift Approach
Last scan-in
shift cycle
Scan
enable
Launch cycle
Capture cycle
1
A
B
EE141
System-on-Chip
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0
1
Combinational
Circuit
Ch. 6 - Delay Testing – P. 16
Launch-on-Shift Approach
Last scan-in
shift cycle
Scan
enable
Launch cycle
Capture cycle
Scan-in
A
B
EE141
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1
0
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 17
Launch-on-Shift Approach
Last scan-in
shift cycle
Scan
enable
Launch cycle
Capture cycle
Scan-in
A
B
EE141
System-on-Chip
Test Architectures
1
0
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 18
Launch-on-Capture Approach
Last scan-in
shift cycle
Scan
enable
Dummy cycle
Launch Capture
Scan-in
A
B
EE141
System-on-Chip
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0
1
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 19
Launch-on-Capture Approach
Last scan-in
shift cycle
Scan
enable
Dummy cycle Launch Capture
Scan-in
A
B
EE141
System-on-Chip
Test Architectures
0
1
Scan-out
0
Combinational
Circuit
0
Ch. 6 - Delay Testing – P. 20
Launch-on-Capture Approach
Last scan-in
shift cycle
Scan
enable 0
0
Dummy cycle Launch Capture
Scan-in
A
B
EE141
System-on-Chip
Test Architectures
0
1
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 21
Launch-on-Capture Approach
Last scan-in
shift cycle
Scan
enable
Dummy cycle
Launch Capture
Scan-in
A
B
EE141
System-on-Chip
Test Architectures
0
0
Scan-out
Combinational
Circuit
Ch. 6 - Delay Testing – P. 22
Launch-on-Shift Implication
Scan-in
1X
A
Combinational
Circuit
B
C
Scan-out
EE141
System-on-Chip
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X0
Ch. 6 - Delay Testing – P. 23
Launch-on-Capture Implication
Scan-in
A
Combinational
Circuit
1X
B
C
Scan-out
EE141
System-on-Chip
Test Architectures
X0
Ch. 6 - Delay Testing – P. 24
Test Robustness
 Robust
test
 Detects delay fault independent of circuit
delays
 Nonrobust
test
 Detection depends on circuit delays
 Functionally
sensitizable test
 Detection depends on delays on multiple
paths
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 25
Robustness Examples
Robust
Nonrobust
0
Functionally Sensitizable
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 26
Transition Fault Test Example
0 0 x1
0 1 x2
3
t=7
t=0
v2 v1
2
2
1 1 x3
EE141
System-on-Chip
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y
t=2
3
Ch. 6 - Delay Testing – P. 27
Transition Fault Properties
A transition fault may be launched robustly,
non-robustly, or neither
 Example: STR at output of OR gate

EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 28
Transition Fault Properties (cont.)
A
transition fault may be propagated
robustly, non-robustly, or neither
 Example: STF at output of gate a
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 29
Untestable Transition Fault
 STF
on signal d is untestable under
Launch on Shift
 Second vector needs to be abc=000
 First vector must then be abc=00X
a
d
b
c
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 30
Path Length Comparison (Robust)
Path Length
s15850
70
60
50
40
30
20
10
0
0
Combinational
EE141
System-on-Chip
Test Architectures
10000
20000
Fault
Launch-on-Capture
30000
Launch-on-Shift
Ch. 6 - Delay Testing – P. 31
Transition Fault Testing with Stuck-At
ATPG
 Simply
treat each transition fault as two
stuck-at faults
 Node x slow-to-rise (x-STR) can be
modeled simply as two stuck-at faults
 First time-frame: x/1 needs to be excited
 Second time-frame: x/0 needs to be excited and
propagated
 Use x/0 and x/1 for x-STF
 Apply
LOC or LOS constraints in ATPG
as needed
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 32
Path Delay Testing

Path Delay Fault
 Delay distributed along path
– Could be combination of slow process and spot defects
 Classic model
– Any path could have any delay
– Must test all paths
– But infeasibly large number of paths – exponential in
circuit size
 KLPG – K Longest Paths Per Gate
– Test K longest paths through each line, with both rising
and falling transition on the line
– Linear in circuit size
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 35
Test Generation Algorithm
Search space
Scan
cells
Scan
cells
Constraints from
outside search space
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 36
Path Generation Flow
Start
Extend the partial path with
longest potential delay
Insert into the
partial path store
Apply side inputs and
perform direct implications
Apply heuristics to
avoid false paths
N
Y
Conflict?
N
Complete path?
Y
End
EE141
System-on-Chip
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Final justification
Ch. 6 - Delay Testing – P. 37
Direct Implication
 Detect
local conflicts
 Most conflicts are local
Conflict
0
1
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 38
Heuristic – Forward Trimming
 Trim
non-solution space immediately
 Path
generation is guided to find a true
path
 Large saving if many paths in the logic block
gi
1
EE141
System-on-Chip
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Logic
Block
gj
1
0
Ch. 6 - Delay Testing – P. 39
Other Heuristics
 Smart
PERT
 Computes the upper bound of longest
testable path more accurately
 Relations
between gates and global
longest path generation
 A long path through a gate may be one of
the K longest paths through another gate
 Reduce repeated work
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 40
7-Value Algebra for Partial Scan
AND
0
1
x
u
0/u
1/u
x/u
0
0
0
0
0
0
0
0
1
0
1
x
u
0/u
1/u
u
x
u 0/u 1/u x/u
0
0
0
0
0
x
u 0/u 1/u u
x 0/u 0/u x/u x/u
0/u u 0/u u 0/u
0/u 0/u 0/u 0/u 0/u
x/u u 0/u 1/u x/u
x/u 0/u 0/u x/u x/u
x – Unknown u – Uncontrollable
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 41
7-Value Algebra for Partial Scan
AND
0
1
x
u
0/u
1/u
x/u
0
0
0
0
0
0
0
0
1
0
1
x
u
0/u
1/u
u
x
u 0/u 1/u x/u
0
0
0
0
0
x
u 0/u 1/u u
x 0/u 0/u x/u x/u
0/u u 0/u u 0/u
0/u 0/u 0/u 0/u 0/u
x/u u 0/u 1/u x/u
x/u 0/u 0/u x/u x/u
x – Unknown u – Uncontrollable
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 42
Application of 7-Value Algebra
M1
u
n1
g1
n3
0/u
x
M2
n2
EE141
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x
n4
g2
0/u
n5
Ch. 6 - Delay Testing – P. 43
Application of 7-Value Algebra
M1
u
n1
g1
n3
0/u
x
M2
n2
EE141
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Test Architectures
x
n4
g2
0/u
n5
Ch. 6 - Delay Testing – P. 44
Final Justification
 Detect
global conflicts which cannot be
detected by direct implication
 Find the vector pair which sensitizes the
path
 PODEM/FAN based justification algorithm
1
EE141
System-on-Chip
Test Architectures
1
1
1
Ch. 6 - Delay Testing – P. 45
KLPG-1 Test Set Construction
Non-robust
test
Robust test
Long
transition
fault test
A long transition fault test tests longer paths than
a regular transition fault test
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 46
Pseudo-Functional Testing
 Avoids
over-testing by scanning in nonfunctional states
 Does not induce excessive circuit switching
 Does not exercise functionally infeasible
paths
– a timing failure due to a functionally infeasible
path may not be a true failure and will result in
throwing good parts away
 Avoid Yield loss
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 47
Constrained ATPG


To avoid scanning in functionally unreachable states,
constraints can be used
Let (¬x + y) represent a constraint
 then abcd={1000, 0100, 1100, 1001, 0101, 1101, 1010,
0110, 1110} are the illegal states
a
x
b
c
y
d
EE141
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Ch. 6 - Delay Testing – P. 48
Pair-wise Constraints



Compute constraints via logic implications
Implications for g=0 and g=1 over the time window -t
to t (t is user-specified) are first computed and stored
Apply transitive law to identify those implications in
the 0th time frame
 a implies b (next time-frame), b implies c (previous
time-frame), then a implies c (same time-frame)
 Remove all combinational implications
 Resulting
set are functional constraints
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 49
Multi-Literal Constraints


[A=1] Λ [B=1]  [F=0] in the next time-frame.
Key: identify x  A (prev time frame) and y  B
(prev time frame), then we have (x Λ y)  [F=0] in
the same time-frame
EE141
System-on-Chip
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Ch. 6 - Delay Testing – P. 50
Constrained ATPG
 Given
a set of computed constraints, U
 ATPG must not violate any constraint in
U during the search
 Key: want U to be as comprehensive as
possible
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 51
Alternative Approach to PseudoFunctional Testing
 Run
ATPG without any constraints
 Map each generated pattern to a known
valid state
 Must make sure the modification still
detects the target fault
 May need to try mapping to different valid
states
EE141
System-on-Chip
Test Architectures
Ch. 6 - Delay Testing – P. 52