KULLIYYAH OF ENGINEERING
END-OF-SEMESTER EXAMINATION
SEMESTER 2, 2014/2015 SESSION
Programme
: Engineering
Level of Study
: UG 1
Time
: 9:00 am- 12:00 pm
Date
: 24/05/2015
Duration
: 3 Hrs
Course Code
: ECE 1312
Section(s)
: 1-9
Course Title
: Electronics
This Question Paper Consists of 9 (Nine) Printed Pages (Including Cover Page)
with 5 (Five) Questions.
INSTRUCTION(S) TO CANDIDATES
DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO
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Total mark of this examination is 100.
This examination is worth 50 % of the total course assessment.
Answer ALL QUESTIONS
Only approved calculator with ‘KoE approved’ sticker is allowed (non-programmable and nongraphical).
Marks assigned to each problem are listed in the margins.
Any form of cheating or attempt to cheat is a serious offence which may lead to dismissal.
All electronics gadgets are prohibited in the exam hall / venue.
(e.g. mobile / smart phones, smart watches, and smart glasses)
1
QUESTION 1 (20 marks)
a)
Design a Lithium battery charger using a half-wave rectifier circuit as shown in Fig. 1(a), so
that the peak diode current is 250 mA. Consider the diode piecewise linear model with diode cutin voltage 𝑉𝛾 = 0.65 V and diode forward resistance 𝑟𝑓 = 15 𝛺.
b)
(Hint: determine the transformer turns ratio).
(6 marks)
Calculate the diode reverse biased voltage.
(2 marks)
Fig. 1(a)
c)
A simple diode circuit is shown in Fig.1(c). If the currents through the diode and resistor R2 are
equal, that is ID = IR2. Assume that the diode cut-in voltage, 𝑉𝛾 = 0.7 V. Determine the values of
the followings:
i.
Resistor R2
(3 marks)
ii.
Output voltage VO
(3 marks)
Fig. 1(c)
2
d)
A solar cell is a special type of pn-junction diode. The current equation of a particular solar cell is
represented as follows:
−13
𝐼𝐷 = 5.0 × 10
[𝑒
𝑉
( 𝐷)
𝑉𝑇
− 1] − 7.7 × 10−2 (A)
When the cell is irradiated in the sunlight and the cell current 𝐼𝐷 = 0, the voltage 𝑉𝐷 at that time
of the solar cell is called the open circuit voltage 𝑉𝑂𝐶 . Similarly, when the cell is irradiated in the
sunlight and the cell voltage 𝑉𝐷 = 0, the current 𝐼𝐷 at that time of the solar cell is called the short
circuit current 𝐼𝑆𝐶 . If the cell is operating in the room temperature determine the parameters of the
solar cell as follows:
i.
Open circuit voltage 𝑉𝑂𝐶
(4 marks)
ii.
Short circuit current 𝐼𝑆𝐶
(2 marks)
QUESTION 2 (20 marks)
a)
The 𝑉𝐶 − 𝐼𝐶 characteristics curves and load line of a transistor amplifier are shown in
Fig. 2(a). Assume that the transistor is operating at the room temperature and the collector reverse
saturation current of the transistor 𝐼𝑆 = 7.2 × 10−9 mA.
i.
Find the quiescent current 𝐼𝐶𝑄
(5 marks)
ii.
Determine the Early voltage 𝑉𝐴
(5 marks)
𝑉𝐵𝐸
[ Hint: 𝐼𝐶 = 𝐼𝑆 (𝑒 𝑉𝑇 − 1) (1 +
𝑉𝐶𝐸
𝑉𝐴
)]
Fig. 2(a)
3
b)
A common-emitter amplifier circuit and its voltage transfer characteristic curve are shown in
Fig. 2(b). Determine the minimum input voltage 𝑉𝐼 at point “X ” as shown in the figure, so that
the transistor goes to 𝑉𝐶𝐸 (sat). Assume that the transistor common emitter current gain β = 150
and then 𝑉𝐵𝐸 (on) = 0.7 V.
(5 marks)
Fig. 2(b)
c)
A common-emitter amplifier with base to the collector biasing circuit is shown in Fig. 2(c).
Assume that the transistor is working in the room temperature and its common emitter current
gain β = 35 and the base to emitter voltage 𝑉𝐵𝐸 (on) = 0.7 V respectively. Determine the
operating point (quiescent point) current 𝐼𝐵𝑄 , 𝐼𝐶𝑄 and 𝑉𝐶𝐸𝑄 .
Fig. 2(c)
4
(5 marks)
QUESTION 3 (20 marks)
a)
Draw a circuit diagram for common-collector BJT amplifier circuit. The circuit uses an npn
transistor with a single DC source and voltage divider DC biasing configuration.
b)
(2 marks)
A transistor amplifier is designed to have 𝑔𝑚 = 95mΩ−1 . If transistor parameters are 𝛽 =
125 and 𝑉𝐴 = 200 V.
c)
i.
Find the required collector current
(1 Marks)
ii.
Determine 𝑟𝜋 and 𝑟𝑂
(2 Marks)
The transistor parameters for the circuit shown in Fig. 3(c) are 𝛽 = 120, 𝑉𝐵𝐸 (on) = 0.7 V and
𝑉𝐴 = 80 V.
i.
Find the quiescent values 𝐼𝐵𝑄 , 𝐼𝐶𝑄 , 𝐼𝐸𝑄 and 𝑉𝐶𝐸𝑄
(4 marks)
ii.
Find the small-signal parameters 𝑔𝑚 , 𝑟𝜋 and 𝑟𝑂
(3 marks)
iii.
Draw the small-signal equivalent circuit.
(2 marks)
iv.
Determine the amplifier small-signal voltage gain 𝐴𝑣
(2 marks)
v.
Determine the amplifier input resistor 𝑅𝑖
(2 marks)
vi.
Determine the amplifier output resistor 𝑅𝑜
(2 marks)
Fig. 3(c)
5
QUESTION 4 (20 marks)
a)
Write four differences between BJT and MOSFET. Sketch a cross section of an n-channel
MOSFET and label the terminals.
b)
(4 marks)
The transistor in the circuit shown in Fig. 4(b) has parameters VTN = 0.25 V and Kn = 0.03
mA/V2. The circuit is biased at VDD = 10 V. Assume that R1 + R2 = 500 k. Design the circuit
such that ID = 0.4 mA and VDS = 6 V. Confirm that the transistor is in saturation mode.
(9 marks)
Fig. 4(b)
c)
The parameters of an n-channel MOSFET are: VTN = 0.6 V, k’n = 0.1 mA/V2 and  = 0.015 V-1.
The transistor is biased in the saturation region with ID = 1.2 mA.
i.
Find the width-to-length (W/L) ratio of the transistor such that the
transconductance, gm = 2.5 mA/V.
( 3 marks)
ii.
Calculate the small signal output resistance, ro
( 2 marks)
iii.
Calculate the value of VGS
( 2 marks)
6
QUESTION 5 (20 marks)
a)
Fig. 5(a) is showing a common-source amplifier circuit and its DC output load line. The transistor
parameters are VTN = 0.8 V, Kn = 0.20 mA/V2 and  = 0. Assume that VDD = 5 V and
RTH = 200 k. Answer the following questions.
Fig 5(a)
i. Calculate the value of ID (assume the transistor is in saturation) and the values
of RD and gm
b)
(4 marks)
ii. Draw the small signal equivalent circuit
(3 marks)
iii. Determine the value of the voltage gain AV
(3 marks)
An ideal Op-amp is shown in Fig. 5(b). Determine the values of the followings :
i. vO, i1, i2, iL and iO
(5 marks)
ii. voltage gain Av
(3 marks)
Fig. 5(b)
7
c)
Evaluate the output voltage vo of the circuit as shown in Fig. 5(c).
Fig. 5(c)
8
(2 marks)
Useful equations for MOSFET:
I D  Kn [2VGS  VTN VDS  VDS ]
2
I D  K n VGS  VTN 
2
𝐾𝑛′
𝐾𝑛 =
2
∙
𝑊
𝐿
VA
I CQ
ro 
VA 
1

g m  2 K n I DQ
Useful equations for BJT:
gm 
r 
I CQ
ro 
VT
 VT
VA
I CQ
I CQ
g m r  
Useful equation for pn- junction:
I D  I s (e
vD
VT
 1)
END OF PAPER
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