Fig. 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10
m, W = 2 to 500 m, and the thickness of the oxide layer is in the range of 0.02 to 0.1 m.
Fig. 5.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the
substrate beneath the gate.
Fig. 5.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined
by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the
depletion region is not shown (for simplicity).
Fig. 5.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape and its
resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt.
Fig. 5.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt.
Fig. 5.8 Derivation of the iD - vDS characteristic of the NMOS transistor.
Fig. 5.9 Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an
n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.
Fig. 5.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow
indicated. (b) The iD - vDS characteristics for a device with Vt = 1 V and k’n(W/L) = 0.5 mA/V2.
Fig. 5.12 The iD - vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V and k’n(W/L) = 0.5 mA/V2).
Fig. 5.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the
effective channel length (by L).
Fig. 5.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA is typically in the range of 30 to 200 V.
Fig. 5.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The
output resistance models the linear dependence of iD on vDS and is given by ro  VA/ID.
Fig. 5.21 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = -4 V and k’n(W/L) = 2 mA/V2: (a)
transistor with current and voltage polarities indicated; (b) the iD - vDS characteristics; (c) the iD - vGS characteristic in saturation.
Fig. 5.31 Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
Fig. 5.32 Small-signal operation of the enhancement MOSFET amplifier.
Fig. 5.33 Total instantaneous voltages vGS and vD for the circuit in Fig. 5.31.
Fig. 5.34 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (channel-length modulation
effect); and (b) including the effect of channel-length modulation modeled by output resistance ro = |VA|/ID.
Fig. 5.37 the T model of the MOSFET augmented with the drain-to-source resistance ro.
Fig. 5.41 Basic MOSFET current mirror.
Fig. 5.42 Output characteristic of the current source in Fig. 5.40 and the current mirror of Fig. 5.41 for the case Q2 is matched to Q1.
Fig. 5.45 The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q2; (c) graphical construction to
determine the transfer characteristic; and transfer characteristic.
Fig. 5.47 The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit
in (b).
Fig. 5.48 The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.
Fig. 5.52 (a) NMOS amplifier with enhancement load; (b) graphical determination of the transfer characteristic; (c) transfer
characteristic.
Fig. 5.53 The NMOS amplifier with depletion load: (a) circuit; (b) graphical construction to determine the transfer characteristic; and
(c) transfer characteristic.
Fig. 5.54 Small-signal equivalent circuit of the depletion-load amplifier of Fig. 5.43 (a), incorporating the body effect of Q2.
Fig. 5.55 (a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
Fig. 5.56 Operation of the CMOS inverter when v1 is high: (a) circuit with v1 = VDD (logic-1 level, or VOH); (b) graphical construction
to determine the operating point; and (c) equivalent circuit.
Fig. 5.57 Operation of the CMOS inverter when v1 is low: (a) circuit with v1 = 0V (logic-0 level, or VOL); (b) graphical construction to
determine the operating point; and (c) equivalent circuit.
Fig. 5.58 The voltage transfer characteristic of the CMOS inverter.
Fig. 5.59 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the
operating point as the input goes high and C discharges through the QN; (d) equivalent circuit during the capacitor discharge.
Fig. 5.64 The CMOS transmission gate.
Fig. 5.65 Equivalent circuits for visualizing the operation of the transmission gate in the closed (on) position: (a) vA is positive; (b) vA
is negative.
Fig. 5.67 (a) High-frequency equivalent circuit model for the MOSFET; (b) the equivalent circuit for the case the source is connected
to the substrate (body); (c) the equivalent circuit model of (b) with Cdb neglected (to simplify analysis).
Fig. 5.68 Determining the short-circuit current gain Io/Ii.