Simulation for Power Integrity to Design a PCB for
an Optimum Cost
Raul FIZESAN, Dan PITICA
Applied Electronic Department
UTCN
Cluj-Napoca, Romania
raul.fizesan@ael.utcluj.ro
Abstract — One of the biggest design challenges today is to
properly design, manufacture, simulate and validate a Power
Distribution Network (PDN) in systems with increasing speed,
power dissipation and density. PDN are typically comprised of
capacitors networks that have several types of capacitors and
values to obtain target impedance over the required frequency
range for the power/ground planes on PCBs. Capacitors provide
a temporary source of localized energy for instantaneous current
demands from an IC, and a low-impedance return path for high
frequency noise. This paper propose a simulation test for a 4
layer PCB, with power/ground planes, to evaluate the
effectiveness and importance of decoupling capacitors, using tools
and methodologies to determine the important factors like
performance, cost and board area.
Keywords: decoupling capacitors, power distribution network,
power integrity, power and ground planes, target impedance.
I.
target impedance is attained the best compromise between cost,
reliability, performance and PCB area. As was presented in [4],
the target impedance will be met according with three
important design principles:
1. Use power and ground planes on wadjacent layers,
with as thins dielectric as possible, and bring them as close to
the surface of the board stack-up as possible.
2. Use short and wide as possible surface trace between
the decoupling capacitor pads and the via to the buried power
and ground planes cavity and place the decoupling capacitors
where they will have the lowest loop inductance.
3. Use SPICE to help select the optimum number of
capacitors and their values to bring the impedance profile
below the target impedance.
INTRODUCTION
Printed Circuit Board (PCB) power/ground reference plane
decoupling analysis has been a source of confusion and
controversy for many years. The effect of local decoupling
capacitors, their distance from their respective ICs, and the
value of these decoupling capacitors are often debated by
engineers in industry and academia.
In this paper, will be discussed a method for power
integrity analysis in a high speed PCB with power and ground
planes.
Power integrity becomes a big issue and will be inevitably
more and more important; it’s becoming a critical issue in
chips, packages and PCB design. Power fluctuation affects
delay budget in chip and produce noise on board. Lower
voltage, power and ground planes, poor stack up design, miss
used decoupling capacitors and simultaneous switching noise
(SSN), all lead to power integrity problems [1][2][4].
This paper will show the effects of decoupling capacitors
on the frequency-domain impedance.
II.
TARGET IMPEDANCE AND DECOUPLING CAPACITORS
It is possible for customer code to cause repeating current
transients at virtually any frequency from DC up to several
GHz, therefore the PDN should meet target impedance in all
frequency bands of each level of assembly and by meeting this
Figure 1. The target value from DC up to the highest frequency of interest
A power delivery network (PDN) that maintains target
impedance across the entire frequency of interest has sufficient
stored charge to supply power at all frequencies. It is used the
term “target” because it gives an optimum cost and
performance solution for the entire PDN.
To meet this target impedance, the ICs need to be bypassed
using decoupling capacitors. The decoupling capacitors are
placed between power and ground traces to establish low
impedance and to reduce the noise from the PDN [3].
 Ztarget =
(Voltage Supply)∗(Alolowed Ripple%)
current from the chip

Using target impedance for PDN design involves choosing
the number of decoupling capacitors of each value such that the
parallel combination approximates the target impedance, by
dividing the target impedance into the ESR of the capacitor.
The equivalent R, L, and C of n capacitors in parallel are:
 Cn = nC
1
 ESR n = ESR
n
1
 ESLn = ESL
n
Decoupling capacitors with different values connected
between power and ground planes may exhibit resonances
between different capacitors or between capacitors and planes.
If the inductance connecting the parts is minimized, the
resonance peaks are also reduced. Using SMD capacitors, it
can be approached a several hundred pH inductance, but in
some cases, the dimensions of the capacitors and of the PCB do
not allow us to lower it below 100pH, and in some applications
this value is still too high to reduce the resonance peaks. Also,
the ESR of the decoupling capacitors could be used to obtain a
flat frequency impedance response, but the designer is
constrained by the fact that the ESR parameter for today’s
capacitors is not user definable. [1]
III.
minimize cost. Important considerations include capacitance
value, ESR, ESL and mounting inductance.
The cost of the small decoupling capacitor is almost
negligible. Its largest direct cost is in the assembly process and
in the indirect costs of more vias to drill, surface real estate
taken up, potential of blocked routing channels, and impact on
the board layer count.
The most important problem with PDN design is that the
system is built from a network of inductances and capacitances
that attempt to mimic the target impedance. A conductor
always has a parasitic inductance that has a +20dB/decade
slope on a log-log impedance. The capacitance from the
decoupling capacitors and from the planes has a slope of
-20dB/decade, so the resonance occurs when the two slopes
cross. A major objective in choosing decoupling capacitors is
to insure that resonant peaks that exceed the target impedance
are avoided. This is achieved through the use of accurate
frequency domain models for each of the components of the
PDN. For every fraction of a nH reduction in the ESL, fewer
decoupling capacitors need to be used and there is a direct
savings.
IV.
PCB DESCRIPTION
THE EFFECTIVE COST OF A PDN
Much board space in modern computer systems is
dedicated to power distributions components, mostly
decoupling capacitors. There is a cost associated with the
components, assembly process, vias, and the PCB area
occupied by the decoupling capacitors. In the real world of
practical PCB design, we may not have the luxury of using as
many decoupling capacitors as the PDN needs, nor the board
area to place them in proximity to the devices they need to
decouple. It is inconvenient to find problems with PCB when
they are been made like many units and see that a percentage of
them are failing due to excessive ripple.
The moment to find out is as close to the beginning of the
design process as possible, and the solution to determine this is
with a proper methodology, right simulation tools, and proper
capacitors libraries, that allow developing a PDN for the PCB
that guarantee adequate power supply at all frequencies of
operation while reducing the overall cost of the PCB systems.
As was described in the first part of the paper, a very
important principle to follow, in special for cost-effective
design, is to use adequate analysis as early as possible in the
design process. This fact will help reducing the unpleasant
surprises as the design advances and leads to a finite product
that works fine with optimum performance, at an acceptable
cost.
It is important to be aware at the way the target impedance
is met. If the PDN impedance is kept below the target
impedance at every frequency of interest, the worst case,
maximum transient current that travels through will be less
than the wanted ripple. If the impedance is much below the
target impedance, it means that the PDN was overdesigned and
as result, costs more than it needs to. [1] It is important to get
the most benefit out of each mounted capacitor in order to
Figure 2. Top and bottom view of the 4 layer PCB analyzed.
The PCB analyzed for this paper was chosen to be 350mm
x 100mm. At this size, any resonance will be easily seen below
a frequency of 1GHz (Figure 2). Additionally, surface mount
capacitors (0805) were positioned at every power pin of the ICs
to analyze the effect of the typical scheme using 100nF
capacitors to decouple every IC. Figure 3 shows the PCB with
these decoupling capacitors positioned at every power pin of
the ICs as much close as possible. In this figure, with red color
were shown the position of the 100nF decoupling capacitors in
0805 cases, and with green, the position of the 10µF bulk
capacitors in case D.
ceramic per logic IC, combined with electrolytic or tantalum
capacitors up to a few hundred µF per board.
Figure 3. The PCB with the 100nF and 10µF decoupling capacitors.
The next step of this paper is to analyze the board
overdesigned. These kinds of simulations were made to see the
importance of a power integrity analysis to reduce the cost of a
PCB. Figure 4 shows the position of the decoupling capacitors
used to overdesign the system.
Figure 5. The overdesigned PCB.
The transfer impedance function was representative of the
results from all other combinations. All capacitors were
simulated with a total of 0.325nH mounting inductance.
For start, it was calculated the target impedance that we try
to meet using relation (1). The supply voltage was chosen to be
5V, with a 5% ripple and a current of 2A.
 Ztarget =
Figure 4. The overdesigned PCB.
5V∗5%
2A
= 125mΩ
The board was simulated in the frequency domain, without
any decoupling capacitor. As it’s shown in figure 6, the first
resonance peak occurs near 100MHz, determining large
voltage fluctuations. In this case, it is recommended to avoid
placing ICs which draw large currents near the resonant
voltage peaks/dips because it is easier to excite the resonant
modes.
To meet the target impedance, was selected a group of
decoupling capacitors, as shown in figure 5.
V.
FREQUENCY DOMAIN ANALYSIS
In this paper, simulations are used to select the best mix of
decoupling capacitors. The impedance can be measured by
using a 1A current source into a port. The voltage across the
current source is numerically the same as the self-impedance of
the PDN measured from the port. Voltages at other positions of
the circuits are numerically the same as the transfer-impedance,
which is the voltage across any two ports of the PCB divided
by the current forced at some other position of the circuit. By
selecting optimum values and quantities of decoupling
capacitors to be placed at various locations of the PCB, the
PDN can be designed to have relatively flat profile across a
broad frequency range.
Since decoupling capacitors differ in their high-frequency
characteristics, and capacitors with good high-frequency
properties are often types with small capacity, while large
capacitors usually have worse high-frequency response,
decoupling often involves the use of a combination of
decoupling capacitors. A common arrangement is 100nF
Figure 6. The transfer impedance between two ICs without the common
100nF and tantalum decoupling capacitors attached to the power pins of the
ICs.
To suppress the resonance, are attached to the PCB
traditional 100nF and 10µF decoupling capacitors. To a better
analysis of those decoupling capacitors, first, was simulated
using SPICE the electrical model of a voltage regulator module
(VRM) (Figure 7), the response of the transfer impedance of
the 100nF and 10µF decoupling capacitors that were used to
nullify the resonance of the transfer impedance from figure 6,
and the response of transfer impedance of a large number of
decoupling capacitors used to overdesigned the system.
Lslew
Lout
R0
Rflat
Figure 7. The electrical model for a VRM.
In figure 8, we can see in blue color the graph response of
the common decoupling capacitors in parallel with a VRM
electrical model; in pink, the VRM response without any
decoupling capacitors; in green, an overdesigned system, and
with red, the target impedance that we want to meet. Using
target impedance, involves choosing the number of decoupling
capacitors of each value such that the parallel combination
approximates the target impedance, by dividing the target
impedance into the ESR of the capacitor. In figures 3 and 4 we
can see that were used 5 10µ bulk capacitors with case D. A
10µ bulk capacitor has an ESR of 4.36315mΩ, from equation
(3); ESR resulted after the parallel mounting of the capacitors
is:
1
 ESR 5 = ESR ≈ 1mΩ 
Figure 9. The transfer impedance between two ICs with the common 100nF
decoupling capacitors attached to the power pins of the ICs.
If we compare the impedance from figure 8 with the
impedance from figure 9, we can observe that there almost
identical, the difference is that in figure 8, it is simulated an
electrical circuit of a VRM in parallel with the electrical
model circuit of decoupling capacitors using SPICE, and in
figure 9 is simulated the PCB using the same VRM parameters
and decoupling capacitors, but with a specialized software that
use the finite difference method to analyze the board.
5
This shows that if we want to obtain a 125mΩ target
impedance, all we need is a single 10µF bulk capacitor. Using
a single capacitor, the board area occupied by the decoupling
capacitors and the cost are reduced.
Figure 10. Transfer impedance between two ICs for a overdesigned system.
Figure 8. Graph response of the common 100nF and 10µF decoupling
capacitors attached to the power pins of the ICs, compared with 125mΩ target
impedance, a VRM response and a overdesigned system.
Figure 8 shows also that an overdesigned system only
creates an anti-resonance peak. Like in the case of the 10µ
decoupling capacitors, because the ESR of a 100nF is
54.325mΩ, it can be used only a single capacitor to decouple
the system and meet the 125mΩ target impedance.
In the next two figures, 9 and 10 is presented the result of
the simulation using the boards from figure 3 and 4, the PCB
with the common decoupling (figure 3) and the overdesigned
PCB (figure 4). These kinds of simulations were made to see
the effect of the power and ground planes in a power
distribution network, compared with the response of a single
decoupled VRM.
Traditional decoupling capacitors connected between
power and ground planes can be relatively ineffective at
frequencies above their self-resonant frequency. The next step
is to evaluate a decoupling strategy, using different techniques
for minimizing the inductance and improving decoupling at
frequencies above resonance.
The additional decoupling capacitors attached at the power
ground pins of the ICs are replaced by different types of
surface mounted capacitors (0603 and 0805), depending on the
self resonance frequency of the capacitors.
Seven different capacitors’ values were used for these
simulations, and the number needed for each capacitor was
calculated by dividing the ESR of each capacitor at the target
impedance, the number obtained was approximated with the
next integer number [3].
 N70p =
ESR
Ztarget
=
3.04337
125m
= 24.34 ≅ 25 
 N82p =
ESR
 N330p =
 N820p =
ESR
Ztarget
 N1µ =
=
ESR
ESR
Ztarget
ESR
Ztarget
ESR
Ztarget
=
125m
0.83572
125m
= 6.68576 ≅ 7 
0.43923
= 3.5138 ≅ 4 
125m
0.19169
125m
0.05432
125m
0.05432
125m
= 21.28 ≅ 22 
= 10.78 ≅ 11 
125m
=
=
2.66070
1.34796
=
Ztarget
 N10n =
=
=
Ztarget
 N2.2n =
 N100n =
ESR
Ztarget
= 1.5335 ≅ 2 
= 0.43456 ≅ 1
Assuming we can ignore the mutual inductance between
capacitor connections, the behavior of multiple capacitors can
be described using a simple circuit shown in next figure.
= 0.12312 ≅ 1
he parameters of each capacitor presented in table 1
include the package type, the capacitance value, the equivalent
series resistance (ESR), the equivalent series inductance
(ESL), the self resonance frequency of each capacitor and the
quantity or number of capacitors used to decouple the PDN.
The values of each capacitor were chosen after series of
simulations and depending on the self resonance frequency of
the capacitors. A single node simulation was used to select the
best mix of decoupling capacitors (Figure 11). Figure 11
shows resulting waveforms: the red color waveform represents
the target impedance, the green color, simulation of the VRM
and the planes without decoupling capacitors. We can observe
the high impedance near 50MHz. The impedance to the left of
50MHz is caused by the inductive behavior of the VRM, and
to the right, by the plane-pair going capacitive. However, to
correct this resonance, we added decoupling capacitors that
resonate at or near frequencies in the area of concern. Notice
that the blue color waveform, with decoupling capacitors
remains below target impedance at any frequency.
TABLE I.
Figure 11. The impedance of the PCB analyzed in a single node without and
with the necessary number and types of decoupling capacitors.
DECOUPLING CAPACITORS
Package
C
ESR [Ω]
ESL [pH]
Freq [MHz]
Quantity
0603
70pF
3.04337
525
625.5
25
0805
82pF
2.6607
710
546.3
22
0603
330pF
1.34796
525
300.5
11
0603
820pF
0.83572
525
190.6
7
0805
2.2nF
0.43923
710
105.5
4
0805
10nF
0.19169
710
49.5
2
0805
100nF
0.05432
710
15.6
1
0805
1µF
0.01539
710
4.9
1
Figure 12. The circuit model to describe the behavior of multiple capacitors.
In figure 13 is shown the graph response of every decoupling
capacitor based on the simulations of the electrical circuit
model of a decoupling capacitor (Figure 12) and in figure 14,
after using the quantity of decoupling capacitors needed to
meet the target impedance, it is shown the graph response of
each group of capacitors, and the impedance of all the
decoupling capacitors mounted in parallel. The capacitive,
resistive and inductive portions are easy to identify:
capacitance gives a slope of -20dB per decade on log/log
impedance vs. frequency (Bode) plot. Resistance gives a flat
response with frequency and inductance gives a +20dB per
decade slope.
100
Each different color signifies the color of each decoupling capacitor from Figure 5.
10
1.0
100m
10m
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
(V(R1:2)-V(V10:+))/I(V10:+)
(V(R2:2)-V(V11:+))/I(V11:+)
(V(R4:2)-V(V13:+))/I(V13:+)
(V(R5:2)-V(V14:+))/I(V14:+)
(V(R7:2)-V(V16:+))/I(V16:+)
Frequency
100MHz
1.0GHz
10GHz
(V(R3:2)-V(V12:+))/I(V12:+)
(V(R6:2)-V(V15:+))/I(V15:+)
Figure 13. Graph response of the decoupling capacitors from Table1.
For a better understanding of all the results obtained from
simulations, in figure 16 was presented a comparative view of
all the transfer impedances presented in this paper. We can see
that using the typical decoupling with 100nF and 10µF, we
waste board area and the cost increase; the target impedance is
met only near de self resonance frequency of the capacitors.
The anti-resonance and resonance peaks depend on the ESR of
each capacitor, and with calculated number of different
decoupling capacitors, the target impedance is maintained at
each frequency.
10
1.0
100m
10m
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
(V(Rload1:2)-V(V1:+))/I(V1:+)
(V(Rload2:2)-V(V2:+))/I(V2:+)
(V(Rload3:2)-V(V3:+))/I(V3:+)
(V(Rload4:2)-V(V4:+))/I(V4:+)
(V(Rload5:2)-V(V5:+))/I(V5:+)
(V(Rload6:2)-V(V6:+))/I(V6:+)
(V(Rload7:2)-V(V7:+))/I(V7:+)
(V(Rload8:2)-V(V8:+))/I(V8:+)
(V(Rload15:2)-V(V9:+))/I(V9:+)
Frequency
100MHz
1.0GHz
10GHz
Figure 14. Graph response of the parallel capacitors calculated to reach the
125mΩ target impedance.
In figure 15 is shown the transfer impedance of the PCB
with the decoupling capacitors from table 1 that were added to
correct the resonance. As it can be seen in the figure, the target
impedance is met from DC up to a few GHz and this
impedance is near the target impedance, so the power
distribution system wasn’t overdesigned and the finite product
works fine with optimum performance, at an acceptable cost.
VI.
CONCLUSIONS
The idea of this paper was to present a solution to design a
product that works with optimum performance at an acceptable
cost. We tried to meet the target impedance in all frequency
bands, and by meeting this target impedance is attained the best
compromise between cost, reliability, performance, and PCB
area. It was proposed a simulation test for a PCB with 4 layers
and power/ground planes, to evaluate the effectiveness and
importance of decoupling capacitors using tools and
methodologies to determine the important factors like
performance, cost and board area.
The steps of this paper were to take a PCB board with 4
layers and to simulate it without any decoupling capacitor, with
100nF and 10µF decoupling capacitors attached to every power
pin, and with selected values of decoupling capacitors obtained
after a set of simulations to compare the results in the
frequency-domain. It was also presented the effect of the VRM
using a circuit model.
Figure 15. The transfer impedance of the PCB with the decoupling capacitors
from table 1.
This paper showed the effects of decoupling capacitors on
the frequency-domain impedance. It was demonstrated that
using simulations, it can be selected a proper number of
decoupling capacitors to reduce the board area and the cost of a
PCB. Also, it can be designed a product that works just fine
with optimum performance at an acceptable cost.
REFERENCES
Figure 16. A comparative view of the all transfer impedance presented in
this paper.
[1]
I.Noval, J.R.Miller, „Frequency-Domain Characterization of Power
Distribution Networks“, Artech House, 2007
[2]
M. Swaminathan, A. E. Engin, „Power integrity Modelling and
Design for Semiconductors and Systems“, Prentice Hall Modern
Semiconductor Design Series, 2007
[3]
L.D. Smith, R.E.Anderson, D.W. Forehand, T.J Pelc, T. Roy, ''Power
Distribution System Methodology and Capacitor Selection for
Modern CMOS Technology'', IEEE Transactions on Advanced
Packaging, vol. 22, No. 3, August, 1999
[4]
E. Bogatin, “Signal and Power Integrity - Simplified”, Prentice Hall
Modern Semiconductor Design Series, 2010