CH/S6CS/Mar. 2005
A TYPICAL I/O SUBSYSTEM (p. 360 - 361 C. S. French)

An overview of a typical Input-Output (I/O) system in provided by figure 22.

A buffer is a temporary storage area that holds data during different stages of input or output. A buffer may
be one of the following types:
i.
Internal buffer area. This is an area of
output or data recently input but not yet processed.
main store
set aside to hold data awaiting
ii.
Buffer registers. These registers are located at various positions along the data path between the I/O
devices and the processor. They hold characters or groups of characters in the process of being
transferred.
Buffer +
Circuit
Console Panel
Lights + Switches
MAIN STORE
ALU
Main Store Access
Controller
Accumulators
I/O Bus and I/O Channel
Control
Channel 1
Channel 2
Multiplexor
I/O Control
Channel I/O
Control
Channel 3
Interface
Interface
Interface
Interface
Interface
Interface
Device Control
Device Control
Device Control
Device Control
Device Control
Device Control
Accumulators
Device
Accumulators
Device
Accumulators
Device
Accumulators
Device
Accumulators
Device
Accumulators
Device
“Slow” devices e.g. Scanners, printers, Handwriting reader
“Fast” devices e.g.
Disk Unit, Tape Unit
Data Path
Figure 22

A channel is a path along which I/O data signals flow. Control signals follow a similar path to regulate the
data flow. The peripheral end of the channel may be called a port.

A bus (also known as a highway) is an item of hardware within the processor through which data signals
pass from any one of a choice of sources to any one of a choice of destinations. On one side are connections
to the channels for various devices including memory, on the other are connections to accumulators in the
ALU.

An Interface is an item of hardware located on each channel adjacent to the processor. It converts control
and data signals from the processor, which are in a standard form, to forms usable by the device connected
to the interface. It also turns all peripheral input to one standard form for the processor.

The I/O control signals received by the interface from the processor are usually generated by I/O control
circuitry, which itself is under the control of the main control unit.

On the device side of the interface further device-control circuitry is at work. Part of it may be an integral
part of the interface, yet more is resident within the device itself. This control circuitry is capable of a large
amount of autonomous operation but works in response to conditions established by the I/O control
circuitry.
PERIPHERAL
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CH/S6CS/Mar. 2005
** Communication between the processor and peripherals are fraught with problems caused by the difference
in speeds between the two. Only for devices like magnetic disk or tape units can the speeds as compatible with
the processor.
A simple method of I/O (p.362 C. S. French)

The following 3 registers are present in the interface card:
i.
Data buffer register (1 byte). This holds 1 byte either received from or sent to the device.
ii.
Control bit register or "Busy" register (1 bit). This is set to 1 when the channel is opened, thereby
starting a transfer, and set to 0 if the channel is not to be used.
iii.
Device status register or "Done" register (1 bit). It is normally set to 0 as a busy is set to 1. It is set
to 1 when a signal is received from the device as it completes the transfer between itself and the data
buffer register.
Control signal
CPU
INTERFACE
DATA
DONE
BUSY
DEVICE
DATA BUFFER
AND
Figure 23

The following pseudo code shows the types of machine instructions used in the various stages of input.
Notation
B : Value of control bit register (BUSY)
D : Value of device status register (DONE)
begin
Start input on specified
device
while D <> 1
endwhile
The control circuitry will set B
to 0 and send signals that will
initiate transfer of a character
from the device to the data buffer
register. It will also set D to 0.
The peripheral then operates
autonomously.
Repeated checks to see if the
device has set the device status
register to 1, thereby indicating
the completed transfer of data to
the buffer
This is a "listen loop", The
processor would waste time
repeating this loop thousands
of times.
AC <-- [data buffer]
B <-- 1
main storage <-- [AC]
end.
Buffers ( p.363-364 C. S. French, p.184, 262-263 Ray Bradley)

It would be a very slow process if the computer continually had to interrogate the printer just to send one
byte. (refer to the above pseudo code)
Buffering is used

A buffer is a small amount of memory that is used to store data temporarily, e.g. a pointer may have a 10K
buffer.

The problem of the very slow method of sending one character at a time can be overcome by using a buffer.
PERIPHERAL
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CH/S6CS/Mar. 2005

e.g. for 10K printer buffer,
Bytes can be sent to the printer at a high speed before the printer busy signal would be generated again. That
means, if there is a 180 cps dot matrix printers, the printer can carry on for nearly a minute before needed
any attention of CPU  CPU is free for other processing.
begin
place data in buffers for output
repeat
Start devices for which input or output is required
Not those
already started
of course
repeat
process available data for a while
Devices are
autonomous
during this
Flags are checked
in turn for the
queue of Devices
Until
transfer any data from buffer to main store
place data in buffers for output
until no input or output is required
Use would be made
of an internal Buffer
area in Main Store.

Buffering means the technique of transferring data into temporary storage prior to processing or output.

Buffering enables the simultaneous operation of devices as in fig. 24.
CHARACTER FROM DEVICE 1 – “B”
AB
CHARACTER FROM DEVICE 2 – “Q”
P
CHARACTER FROM DEVICE 3 – “Z”
XYZ
Buffer area
for device 1
Buffer area
for device 2
Buffer area
for device 3
fig. 24
** Status register (p. 347 C. S. French)

A status register has its contents set by hardware devices such as the ALU and is used by the control unit.
(refer to fig 23)

Each bit in the status register, known as a flag, is used to check for various conditions of the processor at
any time.

Bits in the status register could be used to signify result states such as:
i.
ii.
iii.
iv.
v.
Zero result
Negative result
Positive result
Overflow
Parity error.
PERIPHERAL
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CH/S6CS/Mar. 2005
status of
result
results
external status of data
STATUS
REGISTER
ALU
clock
CONTROL
UNIT
To an external
control bus
To an external
address bus
INDEX
POINTER
INDEX
REGISTER
ACCUMULATOR
WORKING
REGISTER
PC
MAR
IR
INTERNAL BUS (e.g. 16 bits)
MDR
To and from an
external data bus
Figure 25
Autonomy (Direct Memory Access, DMA) (p365-366 C.S. French, p.491 Ray Bradley)

There are data transfer between main store and devices such as disk and tape units through a direct channel
often called a
data channel
. (refer to fig 22)

Once the necessary conditions have been established by software, the transfers are entirely under the control
of hardware.

The data channel "steals" memory cycles from the instruction currently being performed in order to do the
transfer. Thus it slows down the rate of program memory access of foreground operations, but as a whole,
speeds up the overall performance.

Once started the device has autonomous operation. ( Autonomy )

The above technique is known as
Direct Memory Access
controller used is known as
DMA controller

( DMA ).
The I/O
.
DMA with magnetic tape units
i.
Software setup (CPU control):
a.
Wind the tape to bring the Read/Write heads over IBG such that the head lies in front of the first
block of records on the tape file to be read.
b.
A special register named memory address counter register is set to be address of the first location
in the internal buffer area.
c.
Another register is set to be the total number of records or blocks to be read.
d.
Issue the tape read instruction.
PERIPHERAL
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CH/S6CS/Mar. 2005
ii.
Hardware take over (Autonomous operations):
a.
The tape is brought up to speed.
b.
When the read heads detect the start of block to be read, a control signal is issued by the tape drive
I/O control.
c.
The control unit automatically uses the next available memory cycle to transfer the first character
between the tape block and the address specified in the memory address counter register.
d.
The memory address counter register and the counter of number of records transferred are
updated.
e.
The hardware continues automatically to steal memory cycles until the counter indicates that the
transfer is completed.
f.
A "done" flag is set by the I/O control unit.
Polling (p.380 C.S. French)

It is one of the simplest methods for deciding which device should be served by the CPU first and how that
device can be identified.

An external device requests an interrupt by activating an interrupt request line that is common to all devices.

The polling process of interrupt request is as follows:
i.
Polling the device one by one.
ii.
The first device encountered with its Ready bit in the status register set is the device that should be
serviced.
iii.
The appropriate interrupt service routine is then called. A time limit ( time slice ) is given to that
service routine.
iv.
When time slice expired or the service routine completed, the polling will be started again from the
next device.

Advantage of polling: very simple and easy to implement.

Disadvantage of polling: the time spent interrogating the status bits of all the devices that may not be
requesting any service  redundancy.
Interrupt (p. 456-457, 477-478, 489-490 Ray Bradley, p. 366-369, 376-377C.S. French)

An interrupt is a request from an I/O device for service by the processor or from a program for service to
handle I/O.

Practically, an interrupt is a threat into the normal automatic sequential control, so that instead of fetching
the next instruction as part of the fetch-execute cycle, the control unit fetches the first instruction of another
program, or an instruction from another part of the same program.

Just prior to fetching the next instruction, the processor check if there is any interrupt request (IRQ).

If there are requests, a threat in the normal sequence of instruction is made and the requests are dealt with.

Afterward, the control is returned to the original interrupted program.

The checks for interrupts are only done if the interrupt system is activated. (There are instructions turning
the interrupt system on or off - to be discussed later).

There may be more than one device that will request an interrupt at any given time. Some strategy should be
developed on deciding which device should be serviced first.
PERIPHERAL
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CH/S6CS/Mar. 2005
  A position of priority may be assigned to each device.

A program can request an interrupt to input or output data in a similar way to a device.
Interrupt-service routine (ISR) .

The routine executed that response to an interrupt request is called the _____________________________
(__________).

Treatment of an interrupt service routine is very similar to that of a subroutine except that the interrupt
service routine may not have anything in common with the program being executed at the time the interrupt
request is received.

Steps for interrupting:
i.
I/O device sends an interrupt request signal to CPU.
ii.
CPU sends an interrupt-acknowledge signal to I/O device.
iii.
Store the following data onto the processor stack :
a.
return address in PC;
b.
processor status word in the status register; and
c.
other register contents in CPU (optionally)
iv.
Load the content of PC with the starting address of the routine.
v.
Execute the routine. In most cases, the routine makes a number of decisions regarding the choice of
most appropriate action.
vi.
Upon return from the routine, the data of the interrupted which have been stored on the stack are loaded
back to appropriate registers.
Interrupt vectors (P. 477-478 Ray Bradley)

The CPU must find out which device is causing the interrupt.
_____________________.

An interrupting device supplies a number that is then added to a fixed number as shown in and fig. 26, forms
the address of the memory location which contains the jump address where the routine to handle the
interrupt can be found.
Fixed number
(top 4 bits)
1111
Number supplied
by device 6
(bottom 4 bits)
0110
F
6
11110110
main memory
0000FC84
Routine to
0000FC85 handle device
0000FC86
no. 6
0000FC87
:
F
One of the methods is
Interrupting
device
No. 6
6
0000F6
0000F7
0000F8
0000F9
:
0000FC84
0000FD22
0000FDA4
0000FE00
:
Interrupt handling table
(part of memory)
Figure 26

The numbers inside the memory location which are used as pointers to the places where the interrupt
handling routines can be found are called ________________. Here is a sample interrupt request in fig. 27.
PERIPHERAL
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Push registers onto stack
Original
PC
00001000
00001001
00001002
00001003
00001004
Device 2
Device 3
1003
PC
Jump 2046
Device 1
interrupt register
3
base address
1000
Device 4
Device 5
Device 6
00002046
Device 3
00002047 handling routine
00002048
…
00002049
0000204A
Return
PC
00002046
PC
Original
Retrieve registers from stack and
continue after interrupt
figure 27
Interrupt Priority (p. 489-491 Ray Bradley)

There are many different devices that can cause an interrupt in a single computer system. All of them have
different needs in terms of urgency. The system is thus necessary to assign priorities to these different types
of interrupts (interrupt priority ).

On a small computer, there may be only 2 types of interrupt priorities, high or low.

i.
Sample high priority interrupt: updating a real-time system clock.
ii.
Sample low priority interrupt: user-generated interrupt of such as a burglar alarm.
Each level may be enabled (unmasked) or disable (masked) by both hardware and software.
Processor
System
clock
Highest
Real time
clock
Power failure
routine
Typical levels of priority
Tape / disk
M / CS
Others
Lowest
Figure 28

Each device on a particular level has the same priority. The device cause an interrupt first gets priority.

Assume that device 1 has the highest priority where device 4 has the lowest one.
PERIPHERAL
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CH/S6CS/Mar. 2005
Interrupting devices
CPU
Notes
(Note * means that the device has requested an
interrupt. The * is cancelled after the interrupt
has been serviced. M means that the CPU is
engaged in carrying out its main task.
Device
Device
Device
Device
Main task
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
-
*
*
-
MMMMMM
MMMMMM
444444
444444
MMMMMM
222222
222222
222222
333333
333333
MMMMMM
MMMMMM
222222
111111
111111
222222
222222
333333
333333
222222
222222
222222
444444
444444
MMMMMM
MMMMMM
MMMMMM
Device 4 receives processor attention
Device 4 finished, main task reinstated
Device 2 receives attention
Device 3 ignored (lower priority than 2)
Device 3 gets attention as 2 has finished
Main task reinstated as no more interrupts
Device 2 gets attention
Device 1 overrides device 2 service routine
Device 4 gets totally ignored for the moment
Device 2 reinstated
Device 3 ignored
Device 3 now serviced even though 4 was first
Device 2 now being serviced
Device 4 at last
Main task reinstated

Interrupt masking. As in the above example, when the interrupt of higher priority is being handled those
interrupts of lower priority is disabled (or masked), i.e. cannot be serviced until the higher priority interrupt
serviced routine completes.

It is the job of the operating system (O.S.) to make sure that priorities are assigned in such a way as to
maximise the efficient use of CPU time as well as to protect disaster occurring.

Sample devices causing an interrupt:

i.
Ctrl-Break from the keyboard.
ii.
Detecting an imminent power failure by the electronics (so saving all current work).
Some Categories of interrupts:
i.
external interrupts: hardware device
ii.
program fault interrupts (program error trap):
iii.
timer interrupts: e.g. infinite loop
e.g. Arithmetic overflow
** Interrupt flag register. It holds bits showing which devices are interrupting.
*** Interrupt enable / disable register. This is another register inside CPU where bits control how interrupts
in the system will be carried out. Each device has a bit in it. ('1' for enable, '0' disable).
PERIPHERAL
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