P2P – protocol, Rev. 1.1
FLINK – Point to Point Protocol , short description
PCI Configuration Registers (located in PCI Bus Controller ‘S 5933’, see AMCC
S5933-Data Book)
LAT
Master latency (Config Space, R/W)
for tuning the DMA speed
PCI Bus Operation Registers (located in PCI Bus Controller ‘S 5933’, see AMCC
S5933-DATA Book)
Access: Read/Write at Base Address #0 + 00h..3Ch
These regs.+adr. are chosen to control the interface:
comment
IMB1
10
Incoming Mailbox Register #1
ISR register, if IntEnable=1 (ICR)
FIFO
20
FIFO register port, bidirectional
MWAR
MWTC
MRAR
MRTC
24
28
2c
30
Master Write Address Register
Master Write Transfer Count
Master Read Address Register
Master Read Transfer Count
can be used as 32 bit I/O port for
Rx/Tx FIFO access
for DMA control
Write = S5933_Fifo =>PC_Memory
MCSR
3c
Bus Master Control/Status Register
for DMA control
Interrupt Control/Status Register
for Polling ,or PCI Bus-Interrupt
on DMA, or Mailbox status
INTCSR 38
Read = PC_Memory => S5933_Fifo
Interface Control/Status Register (located in ALTERA chip)
Access: 32 bit Read/Write at Base Address #1 + 00h..14h (pass through access)
ICR
ISR
IER
GRX
SRX
STX
GTX
00
04
08
0c
10
14
18
Interface Control Register
Interface Status Register
Interrupt Enable Register
Get RxFIFO Level
Set RxFIFO Reference Level
Set TxFIFO Almost Empty Level
Get TxFIFO Level
Address map , addresses as offsets to Baseaddress#1,
Name
ICR
ISR
IER
GRX
SRX
STX
GTX
p2p.doc, 25. Oct. 99, K.-H. Sulanke
Address
(hex)
00
04
08
0c
10
14
18
Resetvalue
10
C
0
0
7ff
7ff
0
R=read, W=write, O=only, all in hex
Notes
R/W
RO
R/W
RO
R/W
R/W
RO
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Bit4..0
Bit4..0
Bit4..0
Bit11..0, word count
Bit11..0, word count
Bit12..0, word count
Bit12..0, word count
P2P – protocol, Rev. 1.1
Interface Control/Status Registers
Interface Control Register
'ICR' , R/W at Baseadr#1
+ 00h
bit
signal
comment
0
IntEnable
1
2
3
4
n.u.
n.u.
TxReset
RxReset
global Int_Enable for Add_on_side;
if Interrupt: ISR -> Mailbox#1; IntEnable = 0;
must be set again after Interrupt;
not used,
not used,
clears Tx_Fifo's
clears Rx_Fifo's and RxACK (~nowledge) Signal,
is also set after AddOnReset (s.a. MCSR-reg.)
and Power On
Interface Status Register
'ISR' , RO at Baseadr#1
+ 04h
bit
signal
comment
0
1
2
3
4
RxNotEmpty
RxLevel
TxEmptyFlag
TxAEF
ParErr
at least one word is in the RxFIFO
GRX > SRX, RxFIFO level greater than RxFIFO reference level
TxFifo and S5933_ PCI _to_Add_On -FIFO are empty
GTX < STX , TxFIFO level below the TxFIFO reference level
Parity error detected, remains set until RxReset=1 (ICR)
Interrupt Enable Register
'IER' , R/W at Baseadr#1
bit
signal
comment
0
1
2
3
4
IntOnRxNotEmpty
IntOnRxLevel
IntOnTxEmptyFlag
IntOnTxAEF
IntOnParErr
at least one word is in / or flew through the RxFIFO
GET RxFifoLevel Register 'GRX' , RO at Baseadr#1
bit
11..0
+ 08h
+ 0Ch
comment
count of Words, contents of RxFifo
available for read = GRX + 8 (S5933-FIFO)
SET RxFifoLevel Register 'SRX' , R/W at Baseadr#1 + 10h
bit
11..0
comment
count of Words, to compare with GRX
SET TxFifoLevel Register 'STX' , R/W at Baseadr#1 + 14h
bit
12..0
comment
count of Words , to compare with GTX
GET TxFifoLevel Register 'GTX' , RO at Baseadr#1
bit
12..0
+ 18h
comment
count of Words, contents of TxFifo
Rem.: Word means 32 bit .
p2p.doc, 25. Oct. 99, K.-H. Sulanke
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P2P – protocol, Rev. 1.1
ALTERA configuration-register, 'ACR' (located in PLD GAL18V10)
Access: 32 bit Read/Write at Base Address #3 + 00h (pass through access)
write operation
bit
0
1
2
read operation
bit
0
1
signal
data0
dclk
config
comment
ALTERA chip - serial data input
ALTERA chip - serial clock
ALTERA chip - start signal for configuration
signal
conf_done
nstatus
comment
ALTERA chip – configuration ready
ALTERA chip – low active configuration status signal
Last protocol changes
 addtional register GTX
 STX is R/W now
 STX, GTX have 12 bit instead of 11
p2p.doc, 25. Oct. 99, K.-H. Sulanke
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