Code.No: R05420406
R05
SET-1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEM–REGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DSP PROCESSORS & ARCHITECTURES
(Common to ECE, EIE, BME, ETM)
Time: 3hours
Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
--1.a)
b)
Briefly explain about decimation & Interpolation?
Write a MATLAB Program to find the frequency response of an FIR filter? [8+8]
2.
Compute the dynamic range and percentage resolution of a signal that uses:
a)
16-Point fixed-point format
b)
32-Point floating-point format with 24 bits for the mantissa and 8 bits for
the exponent.
[16]
3.a)
b)
Explain about Bus Architecture and Memory in DSP devices.
 8 multiplier using 4  4 multipliers as building
How will you implement an 8
blocks?
[8+8]
4.a)
b)
Explain about branching effects, interrupt effects.
Explain about pipelining and performance.
[8+8]
5.a)
What is the use of the following register of 54x:
i)
T
ii)
TRN
iii) BIC
iv) XPC
Explain the operation of exponent encoder in 54x.
[10+6]
b)
6.a)
b)
Write a TMS320C 54XX Program for the implementation of a FIR filter.
Write a TMS320C 54XX Program to multiply two Q 15 numbers.
[8+8]
7.a)
b)
Explain the FFT algorithm for DFT computation.
Explain the 2-point DFT computation using signal flow graph.
[8+8]
8.a)
b)
What is Direct Memory Access (DMA) in digital signal processors.
What is Synchronous serial interface? Explain.
[8+8]
-oOo-
Code.No: R05420406
R05
SET-2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEM–REGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DSP PROCESSORS & ARCHITECTURES
(Common to ECE, EIE, BME, ETM)
Time: 3hours
Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
--For the IIR filter H z 
1.
a)
b)
c)
d)
e)
2.a)
b)
z 1
determine the

z  0.25 z  0.5  

Magnitude response function.
Phase response function.
Impulse response.
Step response.
Poles & zeros.
[16]
Calculate the dynamic range and precision of each of the following number
representation formats.
i)
24-bit, single Precision, fixed point format
ii)
48-bit, double Precision, fixed point format
iii)
A floating point format with a 16-bit mantissa and an 8-bit exponent.
Explain about A/D conversion errors in DSP implementations.
[8+8]
3.
Explain about different DSP computational building blocks.
[16]
4.a)
b)
Briefly discuss about hardware looping.
Explain about pipeline programming models.
[8+8]
5.a) Can you load T-register using immediate addressing mode? If so give an example.
b) Write a program for the implementation of a PID controller using
TMS320C54XX.
[6+10]
6.a)
b)
Develop a TMS320C54XX subroutine to multiply 3  3 matrices.
What values are represented by the 16-bit fixed point number N = 4000h in Q15 and
Q7 notation.
[10+6]
7.a)
b)
Explain the bit reversed index generation in general.
Draw the butterfly diagram of 4-point DIF-FFT and explain algorithm.
8.a)
b)
Explain the mode control interface signal timing for the PCM 3002 CODEC.
Which bits and register of the PCM 3002 (CODEC) are used to program the
application of a 48 kHz de-emphasis to DAC output of the PCM 3002? Determine
bit setting.
[8+8]
-oOo-
[8+8]
Code.No: R05420406
R05
SET-3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEM–REGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DSP PROCESSORS & ARCHITECTURES
(Common to ECE, EIE, BME, ETM)
Time: 3hours
Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
--1.a)
b)
Write a MAT LAB Program to find the butterworth lowpass IIR filter design.
n 0 2 4 6 8 is interpolated using the interpolation
The signal sequence x 
filter sequence b k = [0.5, 1, 0.5] and the interpolation factor is 2. Determine the
interpolated sequence y(m).
[8+8]
2.a)
b)
Explain about different types of errors in DSP implementations.
Find the degradation in amplitude gain when a sine wave of unit amplitude and 50 Hz
frequency, sampled at 400 Hz, is reconstructed using a zero-order hold.
[8+8]
3.a)
Compute the sequence in which the input data should be ordered for a 16-point
DIT FFT.
Briefly explain about data addressing capabilities.
[8+8]
b)
4.a)
b)
Explain about system level parallelism and pipelining.
Explain about programmability and program execution.
5.a)
b)
Give brief account of memory space of TMS 320 C54XX processors.
Explain about indirect addressing mode of TMS320 54XX with suitable example.
[10+6]
6.a)
b)
Write short notes on adaptive filters.
Write a program for the implementation of a PID controller using TMS320C54XX.
[6+10]
7.
Draw the butterfly diagram of 8-point DIF-FFT and explain the algorithm.
8.a)
b)
Explain about extended memory map of TMS 320C 5416.
Draw the timing diagram of memory interfacing signals for a read-write sequence of
operations.
[8+8]
-oOo-
[8+8]
[16]
Code.No: R05420406
R05
SET-4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.TECH II SEM–REGULAR/SUPPLEMENTARY EXAMINATIONS MAY - 2010
DSP PROCESSORS & ARCHITECTURES
(Common to ECE, EIE, BME, ETM)
Time: 3hours
Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
--n 
x n  
1 x n 2 3 determine:
For the FIR filter y n  
 x 
a)
System function
b)
Magnitude response function
c)
Impulse response
d)
Step response
e)
Poles and zeros.
1.
2.a)
b)
3.a)
b)
[16]
Explain about different types of number formats for signals & coefficients in DSP
Systems.
Show that the dynamic range of a signal increases by 6 dB for each additional bit
used to represent its value.
[8+8]
What distinguishes a digital signal processor from general-purpose micro processor
with regard to basic capabilities?
Explain about parallelism and pipelining.
[8+8]
4.a)
b)
Explain about branching effects and interrupt effects.
Explain about pipeline programming models.
[8+8]
5.a)
Describe the operation of the following MAC instructions:
i)
MAC * ARS +, # 1234 h
ii)
MAC * AR3 , *AR4+, B, A
Write short notes on clock generation and serial I/O ports.
[6+10]
b)
6.a)
b)
Write a TMS320 C54XX program for an interpolation filter implementation.
Briefly discuss about decimation filters.
[10+6]
7.a)
b)
Derive the optimum scaling factor for the DIT-FFT butterfly.
Explain the computation of the signal spectrum.
8.
Draw the multichannel buffered serial port (MCBSP) block diagram and explain
each signal.
[16]
-oOo-
[8+8]