In this experiment you will modify the TV demonstration design that comes with the DE2-70 development board. It converts an input composite video signal to a VGA output and displays it on a LCD/CRT monitor. Your objective is to rotate the picture upside-down by pressing a button
(lab1) or through a C language program running on a NIOS II computer system (lab2).
Keep in mind the following information:
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The FPGA device is EP2C70F896C6N.
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Use NIOS II IDE. Instructions are provided here: o http://www.ict.kth.se/courses/IS1200/2008-2009/nios2setup/idedetail.html
o http://www.ict.kth.se/courses/IS1200/2008-2009/nios2setup/idedetail.html
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Use pin AD15 for 50 MHz clock input.
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Use pin T29 for reset (This is KEY0 button on DE2-70).
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All the necessary pin assignments can be found in file DE2_70_pin_assignments.csv
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Mind the address map of the computer you have designed in SOPC builder when you program it in NIOS II IDE. After building your project you can find that information in a
“system.h” file under your system library debug or release folder.
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The following links give more information about the data formats within the TV demonstration design: o http://en.wikipedia.org/wiki/YCbCr o http://en.wikipedia.org/wiki/Chroma_subsampling o http://en.wikipedia.org/wiki/Composite_video o http://en.wikipedia.org/wiki/NTSC o http://en.wikipedia.org/wiki/Interlace
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The following documents are necessary for understanding and completing the laboratory experiments (you can find them in the “Documents” folder): o Nios II Processor Reference Handbook o Introduction to the Altera Nios II Soft Processor o Introduction to the Altera SOPC Builder o PIO Core o Avalon interface specification o SOPC Components
 When you make your Quartus II or NIOS IDE project directories don’t leave spaces in the names.
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Whenever you add new peripheral device to your computer in SOPC builder, perform an
“Analysis and Elaboration” in Quartus II before adding pins (so the changes would be made available).

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Use ModelSim Altera for simulating your Verilog designs.
Lab1
Your objective is to modify the design in a way that you will be able to rotate the image that is displayed on the LCD/CRT monitor to a 180 degree and vice versa by pressing a button. The design files are located in a “DE2_70_TV” folder. Here is a short description of the main modules in the design:
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DE2_70_TV.v – This file contains the top level module.
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TD_Detect.v – Detects a valid video input.
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ITU_656_Decoder – Converts the video from ITU-R 656 format to YUV 4:2:2 format. (check the links above for more information)
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DIV.v – Used by the previous module to reduce the horizontal resolution from 720 to
640 lines per frame (pixels per line).
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Rotation_Buffer.v – A skeleton file, containing an input FIFO (first in first out buffer), output FIFO, a PLL and a SSRAM memory interface which you will use to implement video frame rotation.
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Sdram_Control_4Port.v – A buffer used for combining the odd and even fields of a frame (Fig.4).
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YUV422_to_444.v – Converts the video from 4:2:2 format to 4:4:4 format. (check the links above for more information)
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YCbCr2RGB.v – Converts the video word from 8 to 10 bits to match the video output
DAC (digital to analog converter).
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VGA_Ctrl.v – Controls the output to the CRT/LCD monitor.
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Line_Buffer.v – One line delay buffer used for de-interlacing the picture.
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I2C_AV_Config – Module controlling the video decoder.
The design contains an audio input and output which is outside the scope of the current experiment!
Look carefully within each of those design files and understand how the system works. Pay special attention to the data formats at each point.
Rotation_Buffer module (located in Rotation_Buffer folder) is the one you need to modify in order to rotate the output video. You will use a SSRAM memory to store two video frames – writing into one and reading the other. Fig.4. shows the structure of one video frame. The memory has 32 bit word size and in order to fit two video frames (508x640) in it you need to pack two pixels (16 bit each) into one memory word. To meet the video data stream throughput you need to access the memory at 100 MHz – use the PLL for that. The input and output data

clock is around 27 MHz and you need to use FIFOs as clock domain bridges. Use the debounced buttons on the DE2-70 board for switching between rotated and normal video. The waveforms for the FIFOs and the memory interface are shown on Fig1, Fig.2 and Fig.3.
Fig.1 Input FIFO waveforms
Fig.2 Output FIFO waveforms

Fig.3 SSRAM memory interface waveforms
You can modify those modules, if you find it necessary. Currently the inputs and outputs of the Rotation_Buffer module are tight together and if you synthesize and implement the design you should be able to see a VGA video output on your LCD/CRT monitor. Currently KEY[0] is the system reset button. You might want to sample some of the other de-bounced buttons during reset to set the output (rotated or not).

Fig.4. Video Frame
Lab2
Create a simple NIOS II computer system (NIOS IIs processor, on-chip memory, JTAG
UART). Design a slave peripheral with a single memory mapped register and attach it to the
NIOS II computer system. You can follow the approach in Experiment 2, Lab2, Part I or read the
Avalon memory mapped interface specification and the SOPC builder new component walkthrough (available in the “Documentation” folder) and build and add the component yourself. Instantiate the NIOS II computer system within the Rotation_Buffer module. Use separate reset signals for the TV demonstration design and for the NIOS II computer system. Use one bit of the memory mapped register of your component to set the picture mode (rotated or not) and one bit to reset the TV demonstration design. Write a C program in NIOS II IDE to read a button and set the VGA output mode (or if you like just set the mode with a software command). You might need to reset the design after changing the mode for resynchronization.
Further works : For your own exercise you are encouraged to add 90º and 270º rotation to the system.
Todor Mladenov 2009