MAGiK-MX OMAP based System Module
www.tesbv.com/magik
09030003-102- 480-1.0
TES MAGIK-MX
OMAP 3530 SM
Feb 2010 Datasheet
1
MAGiK Synergy in Media and Graphics
MAGiK-MX OMAP based System Module
www.tesbv.com/magik
09030003-102- 480-1.0
In this manual are descriptions for copyrighted products that are not explicitly indicated as such. The
absence of the trademark (®) and copyright (©) symbols does not imply that a product is not
protected. Additionally, registered patents and trademarks are similarly not expressly indicated in
this manual.
The information in this document has been carefully checked and is believed to be entirely reliable.
However, TES Electronic Solutions GmbH assumes no responsibility for any inaccuracies. TES
Electronic Solutions GmbH neither gives any guarantee nor accepts any liability whatsoever for
consequential damages resulting from the use of this manual or its associated product. TES Electronic
Solutions GmbH reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, TES Electronic Solutions GmbH offers no guarantee nor accepts any liability for damages
arising from the improper usage or improper installation of the hardware or software. TES Electronic
Solutions GmbH further reserves the right to alter the layout and/or design of the hardware without
prior notification and accepts no liability for doing so.
© Copyright 2010 TES Electronic Solutions GmbH, D-70567 Stuttgart.
Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction
and storage or proceI2Sng in computer systems, in whole or in part are reserved. No reproduction
may occur without the express written consent from TES Electronic Solutions GmbH.
Feb 2010 Datasheet
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Table of contents
1
DEFINITIONS, ABBREVIATIONS AND ACRONYMS ......................................................................... 7
1.1 Definitions ................................................................................................................................ 7
1.2 Abbreviations ........................................................................................................................... 7
1.3 Acronyms ................................................................................................................................. 7
1.4 MAGiK Terminology ................................................................................................................. 7
2
OVERVIEW ..................................................................................................................................... 8
2.1 Purpose .................................................................................................................................... 8
2.2 Board Overview ....................................................................................................................... 8
2.2.1
Top / Bottom View ......................................................................................................... 8
2.3 Reference Number ................................................................................................................... 9
3
SPECIFICATION ............................................................................................................................ 10
3.1 Absolute Maximum rating ..................................................................................................... 10
3.2 Physical Dimensions ............................................................................................................... 10
3.3 RoHS Compliancy ................................................................................................................... 10
4
MAGIK-MX SYSTEM MODULE FEATURES .................................................................................... 11
4.1 MAGiK-MX Block Diagram ..................................................................................................... 11
4.2 Features ................................................................................................................................. 12
4.2.1
Processor OMAP 3530 ................................................................................................. 12
4.2.2
Power Management Unit............................................................................................. 12
4.2.3
Micro SD Card Reader .................................................................................................. 13
4.2.4
Mobile DDR .................................................................................................................. 13
4.2.5
Nand Flash.................................................................................................................... 13
4.2.6
Nor Flash ...................................................................................................................... 13
4.2.7
MAC/PHY Controller .................................................................................................... 13
4.2.8
LED ............................................................................................................................... 13
4.3 External Interfaces ................................................................................................................. 14
4.3.1
Power Output............................................................................................................... 14
4.3.2
Power Input.................................................................................................................. 14
4.3.3
USB I/F (1V8 Level) ....................................................................................................... 14
4.3.4
UART I/F (1V8Level) ..................................................................................................... 16
4.3.5
I2S I/F (1V8 Level) ........................................................................................................ 16
4.3.6
I2C I/F (1V8 Level) ........................................................................................................ 17
4.3.7
Camera I/F (1V8 Level) ................................................................................................. 17
4.3.8
JTAG I/F (1V8 Level) ..................................................................................................... 18
4.3.9
Ethernet I/F (Ethernet STD Level) ................................................................................ 18
4.3.10 GPMC Memory I/F (1V8 Level) .................................................................................... 19
4.3.11 DSS Video Out I/F (1V8 Level) ...................................................................................... 20
4.3.12 SPI I/F (1V8 Level) ........................................................................................................ 20
4.3.13 MMC2 SDIO I/F (1V8 Level).......................................................................................... 20
4.3.14 GPIO I/F (1V8 Level) ..................................................................................................... 21
Feb 2010 Datasheet
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4.3.15
4.3.16
09030003-102- 480-1.0
TVOUT I/F (Analog Output) .......................................................................................... 22
OTHERS I/F ................................................................................................................... 22
5
MAGIK-MX SYSTEM MODULE BOARD TO BOARD CONNECTOR ................................................. 23
5.1 Board to Board Connector1: J1 .............................................................................................. 23
5.2 Board to Board Connector2: J2 .............................................................................................. 25
6
POWER MODE AND POWER MANAGEMENT.............................................................................. 27
7
MAGIK-MX SYSTEM MODULE MEMORY MAP ............................................................................ 28
8
MAGIK-MX SYSTEM MODULE BOOT CONFIGURATION SETTINGS.............................................. 29
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List of Figures
Figure 1 :
Figure 2 :
Figure 3 :
Figure 4 :
Figure 5 :
Figure 6 :
Top View ............................................................................................................................ 8
Bottom View ...................................................................................................................... 9
Processor Board Physical Dimensions (TBC).................................................................... 10
MAGiK-MX Block Diagram ............................................................................................... 11
GPMC Address Management conform to TI recommendation....................................... 19
Resistor configuration for boot mode ............................................................................. 29
Feb 2010 Datasheet
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List of Tables
Table 1 :
Table 2 :
Table 3 :
Table 4 :
Table 5 :
Table 6 :
Table 7 :
Table 8 :
Table 9 :
Table 10 :
Table 11 :
Table 12 :
Table 13 :
Table 14 :
Table 15 :
Table 16 :
Table 17 :
Table 18 :
Table 19 :
Table 20 :
Table 21 :
Table 22 :
Table 23 :
Table 24 :
Processor Board Absolute Maximum Rating....................................................................... 10
LEDs function on MAGiK-MX ............................................................................................... 13
Current Available for Voltage output .................................................................................. 14
Power Output description ................................................................................................... 14
Power Input description ...................................................................................................... 14
USB ULPI I/O description ..................................................................................................... 15
UART I/O description........................................................................................................... 16
I2S I/O description ............................................................................................................... 16
I2C I/O description .............................................................................................................. 17
Camera I/O description ................................................................................................... 17
JTAG I/O description ........................................................................................................ 18
Ethernet I/O description .................................................................................................. 18
GPMC Memory I/O description ....................................................................................... 19
SS I/O Description ............................................................................................................ 20
SPI I/O Description ........................................................................................................... 20
SDIO I/O Description........................................................................................................ 20
GPIOs I/O Description ...................................................................................................... 21
TVout I/O Description ...................................................................................................... 22
Others I/O Description..................................................................................................... 22
Board to Board Connector 2: J1....................................................................................... 24
Board to Board Connector 2: J2....................................................................................... 26
MAGiK-MX Processor Board Power Mode ...................................................................... 27
MAGiK-MX Processor Board Memory Map ..................................................................... 28
MAGiK-MX Boot Sequence .............................................................................................. 29
Feb 2010 Datasheet
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1 Definitions, Abbreviations and Acronyms
1.1 Definitions
MAGiK
MAGiK-MX
OMAP
:
:
:
Media and Graphics Innovation Kit
MAGiK Multimedia Extended Processor board based on OMAP 3530
OMAP3530
1.2 Abbreviations
N.A.
TBC
TBD
:
:
:
Not applicable
To be confirmed
To Be Defined
1.3 Acronyms
PRB
SPI
I2C
I2S
USB
UART
LED
BTB
GPMC
PMU
:
:
:
:
:
:
:
:
:
:
Processor Board
Serial Peripheral Interface
Inter Integrated Circuit
Inter-IC Sound
Universal serial Bus
Universal asynchronous Receiver Transmitter.
Light emitting diode.
Board to Board Connector
General Purpose Memory Controller
Power Management Unit
1.4 MAGiK Terminology
SM
MAGiK-MX
MAGiK-MPI
IO Board
LCD Board
OpenCORE
Guiliani
C Services
D-Bus
BSDUtils
Conman
SSL
:
:
:
:
:
:
:
:
:
:
:
:
Feb 2010 Datasheet
System Module
MAGiK System Module Media eXtravaganza (OMAP3530)
MAGiK System Module Media portable & Industrial (i.MX27)
MAGiK host board for System Module
MAGiK LCD Adapter board
Media Framework
HMI Framework
C. C++, Pthreads, Glib all libraries
Messaging service
Shell services
Connection Manager for network operations
Secure socket layer
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2 Overview
2.1 Purpose
The MAGiK-MX System Module is a Processor Board which provides time to market solutions with
production ready design. Based on latest TI OMAP 3530 processor the module and its accompanying
software enable a host of applications bringing synergy between Media and high quality desktop like
Graphics.
2.2 Board Overview
MAGiK-MX is a full OMAP 3530 system module on a board
Main feature of MAGiK System Module are following:
 OMAP 3530 TI Media Processor
 256 MB of DDR-SDRAM
 512 MB of NAND Flash
 64 MB of NOR Flash
 Micro SD card reader
 Ethernet MAC Controller
 Power Supply Unit (Input = 5V)
 2 Connector for board to board link:
o USB
o Ethernet
o Camera I/F
o Video out
o Audio I/F
o Memory I/F
 Running on Linux or Windows CE
2.2.1 Top / Bottom View
OMAP 3530
Processor
Ethernet 10/100
Mac+Phy Controller
64 MB
NOR-Flash
2 x 128MB
Mobile DDR
512 MB
NAND-Flash
Figure 1 :
Feb 2010 Datasheet
Top View
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Micro-SD
card reader
J1 Board to Board
connector
J2 Board to Board
connector
Figure 2 :
Bottom View
2.3 Reference Number
MAGiK-MX board is exists in two versions, one commercial and one industrial:
 MAGiK-MX-I30 for Industrial grade
 MAGiK-MX-C30 for commercial grade
Feb 2010 Datasheet
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3 Specification
3.1 Absolute Maximum rating
Power Supply Vcc
Max Current Icc
Temperature (For Industrial Grade)
Temperature (For Commercial Grade)
Table 1 :
Min.
2.5V (TBC)
Typ.
5V (TBC)
-40°C
0°C
Max.
6V (TBC)
800 mA (TBC)
+85°C
+70°C
Processor Board Absolute Maximum Rating
3.2 Physical Dimensions
8 mm
50 mm
90 mm
Figure 3 :
Processor Board Physical Dimensions (TBC)
3.3 RoHS Compliancy
MAGiK-MX is RoHS compliant
Feb 2010 Datasheet
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4 MAGiK-MX System Module features
4.1 MAGiK-MX Block Diagram
1V8
Power
Management
Unit
3V3
I2C4 for control
Power
5V
USB0, USB1, USB2
J1 180 Points connector
UART1, UART3
GPMC Bus (Memory)
DSS (Video OUT)
BSP1, BSP2 (I2S)
OMAP
3530
I2C1, I2C2, I2C3, I2C4
SPI1
Camera I/F
JTAG
MMC1, MMC2 (SDIO Bus)
Micro SD
Card Reader
Figure 4 :
Feb 2010 Datasheet
SDRC Bus
J2 180 Points connector
Keypad I/F
Mobile DDR
128 MB
Mobile DDR
128 MB
GPMC Bus
MAC/PHY
Controller
Eth
NOR Flash
64 MB
NAND Flash
512 MB
MAGiK-MX Block Diagram
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4.2 Features
4.2.1 Processor OMAP 3530
OMAP3530 Applications Processor includes the following features:
 OMAP™ 3 Architecture
 MPU Subsystem
o 600-MHz ARM Cortex™-A8 Core
o NEON™ SIMD Coprocessor
 High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
o 430-MHz TMS320C64x+™ DSP Core (EDMA) Controller (128 Independent Channels)
o Video Hardware Accelerators
 POWERVR SGX™ 2D/3D Graphics Accelerator
o Tile Based Architecture Delivering up to 10 MPoly/sec
o Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and
Vertex Shader Functionality
o Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
o Fine Grained Task Switching, Load Balancing, and Power Management
o Programmable High Quality Image Anti-Aliasing
 Fully Software-Compatible With C64x and ARM9™
For more information: http://focus.ti.com/docs/prod/folders/print/omap3530.html
Depending on the Temperature range of the Processor Board (Industrial or Commercial), here are the
references of OMAP3530:
 OMAP3530DCUSA (Industrial grade)
 OMAP3530DCUS (Commercial Grade)
4.2.2 Power Management Unit
Power Management is fully handled by the Processor Board. The 1V8 and 3V3 are also output of
Processor Board for any others purpose through J1 connector.
Power Management is based on TPS65023 and can be controlled by OMAP processor or BTB
connector through an I2C link
Processor Board is supporting different Power modes described in chapter: 5) MAGiK-MX System
Module board to board connector.
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4.2.3 Micro SD Card Reader
A Micro SD Card connector is available on Processor Board. Micro SD Card reader has following
specification:
 The micro SD card size is 2Gbytes.
 The micro SD card connector is interfaced to SDC1 port of OMAP3530.
 The vdds_mmc1 of OMAP3530 operates in 3.0V mode.
4.2.4 Mobile DDR
Two Mobile DDR memories of 128 MB each are used on the board. The SDRC dedicated memory bus
is used to link each 16 bits width memory
For more information, mobile DDR part number is H5MS1G62MFP-K3M
4.2.5 Nand Flash
One 512 MB Nand Flash is directly connected to GPMC bus (nCS3 Chip Select used)
For more information, Nand Flash part number is MT29F4G08ABCHC.
4.2.6 Nor Flash
One 64 MB Nor Flash is directly connected to GPMC bus (nCS0 Chip Select used)
For more information, Nor Flash part number is S29GL01GP11FFIV10.
4.2.7 MAC/PHY Controller
One MAC/PHY Controller is directly connected to GPMC bus (nCS4 Chip Select used). MAC/PHY
Controller is 10/100 Ethernet controller.
For more information, MAC Controller part number is LAN9221.
Note: MAC PROM is also provided on the Processor Board
4.2.8 LED
No.
1 Power On LED
2 Function LED
LED Name
LED glow when board POWERON (Directly connected to PMU)
LED glow for functional testing (OMAP IO142)
Table 2 :
Feb 2010 Datasheet
Functionality
Red
Green
LEDs function on MAGiK-MX
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4.3 External Interfaces
All the external interfaces are available on J1 and J2 connector. Chapter 5) MAGiK-MX System
Module board to board connector described the pinout of this two connectors.
4.3.1 Power Output
Power Output is delivering 1.8V and 3.3V. The table below gives the power available for each voltage
in worst case
Voltage
1.8V DC
3.3V DC
Table 3 :
Maximum available current
500 mA (TBC)
500 mA (TBC)
Current Available for Voltage output
Power output is shown in table below:
Signal
VCC_1.8V
VCC_3.3V
VCC_1.8V_ANA
Direction
O
O
O
Description
1.8V DC Output
3.3V DC Output
1.8V Voltage analog reference (Used for Video DAC of OMAP)
Table 4 :
Power Output description
4.3.2 Power Input
Power Input is shown in table below:
Signal
VCC_5V
VCC_5V_JACK
VCC_BATT
Direction
I
I
I
Description
5V DC Input (800 mA Max)
5V Monitoring from 5V Main Power
Voltage monitoring for Battery voltage input
Table 5 :
Power Input description
4.3.3 USB I/F (1V8 Level)
Three USB port can be directly used:
 USB port 0
 USB port 1
 USB port 2
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USB I/F is ULPI standard as shown in table below:
Signal
USB0_CLK
USB0_D[7..0]
Direction
I
IO
USB0_DIR
I
USB0_STP
USB0_NXT
USB1_CLK
USB1_D[7..0]
USB1_DIR
O
I
I
IO
I
USB1_STP
USB1_NXT
USB2_CLK
USB2_D[7..0]
USB2_DIR
O
I
I
IO
I
USB2_STP
USB2_NXT
O
I
Description
60 MHz ref. clock input
8 Bit bi-directional data bus
Controls the direction of the data bus:
- When DIR = 0 => USB_D[7..0] is an OUTPUT
- When DIR = 1 => USB_D[7..0] is an INPUT
STP assertion for one clock cycle to stop the data strean on the bus
NXT indicates current byte sent has been accepted by the PHY
60 MHz ref. clock input
8 Bit bi-directional data bus
Controls the direction of the data bus:
- When DIR = 0 => USB_D[7..0] is an OUTPUT
- When DIR = 1 => USB_D[7..0] is an INPUT
STP assertion for one clock cycle to stop the data strean on the bus
NXT indicates current byte sent has been accepted by the PHY
60 MHz ref. clock input
8 Bit bi-directional data bus
Controls the direction of the data bus:
- When DIR = 0 => USB_D[7..0] is an OUTPUT
- When DIR = 1 => USB_D[7..0] is an INPUT
STP assertion for one clock cycle to stop the data strean on the bus
NXT indicates current byte sent has been accepted by the PHY
Table 6 :
USB ULPI I/O description
USB ports are configurable:
 One port can be used on Hi-Speed OTG
 One port can be used on Hi-Speed
 One port can be used on Full Speed
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4.3.4 UART I/F (1V8Level)
Two UART port can be used:
 UART port 1 is a general purpose UART without CTS/RTS control
 UART port 3 is the dedicated Boot/Debug UART with CTS/RTS control
UART I/F is shown in table below:
Signal
UART1_TX_IO148
UART1_RX_IO151
UART3_TX_IO166
UART3_RX_IO165
UART3_CTS_IO163
UART3_RTS_IO164
Direction
O
I
O
O
I
O
Description
UART1 Transmit Data (Note the IO can be used as GPIO)
UART1 Receive Data (Note the IO can be used as GPIO)
UART3 Transmit Data (Note the IO can be used as GPIO)
UART3 Receive Data (Note the IO can be used as GPIO)
UART3 Clear To Send (Note the IO can be used as GPIO)
UART3 Request To Send (Note the IO can be used as GPIO)
Table 7 :
UART I/O description
4.3.5 I2S I/F (1V8 Level)
I2S interface is done with OMAP McBSP port. Two ports of OMAP can be used:
 Port 1: McBSP LP 1: can manage input and output I2S link
 Port 2: McBSP LP 2: can manage input or output I2S link
I2S I/F is shown in table below:
Signal
BSP_CLKS
BSP1_CLKX
BSP1_FSX
BSP1_DX
BSP1_CLKR
BSP1_FSR
BSP1_DR
BSP2_CLK
BSP2_FS
BSP2_DX
BSP2_DR
Direction
I
IO
IO
IO
IO
IO
I
IO
IO
IO
IO
Description
External clock input (Shared by McBSP1 and 2)
Transmit clock (Equivalent to I2S SCK)
Transmit frame synchronization (Equivalent to I2S WS)
Transmitted serial data (Equivalent to I2S SD)
Receive Clock (Equivalent to I2S SCK)
Receive frame synchronization (Equivalent to I2S WS)
Received serial data (Equivalent to I2S SD)
Transmit clock (Equivalent to I2S SCK)
Transmit frame synchronization (Equivalent to I2S WS)
Transmitted serial data (Equivalent to I2S SD)
Receive serial data (Equivalent to I2S SD)
Table 8 :
Feb 2010 Datasheet
I2S I/O description
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4.3.6 I2C I/F (1V8 Level)
Four ports of I2C can be used:
 I2C1 for Port1
 I2C2 for Port2
 I2C3 for Port3
 I2C4 for Port4
I2C I/F is shown in table below:
Signal
Direction
I2C1_SCL_IO168
IOD
I2C1_SDA_IO183
IOD
I2C2_SCL
I2C2_SDA
I2C3_SCL
I2C3_SDA
IOD
IOD
IOD
IOD
I2C4_SCL_IO184
IOD
I2C4_SDA_IO185
IOD
Description
I2C port 1 Master Serial clock. Output is open drain (Note the IO can
be used as GPIO)
I2C port 1 Serial Bidirectional Data. Output is open drain (Note the IO
can be used as GPIO)
I2C port 2 Master Serial clock. Output is open drain
I2C port 2 Serial Bidirectional Data. Output is open drain
I2C port 3 Master Serial clock. Output is open drain
I2C port 3 Serial Bidirectional Data. Output is open drain
I2C port 4 Master Serial clock. Output is open drain (Note the IO can
be used as GPIO)
I2C port 4 Serial Bidirectional Data. Output is open drain (Note the IO
can be used as GPIO)
Table 9 :
I2C I/O description
Note: Port 4 is also controlling Power Management Unit
4.3.7 Camera I/F (1V8 Level)
One camera input port is available to receive Digital Video Input. Camera I/F is shown in table below:
Signal
CAM_HS
CAM_VS
CAM_PCLK
CAM_CLKA
CAM_CLKB
CAM_FLD
CAM_WE
CAM_STRO
CAM_GRST
CAM_SHU
CAM_D[11..0]
Direction
IO
IO
I
O
O
IO
I
O
IO
O
I
Table 10 :
Feb 2010 Datasheet
Description
Camera Horizontal Synchronisation
Camera Vertical Synchronization
Camera pixel clock
Camera Clock Output a
Camera Clock Output b
Camera field identification
Camera Write Enable
Flash strobe control signal
Global reset is used strobe synchronization
Mechanical shutter control signal
Camera digital image data bits
Camera I/O description
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4.3.8 JTAG I/F (1V8 Level)
JTAG is used to configure the OMAP as well as for emulation and debugging purpose.
JTAG I/F is shown in table below:
Signal
JTAG_NTRST
JTAG_TCK
JTAG_RTCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_EMU0
JTAG_EMU1
Direction
I
I
O
IO
I
O
IO
IO
Table 11 :
Description
Test Reset (TP6)
Test Clock (TP9)
ARM Clock Emulation (TP10)
Test Mode Select (TP7)
Test Data Input (TP8)
Test Data Output (TP5)
Test emulation 0 (TP3)
Test emulation 1 (TP4)
JTAG I/O description
Note: JTAG I/Os are also available on Test points on OMAP-MX Processor Board (TPxx in signal
description)
4.3.9 Ethernet I/F (Ethernet STD Level)
Ethernet I/F is 10/100 Ethernet speed interface. This I/F can be directly connected to a Magnetic and
RJ45
Ethernet I/F is shown in table below:
Signal
ETH_TPO_P
ETH_TPO_N
ETH_TPI_P
ETH_TPI_N
ETH_LED1
ETH_LED2
ETH_LED3
Direction
O
O
I
I
O
O
O
Table 12 :
Feb 2010 Datasheet
Description
Ethernet Output Positive Differential Line
Ethernet Output Negative Differential Line
Ethernet Input Positive Differential Line
Ethernet Input Negative Differential Line
Ethernet Output LED1
Ethernet Output LED2
Ethernet Output LED3
Ethernet I/O description
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4.3.10 GPMC Memory I/F (1V8 Level)
Global Purpose Memory Interface allows to connect up to 3 different interfaces on the GPMC bus (3
GPMC_CS).
GPMC Memory I/F is shown in table below:
Signal
GPMC_NCS4
GPMC_NCS5
GPMC_NCS6
GPMC_NCS7
GPMC_CLK
GPMC_NWP
GPMC_NWE
GPMC_NOE
GPMC_NADV_ALE
GPMC_CLE
GPMC_WAIT0
GPMC_D[15..0]
GPMC_A[25..0]
Direction
O
O
O
O
O
O
O
O
O
O
I
IO
O
Table 13 :
Description
GPMC Chip Select bit 4
GPMC Chip Select bit 4
GPMC Chip Select bit 6
GPMC Chip Select bit 7
GPMC clock
Flash Write Protect
Write Enable
Output Enable
Address Valid or Address Latch Enable
Command Latch Enable
External indication of wait (TBD Wait 0, 1, 2 or 3)
GPMC Data bits
General-purpose memory address
GPMC Memory I/O description
GPMC_NADV_ALE
GPMC_D[15..0]
Latch
GPMC_A[15..0]
BTB
Connector 2
OMAP3530
GPMC_A[9..0]
Figure 5 :
GPMC_A[25..16]
GPMC Address Management conform to TI recommendation
Note: GPMC_A[15..0] and GPMC_D[15..0] are multiplexed then signal GPMC_NADV_ALE must be
used to validate Address
Feb 2010 Datasheet
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4.3.11 DSS Video Out I/F (1V8 Level)
DSS Video Out I/F is the digital video output of OMAP 3530.
DSS Video Out I/F is shown in table below:
Signal
DSS_PCLK
DSS_HSYNC
DSS_VSYNC
DSS_ACBIAS
DSS_DATA[23..0]
Direction
O
O
O
O
I/O
Description
LCD Pixel Clock
LCD Horizontal Synchronization
LCD Vertical Synchronization
AC bias control (STN) or pixel data enable (TFT) output
LCD Pixel Data bits
Table 14 :
SS I/O Description
4.3.12 SPI I/F (1V8 Level)
One SPI port I/F is available. SPI I/F is described in table below:
Signal
MCSPI1_CLK
MCSPI1_SIMO
MCSPI1_SMI
MCSPI1_CSO
Direction
IO
IO
IO
IO
Description
SPI Clock
Slave data in, master data out
Slave data out, master data in
SPI Enable 0, polarity configured by software
Table 15 :
SPI I/O Description
4.3.13 MMC2 SDIO I/F (1V8 Level)
MMC SDIO I/F port2 is described in table below:
Signal
MMC2_CLK
MMC2_CMD
MMC2_D[3..0]
MMC2_CD_IO140
MMC2_WP_IO141
Direction
O
IO
IO
IO
IO
Table 16 :
Feb 2010 Datasheet
Description
MMC/SD Output Clock
MMC/SD command signal
MMC/SD Card Data bits
SD Card Detect
SD Write Protect
SDIO I/O Description
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4.3.14 GPIO I/F (1V8 Level)
19 GPIOs can be used; SMe of the IOs are GPIO only SMe others are multiplexed with others IOs.
GPIOs are described in table below:
Signal
UART1_TX_IO148
UART1_RX_IO151
UART3_TX_IO166
UART3_RX_IO165
UART3_CTS_IO163
UART3_RTS_IO164
I2C1_SCL_IO168
I2C1_SDA_IO183
I2C4_SCL_IO184
I2C4_SDA_IO185
IO143
IO159
IO138
MMC2_CD_IO140
MMC2_WP_IO141
IO126
IO127
IO128
IO129
Direction
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Table 17 :
Description
GPIO148 (Multiplex with UART)
GPIO151 (Multiplex with UART)
GPIO166 (Multiplex with UART)
GPIO165 (Multiplex with UART)
GPIO163 (Multiplex with UART)
GPIO164 (Multiplex with UART)
GPIO168 (Multiplex with I2C)
GPIO183 (Multiplex with I2C)
GPIO184 (Multiplex with I2C)
GPIO185 (Multiplex with I2C)
GPIO143
GPIO159
GPIO139
GPIO140 (Multiplex with MMC2)
GPIO141 (Multiplex with MMC2)
GPIO126
GPIO127
GPIO128
GPIO129
GPIOs I/O Description
Note: GPIOs can be used also for external interrupt
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4.3.15 TVOUT I/F (Analog Output)
Others I/F are described in table below:
TVOUT1
TVOUT2
Analog O
Analog O
TV analog output Composite : TV Out 1
TV analog output Composite : TV Out 2
Table 18 :
TVout I/O Description
4.3.16 OTHERS I/F
Others I/F are described in table below:
Signal
HDQ_SIO
BOARD_RSTN_STATUS
OMAP_RSTN_STATUS
BOARD_RSTN
CLKOUT1
CLKOUT2
Direction
IOD
IOD
IOD
I
O
O
Table 19 :
Feb 2010 Datasheet
Description
Single Wire Interface (1V8 level)
Reset status of the board (1V8 logic level)
Reset Status of OMAP Processor (1V8 logic level)
Processor Board Reset Input (5V level)
Configurable output clock1 (1V8 level)
Configurable output clock2 (1V8 level)
Others I/O Description
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5 MAGiK-MX System Module board to board connector
5.1 Board to Board Connector1: J1
MAGiK MX
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
btb1_nc1
btb1_nc2
btb1_nc3
btb1_nc4
btb1_nc5
GND
ETH_TPO_N
ETH_TPO_P
btb1_nc6
ETH_TPI_N
ETH_TPI_P
GND
btb1_nc7
btb1_nc8
GND
USB2_D1
USB2_D3
USB2_D5
USB2_D7
USB2_CLK
USB2_NXT
GND
USB1_D1
USB1_D3
USB1_D5
USB1_D7
USB1_CLK
USB1_NXT
GND
btb1_nc9
btb1_nc10
btb1_nc11
btb1_nc12
btb1_nc13
btb1_nc14
GND
UART3_CTS_IO163
UART3_RTS_IO164
UART3_CTS_IO163
UART3_RTS_IO164
Feb 2010 Datasheet
PIN NUMBER
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
MAGiK MX
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
btb1_nc46
btb1_nc22
btb1_nc23
btb1_nc24
btb1_nc25
GND
ETH_LED1 ( speed )
ETH_LED2 ( Link & Activity )
ETH_LED3 ( Full duplex )
btb1_nc26
btb1_nc27
GND
btb1_nc28
btb1_nc29
GND
USB2_D0
USB2_D2
USB2_D4
USB2_D6
USB2_STP
USB2_DIR
GND
USB1_D0
USB1_D2
USB1_D4
USB1_D6
USB1_STP
USB1_DIR
GND
btb1_nc30
btb1_nc31
btb1_nc32
btb1_nc33
btb1_nc34
btb1_nc35
GND
UART3_RX_IO165
UART3_TX_IO166
UART1_RX_IO151
UART1_TX_IO148
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UART3_CTS_IO163
UART3_RTS_IO164
GND
CAM_HS
CAM_VS
CAM_PCLK
CAM_CLKA
CAM_CLKB
CAM_FLD
CAM_GRST
CAM_SHU
CAM_WE
CAM_STRO
CAM_D11
GND
BSP1_CLKX
BSP1_DX
BSP1_DR
BSP1_FSX
BSP1_FSR
BSP1_CLKR
GND
btb1_nc15
btb1_nc16
btb1_nc17
btb1_nc18
btb1_nc19
I2C1_SCL_IO168
I2C1_SDA_IO183
GND
I2C3_SCL_IO
I2C3_SDA_IO
I2C2_SCL_IO
I2C2_SDA_IO
IO_143
IO_150
OMAP_RSTN_STATUS
btb1_nc20
GND
JTAG_NTRST
JTAG_TMS
JTAG_TCK
JTAG_TDI
btb1_nc21
GND
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
Table 20 :
Feb 2010 Datasheet
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
UART1_RX_IO151
UART1_TX_IO148
GND
CAM_D0
CAM_D1
CAM_D2
CAM_D3
CAM_D4
CAM_D5
CAM_D6
CAM_D7
CAM_D8
CAM_D9
CAM_D10
GND
BSP2_CLK
BSP2_DX
BSP2_DR
BSP2_FS
BSP_CLKS
btb1_nc36
GND
btb1_nc37
btb1_nc38
btb1_nc39
btb1_nc40
hdq_sio
I2C1_SCL_IO168
I2C1_SDA_IO183
GND
I2C4_SCL_IO184
I2C4_SDA_IO185
btb1_nc41
PULL UP 3.3V
btb1_nc42
btb1_nc43
btb1_nc44
IO139
GND
JTAG_TDO
JTAG_RTCK
JTAG_EMU0
JTAG_EMU1
btb1_nc45
GND
Board to Board Connector 2: J1
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5.2 Board to Board Connector2: J2
MAGiK-MX
VCC_5V
VCC_5V
VCC_5V
VCC_5V
btb2_nc1
GND
btb2_nc2
VCC_5V_JACK
VCC_BATT
btb2_nc3
btb2_nc4
MMC2_CMD
MMC2_D0
MMC2_CLK
MMC2_CD_IO140
btb2_nc5
btb2_nc6
GND
CLKOUT2
IO128
IO129
btb2_nc7
btb2_nc8
btb2_nc9
btb2_nc10
GND
GPMC_NCS4
btb2_nc11
GPMC_CLK
GPMC_NWP
btb2_nc12
btb2_nc13
GPMC_WAIT0
GPMC_NCS6
btb_nc14
GND
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
GPMC_D5
GPMC_D6
GPMC_D7
GND
GPMC_D8
GPMC_D9
GPMC_D10
Feb 2010 Datasheet
PIN NUMBER
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
MAGiK-MX
VCC_5V
VCC_5V
VCC_5V
VCC_5V
btb2_nc19
GND
btb2_nc20
VCC_5V_JACK
VCC_BATT
VCC_1.8V_ANA
MMC2_D2
MMC2_D3
MMC2_D1
MMC2_WP_IO141
BOARD_RSTN_STATUS
btb2_nc21
BOARD_RSTN
GND
CLKOUT1
IO126
IO127
btb2_nc22
btb2_nc23
btb2_nc24
btb2_nc25
GND
GPMC_NCS7
btb2_nc26
GPMC_NWE
GPMC_NOE
GPMC_NADV_ALE
GPMC_CLE
btb2_nc27
GPMC_NCS5
btb2_nc28
GND
GPMC_A0
GPMC_A1
GPMC_A2
GPMC_A3
GPMC_A4
GPMC_A5
GPMC_A6
GPMC_A7
GND
GPMC_A8
GPMC_A9
GPMC_A10
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GPMC_D11
GPMC_D12
GPMC_D13
GPMC_D14
GPMC_D15
GND
GPMC_A16
GPMC_A17
GPMC_A18
GPMC_A19
GPMC_A24
USB0_D1
USB0_D3
USB0_D5
USB0_D7
USB0_CLK
USB0_NXT
GND
TVOUT1
btb2_nc15
btb2_nc16
DSS_ACBIAS
DSS_D16
DSS_VSYNC
DSS_D7
btb2_nc17
DSS_D3
DSS_D0
GND
DSS_D5
DSS_D19
DSS_D20
DSS_D21
DSS_D6
DSS_D1
DSS_D2
DSS_PCLK
DSS_D4
SPI1_CS0
btb2_nc18
MCSPI1_CLK
GND
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
Table 21 :
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
GPMC_A11
GPMC_A12
GPMC_A13
GPMC_A14
GPMC_A15
GND
GPMC_A20
GPMC_A21
GPMC_A22
GPMC_A23
GPMC_A25
USB0_D0
USB0_D2
USB0_D4
USB0_D6
USB0_STP
USB0_DIR
GND
TVOUT2
btb2_nc29
DSS_D15
btb2_nc30
DSS_D17
DSS_HSYNC
DSS_D12
DSS_D13
DSS_D8
btb2_nc31
GND
DSS_D14
DSS_D18
DSS_D22
DSS_D23
DSS_D10
DSS_D9
DSS_D11
btb2_nc32
btb2_nc33
MCSPI1_SMI
MCSPI1_SIMO
btb2_nc34
GND
Board to Board Connector 2: J2
Note: Connector ref. for J1 and J2 is SAMTEC BTH-090-01-L-D-A
Feb 2010 Datasheet
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6 Power Mode and Power Management
4 Power Mode are available for Power Management of System Module:
Power Mode
Normal Mode
Eco Mode
Standby Mode
Description
Full Power Mode: ARM=650 MHz, DSP=430 MHz
Eco Mode: ARM=125 MHz, DSP=90 MHz
All Logic and Memory are maintained Wake-up time is fast
Table 22 :
Feb 2010 Datasheet
Power
4W (TBC)
1W (TBC)
7 mW (TBC)
MAGiK-MX Processor Board Power Mode
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7 MAGiK-MX System Module Memory Map
Memory Map Summary
Chip
Start
End Address
Select
Address
Component
0x4000 0000
0x4001 3FFF
0x4001 4000
0x4001 BFFF
0x4020 0000
0x4805 0000
0x4805 0400
0x4805 0800
0x4805 0C00
0x480B C000
0x4807 0000
0x4807 2000
0x4806 0000
0x4809 8000
0x4809 A000
0x480B 8000
0x480B
A000
0x4806 A000
0x4806 C000
0x4902 0000
0x480A
B000
0x4806 4000
0x4806 2000
0x4809 C000
0x480B 4000
0x480A
D000
0X0000 0000
0x4020 FFFF
0x4805 03FF
0x4805 07FF
0x4805 0BFF
0x4805 0FFF
0x480B FFFF
0x4807 0FFF
0x4807 2FFF
0x4806 0FFF
0x4809 8FFF
0x4809 AFFF
0x480B 8FFF
Size
Remark
(Byte)
On chip,
80K
secure
On chip,
32K
public
64K
Secure/public
1K
DSS top
1K
Controller
1K
RFBI
1K
Encoder
16K
4K
4K
4K
4K
4K
4K
0x480B AFFF
4K
0x4806 AFFF
0x4806 CFFF
0x4902 0FFF
4K
4K
4K
0x480A BFFF
4K
0x4806 4FFF
0x4806 2FFF
0x4809 CFFF
0x480B 4FFF
4K
4K
4K
4K
0x480A DFFF
4K
0X03FF FFFF
64M
0X8000 0000
0XA000
0000
0X83FF FFFF
0XA3FF
FFFF
64M
Boot ROM
SRAM internal
Display Subsystem (DSS)
Camera ISP
I2C
SPI
#1
#2
#3
#1
#2
#3
#4
UART
#1
#2
#3
HS USB OTG
HS USB HOST
USBTLL module
MMC/SD/SDIO1
MMC/SD/SDIO2
MMC/SD/SDIO3
NOR Flash
NAND Flash
Ethernet Controller
SDRC(DDR)
gpmc_cs0
gpmc_cs3
gpmc_cs4
gpmc_cs5
gpmc_cs6
gpmc_cs7
sdrc_nsc0
sdrc_nsc1
Table 23 :
Feb 2010 Datasheet
64M
MAGiK-MX Processor Board Memory Map
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8 MAGiK-MX System Module Boot configuration settings
BOOT[6:0] Input
0101111
0001111
0000110
0001110
0010101
0000111
BOOTING SEQUENCE
USB, UART, MMC1, NAND
NAND, USB, UART, MMC1
MMC1, USB
XIPWAIT, DOC, USB, UART, MMC1
NAND, UART
MMC1, USB
Table 24 :
MAGiK-MX Boot Sequence
Note: the required boot configuration settings can be made by retaining or removing the following
resistors on Processor Board.
Figure 6 :
Resistor configuration for boot mode
END OF DOCUMENT
Feb 2010 Datasheet
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