8. Data Conversion Methods I
8.1 Introduction
The process of converting a digital binary input code into an output
analogue voltage is known as Digital-to-Analogue Conversion. This will
be treated first as it is normally used within the converse process of
Analogue-to-Digital Conversion. It involves reproducing a quantised
analogue voltage level from an input binary code.
Ideally the output voltage should have a one–to-one relationship with
the input binary code. That is, there should be one particular value of
output voltage for each binary code and this should correspond exactly
to the quantisation level. However, in practise there is an error in
generating the output voltage and this means that it can be a little
above or below the intended quantisation level. Normally the error is
maintained to within ±½ of a quantisation level. The Transfer
Characteristic for the digital-to-analogue conversion process shown in
Fig. 8.2 illustrates this.
The Ideal Current Source:
An ideal current source as shown in Fig. 8.1 is one which generates a
fixed stable value of current which does not vary with changes in the
load it feeds.
VR
SW
IS
Fig. 8.1
RS
ideal
current
source
RL
VL
The Ideal Current Source Driving a Load
When the switch is closed the value of the current is always IS
regardless of the value of the load resistance, RL, or the series
resistance, RS. This means that the voltage developed across the load
resistance is:
VL  IS R L
The voltage developed across the load resistance, RL, is dependent on
the value of RL itself and the current IS. It does not depend on the
series resistance, RS.
1
VREF
Input
Binary
Code
b2
b1
b0
Digital to
Analogue
Converter
Output
Analogue
Voltage
Code
V0 \ VREF
(VFS) 7/8
6/8
5/8
4/8
3/8
2/8
1/8
0
000 001 010 011 100 101 110 111 b2b1b0
Input Binary Code
Fig. 8.2 The Digital-to-Analogue Converter and
Transfer Characteristic
I
2
n
p
u
t
V
o
Kirchhoff’s Current Law:
This law states that the sum of currents at a node is zero. This is
essentially the principle of conservation of charge, which can neither
be created from nothing nor destroyed into oblivion.
Phrased in a more useful way it states that the sum of currents flowing
into a node is equal to the sum of the currents flowing out of the same
node.
This is illustrated in Fig. 8.3 where:
I1  I2  I3  I4  I5
I1
I2
I4
I3
node
I5
Fig. 8.3
An Illustration of Kirchhoff’s Current Law
This means that current sources can be added in parallel so that the
total current flowing in the load is the sum of the individual currents.
VL  ILRL  (I1  I2  I3 )RL
IL
I1
I2
Fig. 8.4
I3
RL
Current Sources Connected in Parallel
3
VL
8.2 Current Source-Based Digital-to-Analogue Converter:
A simplified schematic diagram of an 8-bit digital-to-analogue
converter using weighted current sources is shown in Fig. 8.5. It can
be seen that there is one switch and one current source associated
with each bit in the converter. All of the current sources are connected
in parallel and act in the same direction so that they all add to provide
a total current in the load, RL. From Kirchhoff’s Law it can be said that:
VO  (I7  I6  I5  I4  I3  I2  I1  I0 )RL
However, this only applies when all of the switches are closed. In
order to allow for full binary switching a value ‘b’ is assigned to each
switch in the bank. The switches are controlled by the value of the
digital input byte given as:
DN  (b7b6b5b4b3b2b1b0 )
If b = 0 the switch is OPEN and no current flows in that branch
If b = 1 the switch is CLOSED and a current equal to the value of the
associated current source flows in that branch.
Then an input digital code b7b6b5b4b3b2b1b0 = 01010011 means that:
switches b7 , b5 , b3 , b2 are OPEN
and b6 , b4 , b1 , b0 are CLOSED.
The individual current
progression so that:
are
sources
also
weighted
in
I7  2I6 , I6  2 I5................I2  2 I1 , I1  2I0
or
I7  2I6  4I5  8I4  16I 3  32 I2  64I1  128I 0
4
a
binary
I0 = IREF/256
b0
I1 = IREF/128
b1
I2 = IREF/64
b2
I3 = IREF/32
b3
IL
buffer
amplifier
I4 = IREF/16
b4
VO
RL
I5 = IREF/8
VL
b5
I6 = IREF/4
b6
Fig 8.5 An 8-bit
Digital-to-Analogue Converter
using Binary weighted current
sources
I7 = IREF/2
b7
5
Then including the switching coefficients as multipliers gives:
VO  (b7I7  b6I6  b5I5  b4I4  b3I3  b2I2  b1I1  b0I0 )RL
If a reference current is chosen such that the current in the branch
which represents the least significant bit LSB is:
ILSB  I0 
IREF
 IQ a current quantisati on step
2N
Then:
IL  b7
IREF
I
I
I
I
I
I
I
 b6 REF
 b5 REF
 b4 REF
 b3 REF
 b2 REF
 b1 REF
 b0 REF
1
2
3
4
5
6
7
2
2
2
2
2
2
2
28
Then with IREF = 2NIQ substituting gives:
IL  b7
2N IQ
21
 b6
2N IQ
22
 b5
2N IQ
23
 b4
2N IQ
24
 b3
2N IQ
25
 b2
2N IQ
26
 b1
2N IQ
27
 b0
2N IQ
With N = 8 in this case:
IL  IQ[b727  b6 26  b525  b4 24  b323  b2 22  b121  b0 20 ]
Then finally with VO = ILRL and IQ = IREF/2N:
VO 
IREF
R L [b7 27  b6 26  b5 25  b4 2 4  b3 23  b2 22  b1 21  b0 20 ]
N
2
If IREFRL = VREF then:
VO 
VREF
[b7 27  b6 26  b5 25  b4 2 4  b3 23  b2 22  b1 21  b0 20 ]
N
2
This can be written as:
VO 
VREF N1
VREF
j
Σ
b
2

DN
j

0
j
2N
2N
where DN is the value of the binary digital input.
If N = 8 and b7b6b5b4b3b2b1b0 = 01010011 then
D = 26+24+21+20 = 64+16+2+1 = 83 so that VO = (83/256)VREF.
6
28
8.3 The Flash Analogue-to-Digital Converter
The process of converting an analogue signal into a digital binary code
is known as Analogue-to-Digital Conversion. It involves sampling the
input signal, quantising the sample to the nearest quantisation level
and then encoding this level into binary coded form.
The sampled input analogue signal is essentially quantised to the
nearest level which means that there can be an error of + ½ of a
quantisation level between the actual input voltage and the quantised
voltage which is encoded. The Transfer Characteristic for the
analogue-to-digital conversion process shown in Fig. 8.6 illustrates
this.
The Flash converter is the fastest type of ADC but is only used for low
numbers of bits, rarely exceeding N = 8. This is because it uses a large
amount of circuitry or hardware and therefore occupies a large amount
of Silicon area when integrated on chip.
The Ideal Comparator:
A comparator, as shown in Fig. 8.7, is a device which simply compares
the voltages at two inputs and gives an output logic level that
indicates which of the inputs is more positive than the other. In the
context of its use in an ADC one of the inputs will have a reference
voltage which can be considered fixed.
The rule for the comparator is straight forward. If the signal or voltage
present at the positive input is more positive than that at the negative
input then the output of the comparator is at the HI logic level or
binary ‘1’. If the senses of the voltages are the other way round then
the output of the comparator will be LO or binary ‘0’.
7
Input
Analogue
Signal
b2
b1
b0
Analogue
to Digital
Converter
Output
Binary
Code
Output
Binary
Code
b2b1b0
111
110
101
100
011
010
001
000
Fig. 8.6
0
1/8
2/8
3/8 4/8
5/8
6/8 7/8
VFS
Vin / VREF
Input
Voltage
Analogue-to-Digital Converter and Transfer Characteristic
8
+
_
output
logic
level
Vin
VREF
V
Vin
VREF
t
output
HI
LO
t
Fig. 8.7 The Ideal Comparator and its Operation
9
A simplified schematic diagram of an 8-bit Flash Analogue-to-Digital
Converter (ADC) is shown in Fig 8.3. A number of reference voltages
equal to the number of quantization levels are generated using a
resistor chain. These are fed into a series of comparators along with
the input voltage, so that the input voltage is essentially compared
with all of the different reference levels simultaneously. The
comparator outputs corresponding to all of the levels which the input
voltage exceeds go high. The highest of these is the level which
actually corresponds most closely to the input voltage. Digital
encoding logic is then used to convert this bar-chart type of
comparator output code into a conventional binary code.
Table 8.1 below shows the ranges occupied by the input signal, the
corresponding comparator output states and the associated final
output binary codes.
This type of converter is very fast as only the propagation delay of a
single comparator and the encoding logic is involved. However, it
requires a number of comparators equal to the number of levels, i.e.
256 for an 8-bit ADC. It is generally only used for really high speed
video applications and the number of bits rarely exceeds 8.
Table 8.1
Conversion of Comparator Output States into Binary Code
input voltage condition
comparator outputs
output bits
Q6
Q5
Q4
Q3
Q2
Q1
Q0
b2
b1
b0
0 < Vi < VQ/2
0
0
0
0
0
0
0
0
0
0
VQ / 2 < Vi < 3 VQ / 2
0
0
0
0
0
0
1
0
0
1
3VQ / 2 < Vi < 5 VQ / 2
0
0
0
0
0
1
1
0
1
0
5VQ / 2 < Vi < 7 VQ / 2
0
0
0
0
1
1
1
0
1
1
7VQ / 2 < Vi < 9 VQ / 2
0
0
0
1
1
1
1
1
0
0
9VQ / 2 < Vi < 11 VQ / 2
0
0
1
1
1
1
1
1
0
1
11VQ / 2 < Vi < 13VQ / 2
0
1
1
1
1
1
1
1
1
0
13VQ / 2 < Vi < VREF
1
1
1
1
1
1
1
1
1
1
10
VREF
comparator
R/2
+
13VQ/2
-
R
+
11VQ/2
-
R
+
binary
output
code
b2
9VQ/2
-
R
+
encoding
b1
7VQ/2
-
R
+
logic
b0
5VQ/2
-
R
+
3VQ/2
-
R
+
VQ/2
-
R/2
timing and
control
S/H
Vin
Fig. 8.3 An 8-bit Flash
Analogue-to-Digital Converter
using Resistors and Comparators
11