2007Fall
CS 147 Midterm 3 Study Guide
Nov. 27, Tuesday, 2007
Material Cover in the exam.
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Decoder and multiplexor.
Sequential logic.
ISA
Memory
You should know:
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Memory Hierarchy order
Locality of reference - what it is, why it is important, types and what they
mean
 spatial locality
 temporal locality
Cache: why do we use it?
Cache: Write policies - be able to name, describe, and compare, including
advantages and disadvantages
 write-back
 write-through
Cache: Mapping Types - be able to name, describe, compare, including
advantages and disadvantages.
 direct
 fully-associative
 set-associative
Cache: Address breakdown - know how the address is split up to represent
tag, block, and word in each mapping type.
Cache: How to measure performance - know the formulas for average
access time for one to three caches and how to apply them to compare
cache performance.
Cache: Understand how to trace through a list of cache loads, determining
which ones result in hits, and what happens when there is a miss.
Virtual Memory: why use it?
Virtual Memory: what is a working set? Why it is important?
Virtual Memory: what is the MMU, what does it do?
Virtual Memory: understand pages and page frames
Virtual Memory: understand TLB and why we use it
Virtual Memory: understand thrashing
Both: Replacement Algorithms - be able to name, describe and compare
 random
 least recently used
The most important contribution to the development of modern memory management is
the introduction of virtual memory in the Demand Paging scheme. The key memory
management schemes we talked about are as follows, with associated advantages and
disadvantages:
Memory Scheme
Advantages
Disadvantages
Single User Contiguous
one
Simple to implement
One user, only
active
process
Partitions
fragmentation
Multiple jobs supported
Internal
Sysop had to
guess
size of
program
Dynamic Partitions
fragmentation
No internal fragmentation
External
Partitions
Overhead
No internal fragmentation
Compaction
Demand Paging
and
Job size not limited to
OS overhead
Relocatable Dynamic
memory size
some
internal fragmentation
No need for compaction
Thrashing
Locality of reference
Potential for
possible
Segmented
external
limits swapping
external
fragmentation
Segmented/Demand
implement,
Minimizes swapping, no
external fragmentation
Complicated to
requires
hardware and software
support

 RISC and CISC
Comparision
 Pipelining
o
What is pipelining?
Sample Problems.
1. ) Given the following input and clock waveforms:
5V
CLK
0V
5V
J
0V
5V
K
Q
M/S
Q
Pedge
Q
Nedge
0V
5V
0V
5V
0V
5V
0V
Draw the waveforms of the Q output of a J-K device if:
(a)
(b)
It is a positive edge triggered flip flop.
It is a negative edge triggered flip flop.
Assume that the Q output initially is low.
2. Design the following finite state machine.
The FSM takes two continuous streams of unsigned 4-bit numbers A and B in a
serial fashion with the most significant bit first. The least significant bit is marked
by the presence of a 1 on the control line C. When C is asserted, the output Z
should become 1 if the 4-bit number A is larger than B, otherwise Z remains 0.
The following bit stream illustrates the operation of the FSM:
A (A3 A2 A1 A0): 1 0 1 1 1 0 1 0 0 1 1 1 . . .
B (B3 B2 B1 B0): 0 1 1 1 1 1 0 0 0 1 1 0 . . .
C:
0 0 0 1 0 0 0 1 0 0 0 1 . . .
Z (OUTPUT) :
0 0 0 1 0 0 0 0 0 0 0 1 . . .
Draw the state diagram for the FSM, assuming that you implement it as a Mealy
machine. Label the transitions with the inputs A, B, C (in this sequence) and give
them the values 0, 1 or X. Only the minimized state diagram will get full credit
(there is no need to apply the state minimization methods).
Solution:
State Diagram:
Alternative solution needs an additional state (reset state):
3. Design a 2-bit counter that counts in the following fashion depending on the status of
two control signals A and B:
A
B
Function
0
0
Stop counting (hold the count)
0
1
Counts up by 1
1
0
Counts down by 1
1
1
Gray code up counter
Draw the state diagram. Indicate in each state the binary value of the counter (00,
01, etc
Solution: . a
b.
Binary up counter : 00  01  10  11  00 ...
Binary down counter : 00  11  10  01  00 ...
Gray up counter : 00  01  11  10  00 ...
4. A sequential circuit has one flip-flop Q of type D; two inputs x and y; and one
output S. It consists of a full-adder circuit connected to the D flip-flop, as shown
below. Derive the state table and state diagram of the sequential circuit.
5. Suppose a 32-bit byte-addressable CPU accesses memory in the following order:
17433, 17435, 17443, 17448, 17451, 17438, 17439, 17459. Assume that we have 4 cache
blocks. Initially the cache is empty. (1 word = 4 bytes)
(1) If the cache is direct-mapped, show the final contents of the cache with memory block
number. Assume 1 block is 1 word. (Ignore the tag field and other bits.) What is the total
number of misses?
(2) If the cache is 2-way set associative with LRU replacement policy, show the final
contents of the cache with memory block number. Assume 1 block is 2 words. (Ignore
the tag field and other bits.) What is the total number of misses?
(3) If the cache is fully-associative with FIFO replacement policy, show the final contents
of the cache with memory block number. Assume 1 block is 1 word. (Ignore the tag field
and other bits.) What is the total number of misses?
6.
7.
8. Assume that you have free memory partitions of size 100KB, 500KB, 200KB, 300KB,
and 600KB (in this order) and that memory requests for 212KB, 417KB, 112KB, and
426KB arrive.
a)Show how a First-Fit allocation algorithm would assign the requests to free memory.
(Do NOT assume rotating First-Fit). Clearly show the size of each piece of memory after
each request arrives.
b)Show how a Best-Fit allocation algorithm would assign the same requests. Clearly
show the size of each piece of memory after each request arrives.
c)Show how a Worst-Fit allocation algorithm would assign the same requests. Clearly
show the size of each piece of memory after each request arrives.
9. What is the difference between first-fit and best-fit, in the context of dynamic memory
management?
10. What is the compaction, in the context of dynamic memory management?
11. Explain the difference between a page and a frame.
12. Why can use cache of cache speed up program excutions?
Answer:
13.The input signals D and C for the circuit below are plotted against time below. Q is
initially 0. Plot the output Q.
Answer:
14.Explain the term : direct map in cache.
15. The rectangle in the circuit below is a D-type flip-flop. Its input signals D and
C are plotted against time below. Q is initially 0. Plot the output Q
16. Suppose we have the following address sequence is required for a
program: 2,3,5,2,3,4,2,3,5,2,3,5,4,2,4,5,6,3,2,1. The cache is 3 blocks
with LRU placement policy. What is the hit ratio?
17.
18. A logic function has a min-term list presentation F(X,Y,Z,W) =m(0,2,6,7,8,14).
Implement F using a 4 to 16 decoder and a NAND-gate.
19. True or False
“The limit for dynamic memory allocation can be as large as the amount of
available physical memory in the computer or the amount of available disk space
in a virtual-memory system.”
20.
Write the output
S2 S1 S0
Output
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
21. Multiple choice
(1) Which page replacement suffers from Belady anomaly?
a. Least Recently Used
b. FIFO
c.
Second Chance
d. None of the above
Answer:
(2) Which one of these groups are in proper smallest to largest in memory order?
(a) RAM | L2 Cache | L1 Cache
(c) L1 Cache | L2 Cache | RAM
(b) L2 Cache | RAM | L1 Cache
(d) L2 Cache | L1 Cache | RAM
Answer:
4. (3 points) Given five memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and 600 KB (in
order of increasing starting memory address for each partition), how would each of first-fit and
best-fit algorithms
place processes of sizes 212 KB, 417 KB, 112 KB and 426 KB (in order of arrival)?
Answer:
Process
212
417
112
426
First Fit
Best Fit
3