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Silicon on Insulator
Alan Joch
December 18, 2000 (Computerworld) -- Remember those childhood treats known as pigs in a blanket?
There's a new chip-fabrication technology you might think of as a "chip in a blanket."
Silicon-on-insulator (SOI) chips are made with a layer of silicon dioxide insulation that separates
individual transistors from the underlying silicon wafer. In conventional CMOS chips, transistors sit in
direct contact with the wafer. SOI's hair-thin blanket of silicon dioxide helps keep electrons flowing
efficiently from one transistor gate to another without letting stray electrons leak out into the substrate.
The result is a microprocessor in which electrons get to their destinations faster. These chips provide
better processing performance; and SOI-based computers use less power because there's no waste due to
leaked electrons.
SOI Comes to Market
IBM began shipping the first commercial servers using SOI microprocessors last summer, bringing to
market a power-saving technology that had for years been tried in research labs but until recently had no
commercial demand.
The additional manufacturing steps needed to produce SOI chips have until recently priced the
technology out of an intensely competitive market. But now, thanks to the requirements of high-end
applications like e-business computing, some performance junkies are willing to pay price premiums of
perhaps 25% for chips that outrun conventional CMOS processors.
According to IBM, head-to-head comparisons of equivalent SOI and CMOS chips show that SOI chips
have a speed advantage of 20% to 30% and consume half or one-third the power of CMOS chips.
Although the SOI chip production process involves more steps than production of CMOS chips, existing
chip fabrication facilities don't require major overhauls to accommodate SOI. Once the silicon dioxide
film is spread across the wafer surface, the process of placing the transistors on top of the insulating layer
uses the same lithography and tools as CMOS chip fabrication. Thus, SOI fabrication is an evolutionary
step in chip fabrication, says Joel Tendler, director of Power4 technical assessment at IBM's Austin,
Texas, facility. "We need to use these 'tricks' to keep Moore's Law alive," he adds.
No other chip maker—including notable forces like Intel Corp. and Sun Microsystems Inc.—has
announced plans for production of SOI processors as enthusiastically as IBM announced its plans.
Earlier this year, IBM began shipping high-end p680 servers with the new chips, and it plans to offer an
SOI-based model in its AS/400 line by year's end. These initial SOI systems support high-end
applications like e-business and Web servers, transaction processors and data-mining hardware. Next
year, IBM plans to introduce Power4 systems with the new chips and later will use SOI processors for
portable devices that require power efficiency.
Intel continues to push performance using CMOS technology, achieving speeds of 2 GHz, notes Steve
Leibson, chief analyst at Sunnyvale, Calif.-based MicroDesign Resources and editor in chief of the firm's
"Microprocessor Report" newsletter. Whether SOI will become commercially viable for any company
other than a diversified technology giant like IBM is still unclear, he adds.
"[IBM] needs a manufacturing process for high-end mainframe chips [and] the Power4 line," says
Leibson. "In order to offer better versions of those machines, they have to push the technology. Then they
can look at the merchant semiconductor market. It will take a while for SOI to drift down to business PCs
because . . . we now have enough megahertz for things like Microsoft Office. [Business users] won't need
SOI until multimedia becomes commonplace."
Joch is a freelance writer in Francestown, N.H.
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SOI Chip
In this cross-section of an SOI chip, a hair-thin layer of silicon dioxide is used between
thansistors and the water substrate to more efficiently channel electrons.
CMOS Chip
Conventional CMOS chips without the insulating silicon dioxide layer require more time and
electrical power to compensate for electron inefficiency.
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http://en.wikipedia.org/wiki/Silicon_on_insulator
Silicon on insulator
From Wikipedia, the free encyclopedia
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in
place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to
reduce parasitic device capacitance and thereby improve performance. [1] SOI-based devices differ from
conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically
silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended
application, with sapphire being used for radiation-sensitive applications and silicon dioxide preferred for
improved performance and diminished short channel effects in microelectronics devices [2]. The insulating
layer and topmost silicon layer also vary widely with application. The first implementation of SOI was
announced by IBM in August 1998.[3]
Contents
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1 Industry need
2 Manufacture of SOI wafers
3 Use in the microelectronics industry
4 See also
5 References
6 External links
Industry need
The implementation of SOI technology is one of several manufacturing strategies employed to allow the
continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law.
Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:

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Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at
matched performance.
Resistance to latchup due to complete isolation of the n- and p- well structures.
From a manufacturing perspective, SOI substrates are compatible with most conventional fab processes.
In general, an SOI-based process may be implemented without special equipment or significant retooling
of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for
the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary
barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 15% increase to total manufacturing costs.[4]
Manufacture of SOI wafers
SiO2-based SOI wafers can be produced by several methods:
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SIMOX - Separation by IMplantation of OXygen - uses an oxygen ion beam implantation process followed
by high temperature annealing to create a buried SiO2 layer.[5][6][7]
Wafer Bonding[8] [9] - the insulating layer is formed by directly bonding oxidized silicon with a second
substrate. The majority of the second substrate is subsequently removed, the remnants forming the
topmost Si layer.
3
o

One prominent example of a wafer bonding process is the Smart Cut method developed by the
French firm Soitec which uses ion implantation followed by controlled exfoliation to determine
the thickness of the uppermost silicon layer.
o NanoCleave is a technology developed by Silicon Genesis Corporation that separates the silicon
via stress at the interface of silicon and silicon-germanium alloy.[10]
o ELTRAN is a technology developed by Canon which is based on porous silicon and water cut.[11]
Seed methods[12] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require
some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator,
an appropriately oriented crystalline insulator, or vias through the insulator from the underlying
substrate.
An exhaustive review of these various manufacturing processes may be found in reference
[1]
Use in the microelectronics industry
IBM began to use SOI in high end RS64-IV Istar PowerPC processors in 2000. Other examples of
microprocessors built on SOI technology include AMD's 130 nm, 90 nm and 65 nm single, dual and quad
core processors since 2001.[13] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently
Freescale is shipping SOI products in 180nm, 130nm, 90nm and 65nm lines. [14] The 90 nm Power
Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well.
Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors,
are built using conventional bulk CMOS technology. Intel's new 45 nm process will continue to use
conventional technology. However, Intel made a claim of single-chip silicon laser based on SOI.[15]
On the foundry side, TSMC claimed no customer wanted SOI.[16] But Chartered Semiconductor devoted a
whole fab to SOI.[17]
See also


Intel TeraHertz Similar technology from Intel.
Wafer (electronics)
References
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17.
^ a b Celler, G.K., Cristoloveanu, S. J App Phys, 93, 4955 (2003)
^ SOI design: analog, memory and digital techniques by Andrew Marshall & Sreedhar Natarajan
^ IBM Advances Chip Technology With Breakthrough For Making Faster, More Efficient Semiconductors
^ IBM touts chipmaking technology
^ http://www.google.com/patents?vid=5888297
^ http://www.google.com/patents?vid=USPAT5061642
^ SIMOX-SOI Technology: Ibis Technology
^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience,
1998, ISBN 978-0471574811
^ http://www.google.com/patents?vid=4771016
^ http://www.sigen.com/
^ JSAPI_vol.4
^ http://www.google.com/patents?q=5417180&btnG=Search+Patents
^ Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed
^ Process Technology
^ http://www.eetasia.com/ART_8800359617_499481,499482.HTM
^ TSMC has no customer demand for SOI technology - Fabtech - The online information source for
semiconductor professionals
^ CHARTERED EXPANDS FOUNDRY MARKET ACCESS TO IBM's 90nm SOI TECHNOLOGY
External links
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AMDboard - a site with extensive information regarding SOI technology
4
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Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec.
MIGAS'04 - The 7th session of MIGAS International Summer School on Advanced Microelectronics,
devoted to SOI technology and devices.
Retrieved from "http://en.wikipedia.org/wiki/Silicon_on_insulator"
Categories: Semiconductors | Semiconductor technology | Micro
SIMOX process
Smart Cut process
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