University of Arizona
Department of Electrical and Computer Engineering
ECE 351A: Electronic Circuits
Fall 2011
Catalog Data: Operational amplifiers, diode circuits, circuit characteristics of
bipolar and MOS transistors, MOS and bipolar digital circuits, and simulation software.
Prerequisite: ECE 220; Co-requisites: ECE 301, ECE 320.
The purpose of ECE 351A is to get experience with the fundamental nonlinear devices
for circuit design: diodes and transistors. We'll learn how to analyze simple linear
amplifier circuits with these devices, how to use small signal models, and spend a
relatively small amount of time on how to build digital logic gates. More complex linear
amplifier circuits are left for ECE 304.
Time and place: 10:00-10:50AM on Mondays, Wednesdays and Fridays in
Saguaro Hall 101. Mondays either 3 or 4pm problem session.
Textbook: Microelectronic Circuits, by Adel S. Sedra and Kenneth C. Smith (6th
edition), Oxford University Press, 2010.
Instructor: Elmer Grubbs, Room ECE356R, grubbs@ece.arizona.edu.
Office hours: 1:00 to 1:50 M W TH F or by appointment
Course objectives: The objective of this course is to give students the ability to
design and analyze simple circuits involving diodes and transistors both analytically (by
hand) to meet given specifications and to verify and evaluate such designs using a
computer simulation program, such as PSPICE. Specifically, after this course a student
should be able to:
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Design and analyze simple circuits involving diodes, such as clippers and
rectifiers;
Design and analyze simple linear amplifier circuits using MOS transistors;
Design and analyze simple linear amplifier circuits using bipolar junction
transistors;
Design and analyze simple logic circuits using either BJTs or MOSFETs.
Homework: Homework will generally be assigned weekly on Wednesdays, due the
following week in class. Most homework will have 5 problems each, and will be graded
on a 10-point scale. For each problem, one point will be awarded for trying every part of
the problem. At least 3/4 point will be awarded for showing your understanding of every
part of the problem, even if you get the numerical answers wrong. Homework will be
returned in class, and if not picked up at that time can be picked up in office hours during
the term. No credit will be given for homework turned in after solutions are released.
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Since some homework will involve PSPICE simulations, please familiarize
yourself with this software package, available in several computer labs of the
ECE building.
While you can very likely find homework solutions somewhere on the web, it is not very
smart to copy them onto your homework. Remember that the homework problems are
your only real preparation for the quizzes and exams, which will be original. It is in your
best interest to work your way through them, so the test will make sense! All homework
grading issues must be discussed with the instructor prior to the return of the following
homework.
Quizzes and Final Exam: There will be three closed-book, one sheet of notes
quizzes during the term, in addition to a comprehensive final exam. The purpose of these
quizzes is to let you know how well you are really understanding the material as we go
through the class. However, most of the weight falls on the final exam. Calculators (but
not pocket computers) will be allowed.
Quiz, and exam grading will focus on understanding, rather than on numerical answers;
thus using an incorrect model for a transistor will cost you more points (in general) than a
miscalculation that leads to a wrong numerical answer. All quiz grading issues must be
discussed with the instructor within one week of the class receiving back the graded
exam.
Grading: A final numerical grade will be calculated for each student at the end of the
course as follows:
Grade
composition:
Percentage of
class credit
Quiz 1
25%
Quiz 2
25%
Quiz 3
25%
Weekly HW
15%
Final
examination
35%
The lowest score on these three quizzes will be
dropped for the purposes of the final grade.
The course final letter grade will be assigned on a curve. Initially, the grading scheme
will be:
A 90% +
B 80%+ C 70%+ D 60%+ E <60%
Philosophy: This course will follow Sedra & Smith closely, but my role is not to
read it to you. I strongly encourage you to read the appropriate sections in advance so
you can ask questions in class as I go over the material. I don't insist that you attend my
lectures (since they largely follow the book), but you are responsible for the material I
cover there, even if I do diverge from the book (which I sometimes do to explain
something better).
Schedule of topics: Please note that this schedule is somewhat fluid. This
schedule is in four parts, separated by three quizzes.
Month
August
Day Topic
22 Introduction, course objectives
Book Section
Chapter 1.1-6, 2.1-5
24
Introduction to diodes
4.1-2
26
Analysis of diode circuits
4.3.1-6
29
Small-signal diode model
4.3.7
31
Small-signal diode model, cont'd
4.3.7
Zener diodes, rectifier Circuits
4.4.1,4.5.1-4
September 2
5
No Class (Labor Day)
7
Limiting and clamping circuits
4.6
9
Physical operation
3.1-3
12 Open-circuit and reverse-bias conditions
3.4
14 Open-circuit and reverse-bias conditions
3.5
16 Breakdown and forward-bias cond's; special diodes 4.7.1-4
19 Quiz 1 review
21 Quiz One
23 NPN transistor
6.1.1-4
26 PNP transistor; circuit symbols; graphical analysis 6.1.5,6.2.1-3
October
28 DC analysis
6.3
20 Saturation; Biasing the BJT
6.7,6.8
3
Transistors as amplifiers
6.4
5
NO CLASS
7
Small-signal models
6.5
10
Amplifiers; single-stage BJT amplifier configurations
6.6
November
December
12
BJT amplifier configurations (cont'd)
6.6
14
Quiz 2 review
17
Quiz Two
19
MOSFET basics
5.1.1-4
21
MOSFET basics, cont'd
5.1.5-9
24
Current-voltage characteristics
5.2
26
No Class
28
No Class
31
DC analysis
5.3
2
Biasing MOSFET amplifiers
5.4,5.7
4
MOSFET small-signal models
5.5
7
Recipes / MOSFET amplifier configurations
5.6
9
Amplifier configurations, cont'd
5.8
11
NO CLASS (Veterans Day)
14
Amplifier configurations, cont'd
16
Quiz 3 review
18
Quiz Three
21
Basics of Digital Logic
13.1
23
CMOS inverter
13.2
25
No Class (Thanksgiving)
28
CMOS logic gates
13.4
30
Pass-transistor logic
14.2
2
ECL (Emitter-coupled logic)
14.4
5
Final exam review
7
Question and answer / problem session
5.8
Final exam: Wednesday, Dec 14, 10:30AM-12:30, Saguaro Hall 101.
General rules:
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Be advised of the University's Code of Academic Integrity.
Late homework will be subject to a penalty unless proper documentation of illness or
emergency is provided. Late homework will be penalized 20% per day (or any portion
thereof).
No make-up examinations will be given. If any examination (excepting the final) is
missed with proper documentation or illness or emergency, that grade will be dropped,
and count as your dropped quiz. Any further missed examinations get zero credit.