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SCHOOL OF ENGINEERING
HIGHER NATIONAL DIPLOMA AND CERTIFICATE IN ELECTRONICS
SECOND YEAR
2006/2007
ANALOGUE AND DIGITAL PRINCIPLES
HNH66
Examiner: M. S. Ball

The total number of questions is FOURTEEN
 Marks for each question are indicated

Attempt ALL EIGHT questions in SECTION A
 The time allowed is THREE hours
This section carries 40% of the total marks.

Attempt THREE questions in SECTION B
This section carries 60% of the total marks

You may use a calculator but pre-programmed calculators are not permitted

Where appropriate, clear freehand diagrams are acceptable

Before you start, make sure you have all the items listed as ‘Special Requirements’ below.
Special Requirements:

Answer book with printed Supplement.

Paper clip to enable Supplement to be attached to answer book.

Formula Sheet
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SECTION A (Q1 to Q8)
Attempt all questions in this section for 40% of the marks.
1.
Figure Q1 shows an 8  loudspeaker coupled to the output of a power amplifier via a
d.c. blocking capacitor. Assume the amplifier has negligible output resistance and a
voltage gain is 50.
(a)
If Vin is 150 mV, calculate the mid-band power delivered to the load.
(b)
Calculate the capacitor value required to allow frequencies down to 20 Hz to
be effectively reproduced by the loudspeaker.
C
PA
Vin
8
LS
Figure Q1
5 marks.
2.
(a)
Identify the general features of a programmable logic device (PLD).
(b)
State three possible advantages associated with the use of programmable logic
devices to implement a medium-scale logic design.
5 marks
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3.
Figure Q3 shows the circuit of a basic series voltage regulator.
(a)
Calculate the output voltage Vout.
(b)
Calculate the power dissipation of the series transistor TR1
4 marks.
Heatsink
TR1
TIP31
Vin = 10V
Vout
R2
470R
R4
2k0
R1
1k0
R5
2k0
R3
470R
C1
100n
7
+
C3
100n
-
C4
47u
RL
20
U1
3
6
2
4 1 5
D1
LED
UA741
+
-
C2
470u
R6
3k0
D2 ZENER
3V0
R7
3k0
0V
0V
Figure Q3
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4.
A TDA2050 integrated power amplifier is delivering a continuous 20 W of power to a
load. The device is mounted on a heatsink and the specification is that, for this output
power, the device case temperature is to be no higher than 60C in an ambient
temperature of 25 C. Assuming that the efficiency of the TDA2050 is 50% under
these conditions, and given that the junction-to-case thermal resistance of the
TDA2030 is 3 C/W, and the case-to-heatsink thermal resistance is negligible
calculate:
(a)
the thermal resistance of a suitable heatsink,
(b)
the junction temperature of the TDA2050.
6 marks.
5.
Figure Q5 shows the Karnaugh map of a 5-variable combinational logic function.
Interpret the map and write down the simplified sum-of-products logic equation for
the function represented.
4 marks
 To save you time, these maps are reproduced on page 1 of the supplement to
your answer book. Use them when answering this question. Print your name on
the supplement and hand it in with your answer book.
BA
DC
BA
00
01
11
10
00
01
11
10
00
1
1
0
0
00
1
1
0
0
01
1
1
0
0
01
1
1
1
0
11
0
1
0
0
11
0
1
1
0
10
1
1
1
1
10
1
1
1
1
DC
E=0
E=1
Figure Q5
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6.
Figure Q5 shows a twin-T notch filter.
(a)
Calculate the notch frequency.
(b)
Sketch the graph of
Vout
Vin
against frequency for the filter
dB
4 marks.
C
C
159.2nF
159.2nF
+15V
7
R
1k
3
In
R
U1
+15V
1k
6
7
U2
3
6
Out
2
2
4 1 5
4 1 5
741
C1
741
R1
500R
318.4nF
-15V
-15V
GND
Figure Q6
7.
A 10 kHz, 707 mV sine-wave input is applied to the inverting amplifier shown in
figure Q7. Given that the maximum slew-rate of the operational amplifier is 0.5 V/s
and its other characteristics are ideal:
(a)
Decide, by making suitable calculations’ if the output waveform of the
amplifier will suffer from the effect of ‘slew-rate distortion’.
(b)
Calculate the highest frequency input signal that could be reproduced without
suffering the effect of slew-rate distortion.
5 marks
+18 V
8
3
Vin
1
R1
10k
2
4
R3
9k1
Vout
R2
150k
-18 V
GND
GND
Figure Q7
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8.
Figure Q8 shows a 4-bit digital-to-analogue converter based on an R, 2R resistor
ladder network.
Figure Q7
The digital input is in binary code and the logic levels, applied between pairs of
terminals ‘A’, ‘B’ etc., are defined as 2.5V  1 and 0V  0 .
(a)
State one practical advantage that the R, 2R ladder network has over the
alternative weighted resistor network for use in digital-to-anlogue converters.
(b)
Calculate the voltage present at the non-inverting input of the operational
amplifier if the binary input is 11002.
(c)
If R10 is 1k0, calculate the value of R9 to give an analogue output of 7.5 V
when the binary input is 11112.
5 marks
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SECTION B (Q9 to Q14)
Attempt three questions from this section for 60% of the marks
9.
Figure Q9 shows a high-pass filter assembled from cascaded identical high-pass
networks having 246.5s time constants.
VCC
VCC
VCC
U1:A
8
U1:B
C
3
IN
1
8
C
5
2
7
U2:A
3
6
1
OUT
2
4
VEE
4
VEE
R
R
VEE
GND
GND
Figure Q9
(a)
Identify the role that the operational amplifiers have in this circuit.
2 marks.
(b)
(i)
Derive an expression for the overall voltage transfer ratio
Vout
Vin
of the
dB
filter at any frequency.
6 marks.
(c)
(ii)
Calculate the dB attenuation of the filter at a frequency of 60 Hz.
3 marks.
(i)
Derive an equation for the cut-off (–3dB) frequency of the two-stage
filter.
7 marks.
Calculate the cut-off frequency of the filter.
2 marks.
(ii)
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10.
Refer to the precision half wave rectifier circuit shown in figure Q10.
R2
10k
D1
1N914
VCC (15V)
U2
7
D2
3
R1
In
6
Out
2
1N914
10k
4
1
8
LT1077CN8
R3
680 R
VEE (-15V)
GND
GND
Figure Q10
(a)
Explain the advantages of employing a rectifier of this type when compared to
a simple diode rectifier. Include a sketch of the transfer characteristics of a
simple diode rectifier and a precision rectifier.
3 marks.
(b)
If +2V d.c. is applied to the input, state the approximate voltages that would
occur at the following points:
(i)
Pin 2 of the op-amp.
(ii)
Pin 6 of the op-amp.
(iii)
The circuit output terminal.
6 marks.
(c)
If the input voltage is then changed to –100 mV d.c., estimate the voltages at
the following points:
(i)
Pin 6 of the op-amp.
(ii)
The circuit output terminal.
4 marks.
(d)
(e)
If the input to the circuit was changed to a 1 kHz, 2 Vpk-pk signal, sketch the
input and output waveforms on a common axis indicating significant time and
voltage values.
4 marks.
If a mean-sensing 3 V f.s.d. d.c. voltmeter were connected across the output of
the circuit, calculate the voltmeter reading when a 2Vrms, 100Hz signal is
applied to the circuit input.
3 marks.
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11.
(a)
Figure Q11A shows the VF against IF characteristic of a silicon diode. Given
that the equation of the graph is of the form I F  I 0 e kVF where I0 and k are
constants, show that ln I F  ln I 0  kVF .
2 marks.
(b)
Using data from figure Q11A, show that I0 ≈ 730pA and k ≈ 27.
8 marks.
I
P1
100A
100nA
P2
V
445 mV
185 mV
Figure Q11A
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(c)
If the silicon diode referred to in parts (a) and (b) is incorporated into the
operational amplifier circuit shown in figure Q11B, show that
1 I R
Vout  ln  0 
k  Vin 
4 marks.
D1
SI DIODE
U1
R
Vin
-Vout
100k
OPAMP
0V
0V
Figure Q11B
(d)
Calculate Vout for input voltages
(i)
Vin = 100mV
(ii)
Vin = 1V
(iii)
Vin = 10V
6 marks.
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12.
Figure Q12 shows a closed-loop series voltage regulator.
T1
SUITABLE HEAT SINK
TR1
TIP31A
1
R4
1
1R6
21 V d.c.
T3
V out
R1
470R
R6
10k
+
C3
100n
-
TR2
BC108
R2
470R
C1
100n
7
3
2
T2
R3
100R
U1
RV2
10k
6
415
+
-
C4
47u
UA741
C2
470u
D1
3V3
R7
10k
1
1
0V
T4
0V
Figure Q12
(a)
(b)
(c)
(d)
Identify the role played in the operation of the circuit by the following
components: (i)
C2
(ii)
TR2 (iii)
U1
3 marks.
Calculate the maximum and minimum output voltage of the circuit stating any
assumptions made.
4 marks.
If the base-emitter voltage VBE required to turn TR2 fully on is 800 mV,
calculate the maximum output current that the power supply can deliver
electrically.
2 marks.
Given that the ‘wing’ of TR1 is bolted onto the heat sink with an insulating
washer, that the circuit is operating in an ambient temperature of 30C, that
the output voltage is set to 9V and that the load resistor is 30 make use of the
information given in Table Q12 and:
(i)
(ii)
(iii)
(iv)
Draw the thermal circuit via which heat passes from the collector
junction of TR1 to the air
2 marks.
Estimate the collector junction power dissipation of TR1
3 marks.
Estimate the heat sink surface temperature
3 marks.
Estimate the collector junction temperature of TR1
3 marks.
TR1 junction-to-case thermal resistance
Heat sink washer thermal resistance
Heat sink-to-air thermal resistance
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3C/W
0.8C/W
8C/W
Table Q12
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Q13.
(a)
Figure Q13A shows the circuit diagram of a basic Wien Bridge oscillator.
(i)
State the attenuation and phase shift of the Wien network at the
frequency of oscillation.
2 marks.
(ii)
Briefly explain the purpose of the diodes D1 and D2 in the circuit?
2 marks.
(iii)
Calculate a value for resistor RV that would enable the frequency of
oscillation to be varied from approximately 150 Hz to 1.5 kHz.
4 marks.
(iv)
When the output of this oscillator was analysed with a spectrum
analyser the frequency components recorded in Table Q14 were
observed to be present. Use the data to calculate percentage total
harmonic distortion of the oscillator output waveform.
4 marks.
HARMONIC FREQUENCY FOURIER COMPONENT
NO
(HZ)
VOLTAGE (V)
1
1.000E+03
2.00E+00
2
2.000E+03
1.60E-02
Table Q14
3
3.000E+03
1.10E-02
4
4.000E+03
5.00E-03
5
5.000E+03
8.00E-03
J1
R1
2K2
+15V
RV
?
7
U1
J2
3
6
2
C1
47nF
OUTPUT
4 1 5
741
R2
10k
Ganged
R4
10k
R1
2K2
D1
1N4148
C1
RV
?
47nF
D2
1N4148
R3
10k
J3
0V
J4
-15V
Figure Q13A
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13.
(b)
Figure Q13B shows a 555 Timer IC configured as an astable multivibrator.
Use the given design equations to determine the values of RA and RB required
to generate an output frequency of 1 kHz with a 3:1 mark-to-space ratio.
8 marks.
VCC = +5V
RA
1
2
3
4
U1
GND
VCC
TRIG
DIS
OUT THLD
RST CNTL
8
7
RB
6
5
NE555
OUT
C1
CT
10nF
10nF
GND
t m  0.7CT ( RA  RB )
t s  0.7CT RB
and
tm
HIGH
space
mark
LOW
ts
Figure Q13B
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14.
The Logic Function Generator represented in figure Q14A is to be implemented by
programming a G16V8 PLD. An extract from the data sheet for this device is
reproduced in figure Q14B
X
Y
P
LOGIC
FUNCTION
GENERATOR
Q
A
R
G16V8 PLD
B
S
Figure Q14A
The logic function generator is designed to generate the truth table shown in Table
Q14.
Digital Control Code
X
Y
A
B
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Control Logic Outputs
P
Q
R
S
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
Table Q14

(a)
Page 2 of the answer book supplement contains a blank CUPL.PLD file
template.
In the extract from the PLD data sheet reproduced in Figure 14B, explain the
significance of the fact that pins are variously labelled as ‘I/CLK’, ‘I’,
‘I/O/Q’ and ‘ I/OE ’.
4 marks.
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(b)
Write a CUPL.PLD input file listing into the blank template on page 2 of the
answer book supplement. Fill the header section as appropriate, specify
suitable pin allocations and write a set of logic equation using CUPL’s logical
operators as follows:
#
OR
&
AND
!
NOT
$
EX-OR
11 marks.
(c)
When a design for this application was simulated using the WINSIM
simulation program the results shown in figure Q14C were obtained. Study
figure Q14C and identify any errors. When you discover an error, write down
the XYAB input code and state the corrected PQRS output code.
5 marks.
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Figure Q14B
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Figure Q14C
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