MM74HCA390 Dual 4-Bit Decade Counter/
MM74HCA393 Dual 4-Bit Binary Counter
General Description
These counter circuits contain independent ripple carry
counters and utilize advanced silicon-gate CMOS technology. The MM74HCA390 incorporates dual decade counters,
each composed of a divide-by-two and a divide-by-five
counter. The divide-by-two and divide-by-five counters can
be cascaded to form dual decade, dual bi-quinary, or various combinations up to a single divide-by-100 counter. The
MM74HCA393 contains two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by256 counter.
Each of the two 4-bit counters is incremented on the high to
low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all
four bits of each counter are set to a low level. This enables
count truncation and allows the implementation of divide-byN counter configurations.
Each of the counters outputs can drive 10 low power
Schottky TTL equivalent loads. These counters are func-
tionally as well as pin equivalent to the 74LS390/74LS393.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Typical operating frequency: 50 MHz
Typical propagation delay: 15 ns (Ck to QA)
Wide operating supply voltage range: 2 – 6V
Low input current: k1 mA
Low quiescent supply current: 40 mA maximum
(74HC Series)
Fanout of 10 LS-TTL loads
Low output noise generation
QOS specifications VOLV, VOLP
Identical pinout to HC
Speed upgrade of HC
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/10886 – 3
Top View
TL/F/10886 – 1
Top View
Order Number MM74HCA390
Order Number MM74HCA393
C1995 National Semiconductor Corporation
TL/F/10886
RRD-B30M105/Printed in U. S. A.
MM74HCA390 Dual 4-Bit Decade Counter/
MM74HCA393 Dual 4-Bit Binary Counter
October 1990
Absolute Maximum Ratings (Notes 1 & 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HCA
Min
2
Max
6
0
VCC
Units
V
V
b 40
a 85
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
74HCA
TA eb40 to 85§ C
TA e 25§ C
Typ
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
V
V
VIL
Maximum Low Level
Input Voltage
2.0V
3.0V
4.5V
6.0V
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
3.0V
4.5V
6.0V
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
1.9
2.9
4.4
5.9
V
V
V
V
3.0V
4.5V
6.0V
2.78
4.28
5.78
2.68
4.18
5.68
2.63
4.13
5.63
V
V
V
2.0V
3.0V
4.5V
6.0V
0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V
VIN e VIH or VIL
4.0 mA
lIOUTl s
lIOUTl s5.2 mA
3.0V
4.5V
6.0V
0.2
0.2
0.2
0.26
0.26
0.26
0.33
0.33
0.33
V
V
V
VIN e VIH or VIL
4.0 mA
lIOUTl s
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
4.0
40
mA
VOLP
Quiet Output
Maximum Dynamic VOL
Figures 1, 2
(Note 5)
5.5V
0.550
V
VOLV
Quiet Output
Maximum Dynamic VOL
Figures 1, 2
(Note 5)
5.5V
b 0.750
V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
Note 5: n e number of device outputs, n b 1 outputs switching, each driven 0V to 5.5V, one output
2
@
ground.
AC Electrical Characteristics MM74HCA390/MM74HCA393
VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Typ
Guaranteed Limit
Units
fMAX
Symbol
Maximum Operating Frequency
Parameter
Conditions
50
35
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock A to QA
13
20
ns
tPHL, tPLH
Maximum Propagation Delay, Clock A to QB
19
35
ns
tPHL, tPLH
Maximum Propagation Delay, Clock A to QC
23
42
ns
tPHL, tPLH
Maximum Propagation Delay, Clock A to QD
27
50
ns
tPHL
Maximum Propagation Delay, Clear to any Q
15
28
ns
tREM
Minimum Removal Time
b2
5
ns
tW
Minimum Pulse Width Clear or Clock
10
15
ns
AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
fMAX
Maximum Operating
Frequency
2.0V
3.3V
4.5V
6.0V
tPHL, tPLH
Maximum Propagation
Delay Clock A to QA
2.0V
3.3V
4.5V
6.0V
tPHL, tPLH
Maximum Propagation
Delay Clock A to QB
tPHL, tPLH
74HCA
TA eb40 to 85§ C
Units
Guaranteed Limits
6
22
32
38
5
18
27
32
MHz
MHz
MHz
45
23
15
13
120
36
24
20
150
45
30
26
ns
ns
ns
ns
2.0V
3.3V
4.5V
6.0V
68
35
23
20
180
54
36
31
225
68
45
38
ns
ns
ns
ns
Maximum Propagation
Delay Clock A to QC
2.0V
3.3V
4.5V
6.0V
90
45
30
26
220
66
44
37
275
83
55
47
ns
ns
ns
ns
tPHL, tPLH
Maximum Propagation Delay
Clock to QD
2.0V
3.3V
4.5V
6.0V
100
53
35
30
260
78
52
44
325
98
65
55
ns
ns
ns
ns
tPHL
Maximum Propagation
Delay Clear to any Q
2.0V
3.3V
4.5V
6.0V
54
27
18
15
150
45
30
26
190
57
38
33
ns
ns
ns
ns
tREM
Minimum Clear Removal
Time
2.0V
3.3V
4.5V
6.0V
25
8
5
5
30
9
6
5
ns
ns
ns
ns
tW
Minimum Pulse Width
Clear or Clock
2.0V
3.3V
4.5V
6.0V
30
15
10
9
75
75
15
13
95
95
19
16
ns
ns
ns
ns
tTHL, tTLH
Maximum Output Rise
and Fall Time
2.0V
3.3V
4.5V
6.0V
30
12
8
7
75
75
15
13
95
95
19
16
ns
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input Capacitance
(per counter)
42
pF
5
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
3
HCA Noise Characteristics
4. Set VCC to 5.0V.
5. Set the word generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measurement.
6. Set the word generator input levels at 0V LOW and 5.5V
HIGH for HCA devices. Verify levels with a digital volt
meter.
VOLP/VOLV and VOHP/VOHV:
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the noise
characteristics of HCA.
Equipment:
Word Generator
Printed Circuit Board Test Fixture
Dual Trace Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF, 500X.
2. Deskew the word generator so that no two channels have
greater than 150 ps skew between them. This requires
that the oscilloscope be deskewed first. Swap out the
channels that have more than 150 ps of skew until all
channels being used are within 150 ps. It is important to
deskew the word generator channels before testing. This
will ensure that the outputs switch simultaneously.
3. Terminate all inputs and outputs to ensure proper loading
of the outputs and that the input levels are at the correct
voltage.
# Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50X coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
# Measure VOLP and VOLV on the quiet output during the
HL transition. Measure VOHP and VOHV on the quiet output during the LH transition.
# Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
TL/F/10885 – 4
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note A. VOLV and VOLP are measured with respect to ground reference.
Note B. Input pulses have the following characteristics: f e 1 MHz, tr e 3 ns, tf e 3 ns, skew k 150 ps.
TL/F/10885 – 5
FIGURE 2. Simultaneous Switching Test Circuit
4
Logic Timing Waveforms
TL/F/10886 – 2
5
6
Physical Dimensions inches (millimeters)
Order Number MM74HCA393J
NS Package Number J14A
Order Number MM74HCA390J
NS Package Number J16A
7
MM74HCA390 Dual 4-Bit Decade Counter/
MM74HCA393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HCA393N
NS Package Number N14A
LIFE SUPPORT POLICY
Order Number MM74HCA390N
NS Package Number N16A
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