Boise State University
Department of Electrical and Computer Engineering
ECE 212L – Circuit Analysis and Design Lab
Experiment #4: Power Factor Correction
1
Objectives
The objectives of this laboratory experiment are:
• to calculate and measure complex power, observe lagging power factor, and correct lagging
power factor by adding capacitive compensation.
2
Theory
The apparent power or voltamperes (VA) in a given circuit is the product of the rms voltage and
rms current magnitudes. The real power (also referred to as average power or active power) is the
apparent power times the cosine of the angle between the voltage and the current waveforms or
phasors. This cosine term is known as the power factor, and it is desirable to operate at or near
unity power factor. This is the case since equipment costs are largely proportional to conductor size
and insulation, which are determined by the voltamperes required. Also, low power factor operation
implies high current with resulting small useful work. This is clear since a purely inductive load may
draw a large current and thus large voltamperes demand. The real power lost in the transmission
˜ 2 R losses are costly to utilities
or distribution line feeding this load could be substantial. These |I|
and large energy consumers. It is common to add capacitive reactance to an inductive circuit in
order to bring the voltage and current in phase (and thus bring the power factor to unity). This
practice is known as power factor correction. Clearly, power factor correction can reduce the cost of
electric power system operation and can permit generators to produce more active power at rated
kVA. In order to maintain a higher voltage at the load, and reduce line losses, the correction should
always be made at the load rather than the source.
PS + jQS
−
Z1 = R1 +jX1
+
jQ C
~
V1
+
−
jX C
R2
~
V2
jX 2
−
Figure 1: Capacitive Compensation at Load End
1
PL + jQL
Without the shunt capacitor in dotted lines and in parallel with the load, the source must supply
both real power PL and reactive power QL to the load, thus resulting in high current, high voltage
drop and high losses in the transmission line. When the capacitor is added as shown, the capacitor
supplies reactive power to the load and thus relieves the source and line of this unnecessary load.
As a load, a capacitor has zero power factor leading, thus making its reactive power consumption
negative (i.e., it generates reactive power). If the capacitors were shunted at point 1 instead of
point 2, the compensation would still relieve the source of the unnecessary reactive power QL of
the load, but the line would still carry the full PL + jQL , thus still causing substantial voltage drop
and line losses.
The convention used for leading and lagging power factor is standard. When computing the power
factor of a load (assuming load notation with the current entering the + terminal), the power factor
is lagging if 0o < ϕ < 180o (i.e. current lags voltage), and leading if −180o < ϕ < 0o (i.e.
current leads voltage). Note that for passive RLC loads, −90o ≤ ϕ ≤ 90o .
3
Equipment
• LTspice IV
4
Procedure
~
I1
R1
~
I2
jX 1
+
R2
~
V1
+
jX C
−
~
V2
jX 2
−
Figure 2: AC Study Circuit
1. Build
√ the AC circuit shown in Figure 2 using a 60-Hz, 120-Vrms source (peak voltage of
120 2 or 169.7 volts) delivering real and reactive power to a series RL-load with values
R2 = 100 Ω and L2 = 265 mH through a transmission line with values R1 = 10 Ω and
L1 = 26.5 mH. Assume initially that there is no shunt capacitor. (In the LTspice circuit,
use a value C = 0.001 µF to represent a nearly perfect open circuit.)
2
2. Simulate your circuit with the following parameters:
SINE Voltage Source (right click on voltage icon):
DC offset[V]: 0
Amplitude[V]: 169.7
Frequency[Hz]: 60
Simulation Command (under ”Simulate” menu):
Stop Time: 100 ms
Time to Start Saving Data: 50 ms
Maximum Timestep: 0.01 ms
Choosing a small time step will give you smoother sine waveforms. Place two voltage markers:
One at the top of the voltage source and the other at the top of the R2 -L2 load. Run your
simulation. In the output plot, right-click on the top label of a waveform of interest and
activate two sets of cursors by choosing the option “Attached Cursor: 1st & 2nd.” Measure
the following:
• peak-to-peak source voltage V1,pp (V).
• peak-to-peak load voltage V2,pp (V).
3. Remove the voltage markers and place two current markers: One through R1 or L1 and the
other through R2 or L2 . Measure the following:
• peak-to-peak source current I1,pp (A).
• peak-to-peak load current I2,pp (A).
4. Repeat Steps 2-3 with increasing values of C from 5 µF to 50 µF in steps of 5 µF. Tabulate
your results as shown below.
C (µF)
0
5
10
15
20
25
30
35
40
45
50
V1,pp (V)
V2,pp (V)
3
I1,pp (A)
I2,pp (A)
5
Data Analysis and Interpretation
1. Fill out the table below with the following quantities using the following equations:
√
(a) The rms source voltage magnitude V1 = V1,pp /2 2.
√
(b) The rms source current magnitude I1 = I1,pp /2 2.
(c) The apparent power S1 = V1 I1 delivered by the source.
√
(d) The rms load voltage magnitude V2 = V2,pp /2 2.
√
(e) The rms load current magnitude I2 = I2,pp /2 2 in the RL part of the load.
(f) The apparent power S2 = V2 I1 absorbed by the RLC load.
C (µF)
0
5
10
15
20
25
30
35
40
45
50
V1 (V)
I1 (A)
S1 (VA)
V2 (V)
I2 (A)
S2 (VA)
2. Fill out the table below with the following quantities using the following equations:
(a) The real power absorbed by the RLC load P2 = R2 I22 .
(b) The reactive power absorbed by the load Q2 = X2 I22 + V22 /XC = ωLI22 − ωCV22 .
(c) The power factor pf2 = cos ϕ2 = R2 I22 /V2 I1 of the RLC load and specify whether it
is lagging or leading using the sign of Q2 .
(d) The power factor angle ϕ2 = cos−1 (pf2 ) of the RLC load.
(e) The real power P1 = R1 I12 + P2 delivered by the source.
(f) The reactive power Q1 = X1 I12 + Q2 = ωL1 I12 + Q2 delivered by the source.
C (µF)
0
5
10
15
20
25
30
35
40
45
50
P2 (W)
Q2 (VAr)
pf2 (lag/lead)
4
ϕ2 (deg)
P1 (W)
Q1 (VAr)
3. Comment on the effect of the capacitive compensation on the source apparent power S1 (VA),
the line current magnitude I1 (A), the load voltage magnitude V2 (V), and the load power
factor pf2 .
4. Plot V2 (Vrms) as a function of C (µF). By interpolation, find the value of C that makes
V2 = 120 Vrms (same as the source voltage). Assuming that V1 < 120 < V2 are the two
points closest to V = 120 (V), use the following interpolation formula
V2 − 120
C2 − C
=
V2 − V1
C2 − C1
and solve for C (µF).
5. Fill out the table below with the following quantities using the following equations:
√
√
(a) The rms voltage drop Vline = I1 R12 + X12 = I1 R12 + (ωL1 )2 across the line.
(b) The real power losses Pline = R1 I12 in the transmission line.
(c) The reactive power losses Qline = X1 I12 = ωL1 I12 in the transmission line.
C (µF)
0
5
10
15
20
25
30
35
40
45
50
Vline (V)
Pline (W)
Qline (VAr)
6. Comment of the effect of the capacitive compensation on the line voltage drop Vline , the real
power losses Pline in the line, and the reactive power losses Qline in the line.
7. Plot Pline (W) as a function of C (µF). Find the optimum value Cmin that yields the lowest
losses in the line. To do this, fit a parabola Pline = αC 2 − βC + γ through the three points
closest to the minimum, solve for α, β, and γ, and find Cmin = β/(2α).
5
Boise State University
Department of Electrical and Computer Engineering
ECE 212L – Circuit Analysis and Design Lab
Experiment #4: Power Factor Correction
Date:
Data Sheet
Recorded by:
C (µF)
0
5
10
15
20
25
30
35
40
45
50
V1,pp (V)
V2,pp (V)
I1,pp (A)
I2,pp (A)