8.4.2 Implementation of Page Table
Implementation of Page Table
„ The two memory access problem can be solved by
„ Page table is kept in main memory
„ Page-table base register (PTBR) points to the page
table
„ Page-table length register (PRLR) indicates size of
the page table
„ In this scheme every data/instruction access requires
two memory accesses. One for the page table and one
for the data/instruction.
the use of a special fast-lookup hardware cache
called associative (組合) memory or translation
look-aside buffers (TLBs)
„ Some TLB allow certain entries to be wired down,
meaning that they cannot be removed from the TLB.
„ Typically TLB entries for kernel code are wired down.
„ Some TLBs store address-space identifiers (ASIDs)
in each TLB entry – uniquely identifies each process
to provide address-space protection for that process
„ Typically, the number of entries in a TLB is small,
often between 64 and 1024
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8.1
Operating System Principles
Operating System Principles
Associative Memory
8.2
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Paging Hardware With TLB
„ Associative memory – parallel search
Page #
Frame #
Address translation (p, d)
z
If p is in associative register, get frame # out
z
Otherwise get frame # from page table in memory
Operating System Principles
8.3
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Operating System Principles
8.4
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Effective Access Time Example
Memory Protection
„ Memory protection implemented by associating protection
„ Associative Lookup = 20 nanoseconds
„ Assume memory cycle time is 100 nanoseconds
„ Hit ratio – percentage of times (次數) that a page
number is found in the associative registers; ratio
related to number of associative registers
bits with each frame.
z
For example, one bit can define a page to be read-write or
read-only.
z
The approach could be expanded to a finer level of
protection
„ Let Hit ratio = α
„ Valid-invalid bit attached to each entry in the page table:
„ Effective Access Time (EAT)
EAT = (100 + 20)* α + (200 + 20)(1 – α)
= 220 – 100 * α
Operating System Principles
8.5
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z
“valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
z
“invalid” indicates that the page is not in the process’ logical
address space
8.6
Operating System Principles
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Shared Pages
Valid (v) or Invalid (i) Bit In A Page Table
„ Shared code
z
One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
z
Shared code must appear in same location in the logical
address space of all processes
„ Private code and data
z
Each process keeps a separate copy of the code and
data
z
The pages for the private code and data can appear
anywhere in the logical address space
A program with logical addresses 0 to 10468.
Note that a logical address of 10568 is ‘valid’, but it will be
blocked by limit register.
Operating System Principles
8.7
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Operating System Principles
8.8
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Shared Pages Example
8.5 Structure of the Page Table
„ Hierarchical Paging
z
Break up the logical address space into multiple page
tables
z
A simple technique is a two-level page table, in which
the page table itself is also paged
page number
p1
10
page offset
p2
d
10
12
where p1 is an index into the outer page table, and p2 is the
displacement within the page of the outer page table
8.9
Operating System Principles
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Operating System Principles
Two-Level Paging Example
8.10
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Address-Translation Scheme
„ A logical address (on 32-bit machine with 4K page size) is
divided into:
z
a page number consisting of 20 bits
z
a page offset consisting of 12 bits
„ Since the page table is paged, the page number is further
divided into:
z
a 10-bit page number
z
a 10-bit page offset of the outer pager table
Since address translation works from outer page table inward,
it is also known as forward-mapped page table.
Operating System Principles
8.11
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Operating System Principles
8.12
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Two-Level Page-Table Scheme
Three-level Paging Scheme
For a system with 64-bit logical address space, the following
should be avoided:
Too many levels would require too many number of memory accesses
To translate each logical address.
Operating System Principles
8.13
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Operating System Principles
Hashed Page Tables
8.14
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Hashed Page Table
„ Common in address spaces > 32 bits
„ The virtual page number is hashed into a page table.
This page table contains a chain of elements hashing to
the same location.
„ Virtual page numbers are compared in this chain
searching for a match. If a match is found, the
corresponding physical frame is extracted.
„ A variation uses cluster page tables, where each entry in
the hash table refers to several pages (such as 16) rather
than a single page
Operating System Principles
8.15
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Operating System Principles
8.16
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Inverted Page Table Architecture
Inverted Page Table
„ One entry for each real page of memory
z
Need only one inverted page table in a system
„ Entry consists of the virtual address of the page stored
in that real memory location, with information about the
process that owns that page
„ Decreases memory needed to store each page table,
but increases time needed to search the table when a
page reference occurs
„ Use hash table to limit the search to one — or at most a
few — page-table entries
„ Hard to implement shared memory
8.17
Operating System Principles
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Operating System Principles
8.6 Segmentation
8.18
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User’s View of a Program
„ Memory-management scheme that supports user view of
memory
„ A program is a collection of segments. A segment is a
logical unit such as:
main program,
procedure,
function,
method,
object,
local variables,
global variables,
common block,
stack,
symbol table,
arrays
Operating System Principles
8.19
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Operating System Principles
8.20
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Logical View of Segmentation
Segmentation Architecture
„ A logical address consists of a two tuple:
1
1
<segment-number, offset>
„ Segment table – maps two-dimensional physical
4
addresses; each table entry has:
2
z
base – contains the starting physical address where the
segments reside in memory
z
limit – specifies the length of the segment
3
4
2
„ Segment-table base register (STBR) points to the
3
segment table’s location in memory
„ Segment-table length register (STLR) indicates
user space
physical memory space
number of segments used by a program;
z
Operating System Principles
8.21
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a segment number s is legal if s < STLR
8.22
Operating System Principles
Segmentation Hardware
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Segmentation Architecture
„ Protection
z
With each entry in segment table associate:
validation
bit = 0 ⇒ illegal segment
read/write/execute
privileges
„ Protection bits associated with segments; code
sharing occurs at segment level
„ Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
„ A segmentation example is shown in the following
diagram
Operating System Principles
8.23
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Operating System Principles
8.24
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Example of Segmentation
8.7 Example: The Intel Pentium
„ Supports both segmentation and segmentation with
paging
„ CPU generates logical address
z
Given to segmentation unit
Which
z
produces linear addresses
Linear address given to paging unit
Which
generates physical address in main memory
Paging
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8.25
Operating System Principles
Operating System Principles
Logical to Physical Address Translation in
Pentium
units form equivalent of MMU
8.26
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Intel Pentium Segmentation
segment
number
LDT/GDT protection
s
g
13
1
offset
p
32
2
LDT: local descriptor table
GDT: global descriptor table
Each entry in LDT or GDT has 8-byte segment descriptor with detailed information
about the segment, including the base location and limit of that segment
Operating System Principles
8.27
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Operating System Principles
8.28
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Pentium Paging Architecture
8.8 Summary
„ The following considerations are used in comparing
different memory management strategies:
skip 8.7.3
Operating System Principles
8.29
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z
Hardware support
z
Performance
z
Fragmentation
z
Relocation
z
Swapping
z
Sharing
z
Protection
Operating System Principles
8.30
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