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Design Register Stack with Bubble Sorting Function
Hoda B. Abugharsa
The Higher Institute of Industry
Misurata, LIBYA
Email: hudabader82@yahoo.com
Abstract: -In this paper we propose to design a register-stack with sorting ability, that means at any time we
can stop pushing in and popping out data from the stack and start sorting the stored data. The sorting operation
design depends on converting a sorting algorithm that called Bubble Sorting Algorithm into an Algorithm
State Machine (ASM) chart in order to design a control unit for the stack that performs the sorting operation.
Key-Words: -ASM chart, Bubble Sorting Algorithm, Register Stack, Control Unit, Data Processor.
information that manipulated to perform arithmetic,
shift, and other similar data processing tasks.
Control information provides command signals that
supervised the various operations in order to
accomplish the desired data processing tasks. That
means it generates the signals for sequencing the
operations. It is a sequential circuit whose internal
states dictated the control commands for the system.
The control and data-processing tasks of a digital
system are specified by means of hardware
algorithms. An algorithm consists of a finite number
of ocedura1 steps that specify how to obtain a
solution to a problem [4][5]. A hardware algorithm
is a procedure for implementing the problem with a
given piece of equipment. A special flowchart that
has been developed specifically to define digital
hardware algorithms is called an algorithmic state
machine (ASM) chart.
1 Introduction
Many digital applications require that a data item
can be inserted into a set and popped back out from
that set at any time. This type of structure is called
last in first out (LIFO) stack [1]. In some
applications data that is stored in a stack need to be
sorted. Sort this data may be done by using a
hardware circuit.
The algorithm state machine ASM is a device that
has two units: data processor unit, and control unit.
These units could be designed using a special
flowchart called ASM chart.
2 Bubble Algorithm
Bubble sorting is the most widely known algorithm
among all sorting algorithms. One of the
characteristic of this algorithm that it is easy to
understand and apply [2]. Assume that the array
needs to be sorted is denoted by x . It contains of n
elements. The array elements are denoted by
x[0], x[1],............x[n - 2], x[n  1] . The basic idea is
illustrated in the following algorithm steps:
1. Start.
2. Let i=0
3. If i>n-2 go to step (8).
4. j=n-2
5. if j<i then let i=i+1 and go to step (3) .
6. if x[j] and x[j+1] are not sorted, then
exchange them.
7. j=j-1 and got to step (5).
8. End.
3 ASM Chart
Information in digital systems can be classified as
either data or control information. Data are
ISSN: 1790-5117
Fig. 1: Bubble Sorting Algorithm Flowchart.
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The ASM chart resembles a conventional
flowchart, but it is interpreted somewhat differently.
A conventional flowchart describes the sequence of
procedural steps and decision paths for an algorithm
without concern for their time relationship. But the
ASM chart describes the sequence of events as well
as the timing relationship between the states of a
sequential controller and the events that occur while
going from one state to other [4]. An ASM chart is
composed of three basic elements that shown in Fig.
2. These elements are the state box, the decision
box, and the conditional box. The shape of the state
box is a rectangle within which are written register
operations or output signal names that the control
generates while being in this state. The state is given
a symbolic name. The decision box describes the
effect of an input on the control subsystem. It has a
diamond-shaped box with two or more exit paths.
The third element that is conditional box is unique to
the ASM chart, it has an oval shape. The input path
to the conditional box must come from one of the
exit paths of a decision box. The register operations
or outputs listed inside the conditional box are
generated during a given state provided that the
input satisfied [4].
4.1 Moving Data in a stack
Data in a stack moves from one register to other as
follows[1]:
 When pushing data in, all previous stored
data are pushed deeper one register into the
stack.
 When popping data out, all previous stored
data are popped back out by one register from
the stack.
4.2 Status of a Stack
It is very important to know the status of the stack
before any new operation (pop or push operation).
The stack at each clock cycle can be [6]:
 Empty: No data can be popped out of the
stack, but new data can be pushed into it.
 Full: No data can be pushed into the stack, but
data can be popped out from it.
 Not empty/Not full: The stack contains at
least one item of data, so the pop operation
can be performed, and the stack is not
completely full, so that at least one item of
data can be pushed into the stack.
One way to detect the status of the stack is using
m -bit up/down counter, where m  log 2 n  1 .
Before the first use of the stack, the counter is
cleared. As an item is pushed into the stack, the
counter counts up, and when an item is popped out
from the stack, the counter counts down. If the
reading of the counter is zero then the stack is
empty, at this time if a pop signal occurs, then the
counter keeps zero on its output. If the counter
shows number of registers in the stack (n) then the
stack is full, at this time if a push signal occurs, then
the counter keeps n on its output. keeping the output
of the counter could be done by loading the counter
with its output. Fig. 4 shows a status detector circuit
for n registers-stack.
Binary code State Name
Register Operation
or output
State Box
0
Condition
1
Register Operation
or output
Decision Box Conditional Box
Fig. 2: ASM Charts Components.
4 Register Stack
The stack in many computing systems is
implemented with a group (array) of bi-directional
shift registers [1]. The bi-direction shift register is a
register with two data-in inputs and two data-out
outputs. The register-stack has there control signals;
they are Clk to drive clock signal, Push to move data
in a direction, and Pop to move data in the other
direction. Fig. 3 shows simplified illustration of a
register-stack using n bi-directional shift registers
{R0, R1, R2, ……….Rn-2, Rn-1} each one is r bits
register.
Fig. 4: Register Stack Status Detector.
5 The proposed Register Stack
Converting the bubble sorting flowchart into an
ASM chart is the first step to design the proposed
register stack with bubble sorting function. The
stack registers will be denoted by {R0, R1, R2,
Fig. 3: Register Stack with n Registers.
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into an ASM chart. We need to convert some
software expressions we have use in the flowchart
into hardware expressions. Fig. 6 shows the ASM
bubble sorting chart.
The variable i in that flowchart will be represented
in the proposed ASM chart as m-bit up counter (i
counter), where m  log 2 n  1 . The initializing
statement i=0 will be represented as clearing i
counter, that means the clear input of i counter
( CLRi ) must be equaled to 1. The variable j in the
same flowchart will be represented as m-bit down
counter (j counter). The initializing statement j=n-2
will be represented as loading j counter with the
value Q-2; where Q is the output of the status
detector circuit that represents number of full
registers in the stack. The value Q-2 could be
generated using a subtracter circuit that receives Q
and generates Q-2. This circuit is denoted by Q-2
circuit. Loading j counter with this value could be
done by making the load input of j counter ( LD j )
equals to 1.
……….Rn-2, Rn-1}, where n is number of registers in
the stack. The designed stack has a starting control
signal denoted by StartSort. If StartSort=0 then the
stack stays at its normal state, that means the stack
performs push and pop operations. If StartSort=1,
then the control signals (Push and Pop) will be
masked and the stack state will be changed into
sorting state. The stack stays at sorting state until an
output that is denoted by Endsort becomes 1, at this
time the stack is returned to the normal state and the
signals Push and Pop will not be masked.
At sorting state, we need to exchange data between
any two registers in the stack, that is why we need to
design an exchanger circuit.
5.1 Exchanger circuit
A stack with n registers requires n  1 exchanger
circuits, they are denoted by {C0, C1, C2, …….….
Cn-2}. The circuit Cj is connected to the registers Rj
and Rj+1. The function of the exchanger circuit Cj is
to exchange data between Rj and Rj+1 if they are not
sorted, that is why Cj has two other input signals:
 The SortType input is for defining the sorting
type. If SortType is equaled to 1, then it is
ascended sorting, that is why if Rj > Rj+1, then
we define Rj and Rj+1 as not sorted registers.
Otherwise if SortType is equaled to 0, then it is
descended sorting, that is why if Rj < Rj+1, then
we define Rj and Rj+1 as not sorted registers.
 The Enj signal is for enabling the exchanger
circuit Cj. If Enj is equaled to 0, then the circuit
will not exchange data between Rj and Rj+1
even they are not sorted.
If the registers R j and R j 1 are not sorted and the
enable input of Cj exchanger circuit is activated then
a pop signal to R j register ( Pop j ) and a push signal
to R j 1 register ( Push j 1 ) will occur. Pop j will occur
also if the external pop signal is equal to 1 (popping
data out from the stack in the normal state), and
Push j 1 will occur also if the external push signal is
equal to 1 (pushing data into the stack in the normal
state). Fig. 5 shows C j exchanger circuit.
Fig. 5:
Cj
Fig. 6: ASM Chart for the proposed Circuit.
In that bubble sorting flowchart there are some
compare operations. The first compare operations is
comparing the variable i with the value n-2. It will
be represented in the ASM chart by comparing the
output of i counter with the value Q-2, if i<=Q-2
then the comparator output (Z1) will equal to 1,
otherwise Z1 will equal to 0. The second compare
operation in the flowchart is comparing the variable
j with the variable i. This compare operation will be
represented by comparing the output of j counter
with the output of i counter, if j>=i then the
comparator output (Z2) will equal to 1, otherwise Z2
Exchanger Circuit.
5.2 Bubble ASM Chart
The first step of the proposed design is converting
the bubble sorting flowchart that shown in Fig. 1
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will equal to 0. The third compare operation in the
flowchart is comparing x[j] with x[j+1]. This
operation is represented by comparing Rj with Rj+1
data. When we need to compare Rj with Rj+1, we
must enable the exchanger circuit C j , that means Enj
input of Cj must be 1. An m/n decoder with enable
input could be use to activate only one exchanger
circuit each time. The input of this decoder is the
output of j counter. The outputs of this decoder are
connected to the enable inputs for the exchanger
circuits. When the enable input of the decoder
(EnDec) equals to 1 then the enable input of Cj will
equal to 1.
Fig. 7 shows the proposed register stack, it consists
of n registers, n-1 exchanger circuits, two counters, a
status detector, two comparators, and a control unit.
Fig. 7: The Proposed Register Stack with sorting Function
( Q1Q0 ). The inputs of these flip-flops are ( D1 D0 ).
Fig. 8 shows the control unit state table. From that
table the flip-flops inputs can be obtained from:
D0  T0 .StartSort  T2
D1  T1Z1  T2 . Z 2  T3
The outputs of the control circuit could be obtained
from:
5.3 The Control Unit
The ASM chart that is shown in Fig. 6 has 4 states;
they are T0, T1, T2 and T3. The binary codes of these
states are 00, 01, 10, and 11. The control unit for the
proposed stack is a sequential circuit. To design this
control unit we should represent the ASM chart in a
sequential circuits-state-table form. The inputs of the
sequential circuit are the start sorting signal
(StartSort), the first comparator output (Z1), and the
second comparator output (Z2). The outputs of this
sequential circuit are the clear input of i counter
(CLRi), the up count input of i counter (UPi), the
load input of j counter (LDj), the count down input
of j counter (Downj), the end sorting signal
(EndSort), and the enable input of the decoder
(EnDec). To implement four states sequential circuit
we need two flip-flops. We will use D flip-flops.
ISSN: 1790-5117
CLRi  T0 .StartSort
Upi  T2 .Z 2
LD j  T1. Z1
Down j  T3
EnDec  T2 .Z 2
EndSort  T1. Z 1
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Current State
State
T0
T0
T1
T1
T2
T2
T3
Q 1Q 0
00
00
01
01
10
10
11
Inputs
S*
0
1
x
x
x
x
x
Z1
x
x
0
1
x
x
x
Next State
Z2
x
x
x
x
0
1
x
State
T0
T1
T0
T2
T1
T3
T2
Q1Q0
00
01
00
10
01
11
10
Flip-Flops
Input
D1
D0
0
0
0
1
0
0
1
0
0
1
1
1
1
0
*S=StartSort
Fig. 8: Control Unit State Table.
Fig. 9 shows the complete control circuit for the
designed stack. An 2/4 decoder is used to decode the
two flip-flops output to the four states of the control
unit
Fig.9: Control Unit Circuit
References:
[1] Thomas L. Floyd "Digital Fundamentals",
Prentice Hall, July 2005.
[2] Robert Lafore, " Data Structures & Algorithms
in Java", Second Edition, Sams Publishing,
2003.
[3] Ronald L. Rivest, "Introduction to Algorithms",
Second Edition, McGraw-Hill Book Company,
2001.
[4] Morris Mano, "Digital Design", Prentice Hall,
Third Edition 2002.
[5] Sajjan G. Shjiva, Huntsville, " Introduction to
Logic Design", MARCEL DEKKER Inc, second
Edition, 1998.
[6] H. Abugharsa, A. H. Maamar, "Self Checking
Systolic Stack", WSEAS IMCAS'08, pp 98-101,
2008.
ISSN: 1790-5117
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ISBN: 978-960-474-155-7