a
Low Cost, Low Power
Instrumentation Amplifier
AD620
CONNECTION DIAGRAM
FEATURES
EASY TO USE
Gain Set with One External Resistor
(Gain Range 1 to 1000)
Wide Power Supply Range (62.3 V to 618 V)
Higher Performance than Three Op Amp IA Designs
Available in 8-Lead DIP and SOIC Packaging
Low Power, 1.3 mA max Supply Current
EXCELLENT DC PERFORMANCE (“B GRADE”)
50 mV max, Input Offset Voltage
0.6 mV/8C max, Input Offset Drift
1.0 nA max, Input Bias Current
100 dB min Common-Mode Rejection Ratio (G = 10)
LOW NOISE
9 nV/√Hz, @ 1 kHz, Input Voltage Noise
0.28 mV p-p Noise (0.1 Hz to 10 Hz)
RG
1
8
–IN
2
7 +VS
+IN
3
6 OUTPUT
–VS
4
AD620
RG
5 REF
TOP VIEW
1000. Furthermore, the AD620 features 8-lead SOIC and DIP
packaging that is smaller than discrete designs, and offers lower
power (only 1.3 mA max supply current), making it a good fit
for battery powered, portable (or remote) applications.
The AD620, with its high accuracy of 40 ppm maximum
nonlinearity, low offset voltage of 50 µV max and offset drift of
0.6 µV/°C max, is ideal for use in precision data acquisition
systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power
of the AD620 make it well suited for medical applications such
as ECG and noninvasive blood pressure monitors.
EXCELLENT AC SPECIFICATIONS
120 kHz Bandwidth (G = 100)
15 ms Settling Time to 0.01%
APPLICATIONS
Weigh Scales
ECG and Medical Instrumentation
Transducer Interface
Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment
PRODUCT DESCRIPTION
The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to
30,000
The low input bias current of 1.0 nA max is made possible with
the use of Superβeta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of
9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,
0.1 pA/√Hz input current noise. Also, the AD620 is well suited
for multiplexed applications with its settling time of 15 µs to
0.01% and its cost is low enough to enable designs with one inamp per channel.
10,000
25,000
3 OP-AMP
IN-AMP
(3 OP-07s)
1,000
RTI VOLTAGE NOISE
(0.1 – 10Hz) – mV p-p
TOTAL ERROR, PPM OF FULL SCALE
8-Lead Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
20,000
15,000
AD620A
10,000
RG
TYPICAL STANDARD
BIPOLAR INPUT
IN-AMP
100
G = 100
10
AD620 SUPERbETA
BIPOLAR INPUT
IN-AMP
1
5,000
0
0
5
10
SUPPLY CURRENT – mA
15
20
Figure 1. Three Op Amp IA Designs vs. AD620
0.1
1k
10k
100k
1M
SOURCE RESISTANCE – V
10M
100M
Figure 2. Total Voltage Noise vs. Source Resistance
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD620–SPECIFICATIONS
Model
Conditions
GAIN
Gain Range
Gain Error2
G=1
G = 10
G = 100
G = 1000
Nonlinearity,
G = 1–1000
G = 1–100
Gain vs. Temperature
G = 1 + (49.4 k/R G)
VOUT = ± 10 V
(Typical @ +258C, VS = 615 V, and RL = 2 kV, unless otherwise noted)
Min
AD620A
Typ Max
1
VOUT = –10 V to +10 V,
RL = 10 kΩ
RL = 2 kΩ
10,000
Over Temperature
Average TC
Offset Referred to the
Input vs.
Supply (PSR)
G=1
G = 10
G = 100
G = 1000
Over Temperature
Common-Mode Rejection
Ratio DC to 60 Hz with
I kΩ Source Imbalance
G=1
G = 10
G = 100
G = 1000
OUTPUT
Output Swing
Over Temperature
Over Temperature
Short Current Circuit
1
10,000
(Total RTI Error = V OSI + VOSO/G)
VS = ± 5 V to ± 15 V
VS = ± 5 V to ± 15 V
VS = ± 5 V to ± 15 V
VS = ± 15 V
VS = ± 5 V
VS = ± 5 V to ± 15 V
VS = ± 5 V to ± 15 V
Min
AD620S1
Typ Max
1
Units
10,000
0.10
0.30
0.30
0.70
0.01
0.10
0.10
0.35
0.02
0.15
0.15
0.50
0.03
0.15
0.15
0.40
0.10
0.30
0.30
0.70
%
%
%
%
10
10
40
95
10
10
40
95
10
10
40
95
ppm
ppm
10
–50
ppm/°C
ppm/°C
125
225
1.0
1000
1500
2000
15
µV
µV
µV/°C
µV
µV
µV
µV/°C
10
–50
30
0.3
400
5.0
10
–50
125
185
1.0
1000
1500
2000
15
15
0.1
200
2.5
50
85
0.6
500
750
1000
7.0
30
0.3
400
5.0
VS = ± 2.3 V to ± 18 V
80
95
110
110
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range 3
Over Temperature
AD620B
Typ Max
0.03
0.15
0.15
0.40
G =1
Gain >1 2
VOLTAGE OFFSET
Input Offset, VOSI
Over Temperature
Average TC
Output Offset, V OSO
Min
100
120
140
140
0.5
3.0
0.3
VS = ± 2.3 V to ± 5 V
VS = ± 5 V to ± 18 V
80
100
120
120
2.0
2.5
100
120
140
140
0.5
3.0
0.3
1.0
1.5
80
95
110
110
1.0
1.5
100
120
140
140
0.5
8.0
0.3
0.5
0.75
1.5
1.5
8.0
10i2
10i2
10i2
10i2
10i2
10i2
–VS + 1.9
–VS + 2.1
–VS + 1.9
–VS + 2.1
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.4
–VS + 1.9
–VS + 2.1
–VS + 1.9
–VS + 2.1
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.4
–VS + 1.9
–VS + 2.1
–VS + 1.9
–VS + 2.3
dB
dB
dB
dB
2
4
1.0
2.0
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.4
nA
nA
pA/°C
nA
nA
pA/°C
GΩipF
GΩipF
V
V
V
V
VCM = 0 V to ± 10 V
73
93
110
110
RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V
VS = ± 5 V to ± 18 V
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
90
110
130
130
± 18
80
100
120
120
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.5
–2–
–VS + 1.1
–VS + 1.4
–VS + 1.2
–VS + 1.6
90
110
130
130
± 18
73
93
110
110
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.5
–VS + 1.1
–VS + 1.6
–VS + 1.2
–VS + 2.3
90
110
130
130
± 18
dB
dB
dB
dB
+VS – 1.2
+VS – 1.3
+VS – 1.4
+VS – 1.5
V
V
V
V
mA
REV. E
AD620
Model
Conditions
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%
10 V Step
G = 1–100
G = 1000
Min
AD620A
Typ Max
1000
800
120
12
1.2
0.75
Min
0.75
15
150
AD620B
Typ Max
1000
800
120
12
1.2
Min
0.75
15
150
AD620S1
Typ Max
Units
1000
800
120
12
1.2
kHz
kHz
kHz
kHz
V/µs
15
150
µs
µs
NOISE
Voltage Noise, 1 kHz
Input, Voltage Noise, e ni
Output, Voltage Noise, e no
RTI, 0.1 Hz to 10 Hz
G=1
G = 10
G = 100–1000
Current Noise
0.1 Hz to 10 Hz
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
POWER SUPPLY
Operating Range 4
Quiescent Current
Over Temperature
Total RTI Noise = (e2 ni ) + (eno / G)2
9
72
f = 1 kHz
VIN+ , VREF = 0
VS = ± 2.3 V to ± 18 V
13
100
13
100
9
72
13
100
nV/√Hz
nV/√Hz
3.0
0.55
0.28
100
10
3.0 6.0
0.55 0.8
0.28 0.4
100
10
3.0 6.0
0.55 0.8
0.28 0.4
100
10
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
20
+50
20
+50
20
+50
kΩ
µA
V
+60
–VS + 1.6
+VS – 1.6
1 ± 0.0001
+60
–VS + 1.6
+VS – 1.6
1 ± 0.0001
+60
–VS + 1.6
+VS – 1.6
1 ± 0.0001
± 2.3
± 2.3
± 2.3
TEMPERATURE RANGE
For Specified Performance
± 18
1.3
1.6
0.9
1.1
–40 to +85
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
Does not include effects of external resistor R G.
3
One input grounded. G = 1.
4
This is defined as the same supply range which is used to specify PSR.
Specifications subject to change without notice.
REV. E
9
72
–3–
0.9
1.1
–40 to +85
± 18
1.3
1.6
0.9
1.1
± 18
1.3
1.6
–55 to +125
V
mA
mA
°C
AD620
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .± 25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package: θJA = 95°C/W
8-Lead Cerdip Package: θJA = 110°C/W
8-Lead SOIC Package: θJA = 155°C/W
Model
Temperature Ranges Package Options*
AD620AN
AD620BN
AD620AR
AD620AR-REEL
AD620AR-REEL7
AD620BR
AD620BR-REEL
AD620BR-REEL7
AD620ACHIPS
AD620SQ/883B
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-8
N-8
SO-8
13" REEL
7" REEL
SO-8
13" REEL
7" REEL
Die Form
Q-8
*N = Plastic DIP; Q = Cerdip; SO = Small Outline.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
RG*
8
+VS
OUTPUT
7
6
5
REFERENCE
8
0.0708
(1.799)
1
1
RG*
3
2
–IN
0.125
(3.180)
4
–VS
+IN
*FOR CHIP APPLICATIONS: THE PADS 1RG AND 8RG MUST BE CONNECTED IN PARALLEL
TO THE EXTERNAL GAIN REGISTER RG. DO NOT CONNECT THEM IN SERIES TO RG. FOR
UNITY GAIN APPLICATIONS WHERE RG IS NOT REQUIRED, THE PADS 1RG MAY SIMPLY
BE BONDED TOGETHER, AS WELL AS THE PADS 8RG.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. E
AD620
Typical Characteristics (@ +258C, V = 615 V, R = 2 kV, unless otherwise noted)
S
L
50
2.0
SAMPLE SIZE = 360
1.5
INPUT BIAS CURRENT – nA
PERCENTAGE OF UNITS
40
30
20
10
1.0
+IB
–I B
0.5
0
–0.5
–1.0
–1.5
0
–80
–40
0
+40
–2.0
+80
–75
INPUT OFFSET VOLTAGE – mV
Figure 3. Typical Distribution of Input Offset Voltage
–25
25
75
TEMPERATURE – 8C
125
175
Figure 6. Input Bias Current vs. Temperature
2
50
CHANGE IN OFFSET VOLTAGE – mV
SAMPLE SIZE = 850
PERCENTAGE OF UNITS
40
30
20
10
0
–1200
–600
0
+600
1.5
1
0.5
0
+1200
0
1
INPUT BIAS CURRENT – pA
Figure 4. Typical Distribution of Input Bias Current
2
3
WARM-UP TIME – Minutes
4
5
Figure 7. Change in Input Offset Voltage vs.
Warm-Up Time
50
1000
SAMPLE SIZE = 850
GAIN = 1
VOLTAGE NOISE – nV/!Hz
PERCENTAGE OF UNITS
40
30
20
10
100
GAIN = 10
10
GAIN = 100, 1,000
GAIN = 1000
BW LIMIT
0
–400
–200
0
+200
1
+400
1
INPUT OFFSET CURRENT – pA
Figure 5. Typical Distribution of Input Offset Current
REV. E
10
100
1k
FREQUENCY – Hz
10k
100k
Figure 8. Voltage Noise Spectral Density vs. Frequency,
(G = 1–1000)
–5–
AD620–Typical Characteristics
CURRENT NOISE – fA/!Hz
1000
100
10
1
10
100
FREQUENCY – Hz
1000
Figure 9. Current Noise Spectral Density vs. Frequency
Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
RTI NOISE – 2.0 mV/DIV
TOTAL DRIFT FROM 258C TO 858C, RTI – mV
100,000
10,000
FET INPUT
IN-AMP
1000
AD620A
100
10
TIME – 1 SEC/DIV
1k
10k
100k
1M
SOURCE RESISTANCE – V
10M
Figure 12. Total Drift vs. Source Resistance
Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
+160
+140
RTI NOISE – 0.1mV/DIV
+120
G = 1000
G = 100
G = 10
CMR – dB
+100
G=1
+80
+60
+40
+20
0
0.1
TIME – 1 SEC/DIV
1
10
100
1k
FREQUENCY – Hz
10k
100k
1M
Figure 13. CMR vs. Frequency, RTI, Zero to 1 kΩ Source
Imbalance
Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
–6–
REV. E
AD620
180
35
G = 10, 100, 1000
160
140
G = 1000
PSR – dB
120
100
G = 100
80
G = 10
60
G=1
40
20
0.1
G=1
20
15
10
5
G = 1000
G = 100
0
1
10
100
1k
FREQUENCY – Hz
10k
100k
1k
1M
10k
100k
FREQUENCY – Hz
1M
Figure 17. Large Signal Frequency Response
Figure 14. Positive PSR vs. Frequency, RTI (G = 1–1000)
+VS –0.0
160
–0.5
INPUT VOLTAGE LIMIT – Volts
(REFERRED TO SUPPLY VOLTAGES)
180
140
120
PSR – dB
25
BW LIMIT
OUTPUT VOLTAGE – Volts p-p
30
100
G = 1000
80
G = 100
60
G = 10
40
–1.0
–1.5
+1.5
+1.0
+0.5
G=1
20
0.1
–VS +0.0
1
10
100
1k
FREQUENCY – Hz
10k
100k
1M
Figure 15. Negative PSR vs. Frequency, RTI (G = 1–1000)
OUTPUT VOLTAGE SWING – Volts
(REFERRED TO SUPPLY VOLTAGES)
GAIN – V/V
10
15
SUPPLY VOLTAGE 6 Volts
20
+VS –0.0
100
10
1
1k
10k
100k
FREQUENCY – Hz
1M
–0.5
RL = 10kV
–1.0
RL = 2kV
–1.5
+1.5
RL = 2kV
+1.0
RL = 10kV
+0.5
–VS +0.0
10M
0
Figure 16. Gain vs. Frequency
REV. E
5
Figure 18. Input Voltage Range vs. Supply Voltage, G = 1
1000
0.1
100
0
5
10
15
SUPPLY VOLTAGE 6 Volts
20
Figure 19. Output Voltage Swing vs. Supply Voltage,
G = 10
–7–
AD620
OUTPUT VOLTAGE SWING – Volts p-p
30
.... .... .... ........ ........ .... ........
VS = 615V
G = 10
20
10
.... .... .... ........ ........ .... ........
0
0
100
1k
LOAD RESISTANCE – V
10k
Figure 20. Output Voltage Swing vs. Load Resistance
Figure 23. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)
.... .... .... ........ ........ .... ........
.... .... ........ .... ........ .... ........
.... .... .... ........ ........ .... ........
.... .... ........ .... ........ .... ........
Figure 21. Large Signal Pulse Response and Settling Time
G = 1 (0.5 mV = 0.01%)
Figure 24. Small Signal Response, G = 10, RL = 2 kΩ,
CL = 100 pF
.... .... .... ........ ........ .... ........
.... .... .... ........ ........ .... ........
.... .... .... ........ ........ .... ........
.... .... .... ........ ........ .... ........
Figure 22. Small Signal Response, G = 1, RL = 2 kΩ,
CL = 100 pF
Figure 25. Large Signal Response and Settling Time,
G = 100 (0.5 mV = 0.01%)
–8–
REV. E
AD620
20
.... .... .... ........ ........ .... ........
SETTLING TIME – ms
15
TO 0.01%
TO 0.1%
10
5
.... .... .... ........ ........ .... ........
0
Figure 26. Small Signal Pulse Response, G = 100,
RL = 2 kΩ, CL = 100 pF
0
5
10
15
OUTPUT STEP SIZE – Volts
20
Figure 29. Settling Time vs. Step Size (G = 1)
1000
SETTLING TIME – ms
.... .... ........ ........ .... .... ........
100
10
.... .... ........ ........ .... .... ........
1
1
10
100
1000
GAIN
Figure 27. Large Signal Response and Settling Time,
G = 1000 (0.5 mV = 0.01%)
Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step
.... .... .... ........ ........ .... ........
.... .... ........ ........ .... .... ........
.... .... .... ........ ........ .... ........
.... .... ........ ........ .... .... ........
Figure 31a. Gain Nonlinearity, G = 1, RL = 10 kΩ
(10 µ V = 1 ppm)
Figure 28. Small Signal Pulse Response, G = 1000,
RL = 2 kΩ, CL = 100 pF
REV. E
–9–
AD620
I1
20mA
VB
I2
20mA
.... .... .... ........ .... .... .... ........
A1
A2
10kV
C2
C1
10kV
A3
– IN
R3
400V
R1
10kV
R2
Q1
Q2
R4
400V
RG
.... .... .... ........ .... .... .... ........
GAIN
SENSE
OUTPUT
10kV
REF
+IN
GAIN
SENSE
–VS
Figure 33. Simplified Schematic of AD620
Figure 31b. Gain Nonlinearity, G = 100, RL = 10 kΩ
(100 µ V = 10 ppm)
THEORY OF OPERATION
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and
tracking of circuit components, thus ensuring the high level of
performance inherent in this circuit.
.... .... ........ ........ .... .... ........
The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 33), yet offer 10×
lower Input Bias Current thanks to Superβeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1, Q2
thereby impressing the input voltage across the external gain
setting resistor RG. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1.
The unity-gain subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin
potential.
.... .... ........ ........ .... .... ........
Figure 31c. Gain Nonlinearity, G = 1000, RL = 10 kΩ
(1 mV = 100 ppm)
10kV*
INPUT
10V p-p
1kV
10T
10kV
100kV
VOUT
+VS
11kV
1kV
2
100V
7
1
G=1000
G=1
AD620
G=100 G=10
49.9V
499V
5.49kV
6
5
8
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gainrelated errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/√Hz, determined mainly by the collector current and base resistance of the
input devices.
The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 kΩ, allowing the gain to be programmed
accurately with a single external resistor.
4
The gain equation is then
3
–VS
G=
*ALL RESISTORS 1% TOLERANCE
Figure 32. Settling Time Test Circuit
49.4 kΩ
+1
RG
so that
RG =
–10–
49.4 kΩ
G −1
REV. E
AD620
Make vs. Buy: A Typical Bridge Application Error Budget
The AD620 offers improved performance over “homebrew”
three op amp IA designs, along with smaller size, fewer components and 10× lower supply current. In the typical application,
shown in Figure 34, a gain of 100 is required to amplify a bridge
output of 20 mV full scale over the industrial temperature range
of –40°C to +85°C. The error budget table below shows how to
calculate the effect various error sources have on circuit accuracy.
Regardless of the system in which it is being used, the AD620
provides greater accuracy, and at low power and price. In simple
systems, absolute accuracy and drift errors are by far the most
significant contributors to error. In more complex systems with
an intelligent processor, an autogain/autozero cycle will remove all
absolute accuracy and drift errors leaving only the resolution
errors of gain nonlinearity and noise, thus allowing full 14-bit
accuracy.
Note that for the homebrew circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by √2. This
is because a three op amp type in-amp has two op amps at its
inputs, both contributing to the overall input error.
+10V
10kV*
10kV*
OP07D
R = 350V
R = 350V
10kV**
RG
499V
R = 350V
AD620A
100V**
OP07D
10kV**
R = 350V
REFERENCE
OP07D
10kV*
PRECISION BRIDGE TRANSDUCER
AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100
10kV*
“HOMEBREW” IN-AMP, G = 100
*0.02% RESISTOR MATCH, 3PPM/8C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/8C TRACKING
SUPPLY CURRENT = 15mA MAX
SUPPLY CURRENT = 1.3mA MAX
Figure 34. Make vs. Buy
Table I. Make vs. Buy Error Budget
Error Source
AD620 Circuit
Calculation
“Homebrew” Circuit
Calculation
Error, ppm of Full Scale
AD620
Homebrew
ABSOLUTE ACCURACY at TA = +25°C
Input Offset Voltage, µV
Output Offset Voltage, µV
Input Offset Current, nA
CMR, dB
125 µV/20 mV
1000 µV/100/20 mV
2 nA × 350 Ω/20 mV
110 dB→3.16 ppm, × 5 V/20 mV
(150 µV × √2)/20 mV
((150 µV × 2)/100)/20 mV
(6 nA × 350 Ω)/20 mV
(0.02% Match × 5 V)/20 mV/100
16,250
14,500
14,118
14,791
10,607
10,150
14,153
10,500
Total Absolute Error
17,558
11,310
100 ppm/°C Track × 60°C
(2.5 µV/°C × √2 × 60°C)/20 mV
(2.5 µV/°C × 2 × 60°C)/100/20 mV
13,600
13,000
14,450
16,000
10,607
10,150
Total Drift Error
17,050
16,757
40 ppm
(0.38 µV p-p × √2)/20 mV
14,140
141,14
10,140
13,127
Total Resolution Error
14,154
101,67
Grand Total Error
14,662
28,134
DRIFT TO +85°C
Gain Drift, ppm/°C
Input Offset Voltage Drift, µV/°C
Output Offset Voltage Drift, µV/°C
(50 ppm + 10 ppm) × 60°C
1 µV/°C × 60°C/20 mV
15 µV/°C × 60°C/100/20 mV
RESOLUTION
Gain Nonlinearity, ppm of Full Scale
40 ppm
Typ 0.1 Hz–10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV
G = 100, VS = ± 15 V.
(All errors are min/max and referred to input.)
REV. E
–11–
AD620
+5V
3kV
3kV
3kV
3kV
20kV
7
3
REF
8
AD620B
G=100
499V
6
IN
5
1
ADC
10kV
DIGITAL
DATA
OUTPUT
4
2
AD705
AGND
20kV
1.7mA
0.6mA
MAX
0.10mA
1.3mA
MAX
Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply
Pressure Measurement
Medical ECG
Although useful in many bridge applications such as weigh
scales, the AD620 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small size and
low power become more significant.
The low current noise of the AD620 allows its use in ECG
monitors (Figure 36) where high source resistances of 1 MΩ or
higher are not uncommon. The AD620’s low power, low supply
voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery
powered data recorders.
Figure 35 shows a 3 kΩ pressure transducer bridge powered
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the
signal to be conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic noninvasive blood pressure measurement.
Furthermore, the low bias currents and low current noise
coupled with the low voltage noise of the AD620 improve the
dynamic range for better performance.
The value of capacitor C1 is chosen to maintain stability of the
right leg drive loop. Proper safeguards, such as isolation, must
be added to this circuit to protect the patient from possible
harm.
+3V
PATIENT/CIRCUIT
PROTECTION/ISOLATION
C1
R1
10kV
R3
24.9kV
R2
24.9kV
R4
1MV
RG
8.25kV
AD620A
G=7
0.03Hz
HIGH
PASS
FILTER
G = 143
OUTPUT
1V/mV
OUTPUT
AMPLIFIER
AD705J
–3V
Figure 36. A Medical ECG Monitor Circuit
–12–
REV. E
AD620
Precision V-I Converter
INPUT AND OUTPUT OFFSET VOLTAGE
The AD620, along with another op amp and two resistors, makes
a precision current source (Figure 37). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
VX of the AD620 appears across R1, which converts it to a
current. This current less only, the input bias current of the op
amp, then flows out to the load.
The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total VOS for a given gain is calculated as:
Total Error RTI = input error + (output error/G)
Total Error RTO = (input error × G) + output error
+VS
VIN+
REFERENCE TERMINAL
7
3
8
The reference terminal potential defines the zero output voltage,
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.
+ VX –
AD620
RG
6
R1
1
VIN–
5
2
4
I
–VS
I L=
Vx
R1
=
L
AD705
INPUT PROTECTION
[(V IN+) – (V IN– )] G
R1
LOAD
Figure 37. Precision Voltage-to-Current Converter
(Operates on 1.8 mA, ± 3 V)
GAIN SELECTION
The AD620’s gain is resistor programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1%–1%
resistors. Table II shows required values of RG for various gains.
Note that for G = 1, the RG pins are unconnected (RG = ∞). For
any arbitrary gain RG can be calculated by using the formula:
RG =
49.4 kΩ
G −1
To minimize gain error, avoid high parasitic resistance in series
with RG; to minimize gain drift, RG should have a low TC—less
than 10 ppm/°C—for the best performance.
The AD620 features 400 Ω of series thin film resistance at its
inputs, and will safely withstand input overloads of up to ± 15 V
or ±60 mA for several hours. This is true for all gains, and power
on and off, which is particularly important since the signal
source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (IIN ≤
VIN/400 Ω). For input overloads beyond the supplies, clamping
the inputs to the supplies (using a low leakage diode such as an
FD333) will reduce the required resistance, yielding lower
noise.
RF INTERFERENCE
All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
small dc offset errors. The AD620 allows direct access to the
input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 38),
where RC < 1/(2 πf) and where f ≥ the bandwidth of the
AD620; C ≤ 150 pF. Matching the extraneous capacitance at
Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.
Table II. Required Values of Gain Resistors
1% Std Table
Value of RG, V
Calculated
Gain
0.1% Std Table
Value of RG, V
Calculated
Gain
49.9 k
12.4 k
5.49 k
1.990
4.984
9.998
49.3 k
12.4 k
5.49 k
2.002
4.984
9.998
2.61 k
1.00 k
499
19.93
50.40
100.0
2.61 k
1.01 k
499
19.93
49.91
100.0
249
100
49.9
199.4
495.0
991.0
249
98.8
49.3
199.4
501.0
1,003
RG
1
8
2
7
3
6
4
5
C
R
–IN
R
+IN
C
Figure 38. Circuit to Attenuate RF Interference
REV. E
–13–
AD620
COMMON-MODE REJECTION
GROUNDING
Instrumentation amplifiers like the AD620 offer high CMR,
which is a measure of the change in output voltage when both
inputs are changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a specified source imbalance.
Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems by simply tying the REF pin to the appropriate “local
ground.”
For optimal CMR the reference terminal should be tied to a low
impedance point, and differences in capacitance and resistance
should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
best CMR over frequency the shield should be properly driven.
Figures 39 and 40 show active data guards that are configured
to improve ac common-mode rejections by “bootstrapping” the
capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs.
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 41). It would be convenient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be
tied together at some point, usually best at the ADC package as
shown.
+VS
ANALOG P.S.
+15V C –15V
– INPUT
DIGITAL P.S.
C +5V
AD648
100V
0.1mF
RG
100V
AD620
0.1mF
1mF 1mF
1mF
VOUT
+
–VS
AD620
REFERENCE
AD585
AD574A
S/H
ADC
DIGITAL
DATA
OUTPUT
+ INPUT
–VS
Figure 41. Basic Grounding Practice
Figure 39. Differential Shield Driver
+VS
– INPUT
100V
RG
2
AD548
RG
2
AD620
VOUT
REFERENCE
+ INPUT
–VS
Figure 40. Common-Mode Shield Driver
–14–
REV. E
AD620
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore, when amplifying “floating” input
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figure 42.
Refer to the Instrumentation Amplifier Application Guide (free
from Analog Devices) for more information regarding in amp
applications.
+VS
+VS
– INPUT
– INPUT
RG
AD620
AD620
RG
VOUT
VOUT
LOAD
LOAD
+ INPUT
REFERENCE
REFERENCE
+ INPUT
–VS
–VS
TO POWER
SUPPLY
GROUND
TO POWER
SUPPLY
GROUND
Figure 42b. Ground Returns for Bias Currents with
Thermocouple Inputs
Figure 42a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
+VS
– INPUT
RG
AD620
VOUT
LOAD
+ INPUT
100kV
100kV
REFERENCE
–VS
TO POWER
SUPPLY
GROUND
Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs
REV. E
–15–
AD620
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
8
C1599c–0–7/99
0.430 (10.92)
0.348 (8.84)
5
1
0.280 (7.11)
0.240 (6.10)
4
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.015 (0.381)
0.008 (0.204)
Cerdip (Q-8) Package
0.005 (0.13)
MIN
0.055 (1.4)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
PIN 1
0.200 (5.08)
MAX
0.320 (8.13)
0.290 (7.37)
0.405 (10.29)
0.060 (1.52)
MAX
0.015 (0.38)
0.150
(3.81)
0.200 (5.08)
MIN
0.125 (3.18)
0.023 (0.58) 0.100 0.070 (1.78) SEATING
PLANE
0.014 (0.36) (2.54) 0.030 (0.76)
BSC
15°
0°
0.015 (0.38)
0.008 (0.20)
SOIC (SO-8) Package
0.1968 (5.00)
0.1890 (4.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
–16–
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0° 0.0500 (1.27)
0.0160 (0.41)
PRINTED IN U.S.A.
0.1574 (4.00)
0.1497 (3.80)
REV. E