IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
75
61
A Continuous-Time
Modulator With 88-dB
Dynamic Range and 1.1-MHz Signal Bandwidth
Shouli Yan, Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE
61
Abstract—This paper presents the design and experimental remodulator for ADSL applications.
sults of a continuous-time
Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem
in conventional continuous-time
modulators is solved by our
proposed architecture. A prototype third-order continuous-time
modulator with 5-bit internal quantization was realized in
a 0.5- m double-poly triple-metal CMOS technology, with a chip
area of 2.4 2.4 mm2 . Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR
over a 1.1-MHz signal bandwidth with an oversampling ratio of 16,
while dissipating 62 mW from a 3.3-V supply.
61
61
61
Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits, continuous-time
modulation, multibit internal
quantization.
I. INTRODUCTION
W
IRELESS and wireline communication applications
demand analog-to-digital converters (ADCs) with
megahertz signal bandwidth and 14-bit or better resolution.
ADCs
Compared with Nyquist-rate ADCs, oversampling
use more digital signal processing to perform analog-to-digital conversion, with the advantage of significantly relaxed
matching requirements on analog components, while still
achieving medium to high resolution [1]. Moreover, thanks
ADCs do not need steep roll-off
to the oversampling,
antialias filtering, which is usually required in Nyquist-rate
ADCs. Power-hungry high-order high-linearity antialias filters
with accurate cutoff frequencies are thus avoided.
ADCs are traditionally used in instruOversampling
mentation, seismic, voice, and audio applications, with low
signal bandwidth and high resolution. In recent years, due to
improvements in CMOS technology and architecture/circuit
ADCs can achieve higher input signal
design techniques,
bandwidth and medium to high resolution (12–16 bits), and
enjoy wide deployment in wireless and wireline communication
applications [2], [3].
modulators are based on switchedMost of the earlier
modulators with concapacitor circuit techniques, whereas
Manuscript received October 10, 2002; revised July 18, 2003. This work was
supported in part by Texas Instruments, Inc.
S. Yan was with the Analog and Mixed-Signal Center, Texas A&M University, College Station, TX 77843-3128 USA. He is now with the Department of
Electrical and Computer Engineering and the Computer Engineering Research
Center (CERC), University of Texas, Austin, TX 78712-1084 USA (e-mail:
slyan@ece.utexas.edu).
E. Sánchez-Sinencio is with the Analog and Mixed-Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX
77843-3128 USA (e-mail: sanchez@ee.tamu.edu).
Digital Object Identifier 10.1109/JSSC.2003.820856
tinuous-time loop filters can potentially achieve higher clock
frequency and/or consume less power. A few continuous-time
modulators have been successfully built for voice, audio
[4], and AM/FM radio or GSM receivers [5], [6] applications
with a few kilohertz up to 200-kHz signal bandwidth.
Our work is the first attempt, to the best of the authors’ knowledge, to reach 88-dB (better than 14-bit) dynamic range with
modover 1-MHz signal bandwidth using continuous-time
ulation techniques [7]. Multibit nonreturn-to-zero (NRZ) DAC
pulse shaping is used to minimize clock jitter sensitivity and to
improve resolution. Clock jitter sensitivity is reduced by more
than 33 dB over prior work [6] as simulated and calculated.
The nonzero excess loop delay problem of conventional continmodulators has been solved by a proposed archiuous-time
tecture. A dynamic range of 88 dB is achieved experimentally
by the prototype chip over 1.1-MHz signal bandwidth with a
clock frequency of 35.2 MHz, proving the effectiveness of the
proposed architecture and circuit design techniques.
The rest of this paper is organized as follows. Section II
architecture level considerations. Section III
discusses
addresses circuit design issues. Section IV presents the prototype chip microphotograph and experimental results. Section V
concludes the paper.
II. ARCHITECTURE LEVEL CONSIDERATIONS
modulators with signal bandwidth up to tens of
For
kilohertz, a large oversampling ratio (OSR) from 64 to 256 is
usually used with significant noise shaping, achieving a high
resolution. However, we cannot extend the signal bandwidth
into the megahertz range by simply increasing the clock
frequency without reducing OSR. An OSR of less than 64
is usually preferred for a wide input signal bandwidth with
a reasonable clock frequency that can be realized in current
CMOS or BiCMOS process technologies.
A. Architecture Level Design Options for High-Speed
Modulators
To improve resolution at a low OSR, we can either: 1) use
a higher order loop filter, and/or 2) increase internal quantizer
resolution. For single-bit single-loop modulators, we have to
reduce the integrator gain to maintain the stability when the
loop order is increased. Thus, little signal-to-noise ratio (SNR)
improvement can be gained by simply increasing the loop
filter order at a low OSR. Widely used multiloop (MASH)
topologies, with two or three cascaded loops of first-order
and/or second-order modulators, solve the stability problem of
single-loop high-order modulators.
0018-9200/04$20.00 © 2004 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 1. General block diagram of a continuous-time
61 modulator.
Another way to achieve high resolution is to use multibit
internal quantization. Since multibit quantizers have less
nonlinearity than single-bit quantizers, the stability of multibit
modulators is significantly improved. Thus,
single-loop
more aggressive noise-shaping transfer functions can be employed, with the benefit of extra dynamic range in addition to
dB (where is the bit number of internal
the
quantization) improvement over single-bit quantization [8].
modulators have been successfully built using one
Several
or both of these techniques: 1) cascaded topologies with 1-bit
quantization in all loops [9], [10]; 2) cascaded topologies with
multibit quantization in one or more loops [2], [10]–[12]; and
3) multibit single-loop modulators [3], [13]–[15].
B. Continuous-Time
Modulators
kHz)
Most prior wide-bandwidth (signal bandwidth
modulators are implemented using switched-capacitor circuit techniques. In switched-capacitor circuits, amplifiers with
high unity-gain bandwidths (usually at least five times the clock
frequency) are required to satisfy the settling accuracy requirements. No settling behavior is involved in continuous-time loop
modulators can potentially opfilters, thus continuous-time
erate at higher clock frequencies and/or with less power conmodulation
sumption. Another benefit of continuous-time
is intrinsic antialias filtering [16]. As shown in Fig. 1, because
the input signal is sampled after being filtered through the continuous-time loop filter, significant suppression at aliasing frequencies can be obtained.
modulation is much
A third benefit of continuous-time
relaxed sampling network requirements [16]. It is a challenging task to design the front-end sampling network for a
modulator [12], [17], [18], because a
switched-capacitor
sampling accuracy greater than the full resolution of the entire
modulator,
modulator is needed. But in a continuous-time
the sampler is inside the noise-shaping loop. Any sampling
error, together with the quantization noise, is significantly
suppressed (usually by over 50 dB) by the high gain of the
loop filter in the bandwidth of interest. Thus, the performance
requirement of the sampler is significantly relaxed.
modulators
As well as their benefits, continuous-time
have drawbacks. They are more sensitive to clock jitter than
switched-capacitor modulators. As the sampler of a continmodulator directly follows the loop filter, as
uous-time
shown in Fig. 1, any error of the sampler, including clock jitter
timing error, is significantly suppressed at low frequencies,
thanks to the noise-shaping effect. Thus, clock jitter presents
little problem at the sampler. However, timing error of the
feedback DAC is directly superimposed upon the input signal
without any noise shaping, and significant SNR degradation
modulators are
results. Consequently, continuous-time
more vulnerable to clock jitter than are switched-capacitor
implementations [19]. This effect must be minimized for
modulators.
high-performance
Another problem of continuous-time
modulators is
nonzero excess loop delay [20]. The ADC and the DAC are
required to have zero input-output time delay when an NRZ
feedback DAC is used. Performance degradation or even
instability may result if the excess loop delay is too large.
Even though the modulator architecture can be designed to
accommodate a known delay, signal-dependent delay of the
internal ADC may still degrade the SNR performance. Delayed
return-to-zero (RZ) DAC pulse shaping can be used to relax
loop delay to a fraction of the clock period [20]. However,
a multibit RZ DAC is more sensitive to clock jitter than is a
multibit NRZ DAC. We will address this issue shortly.
C. Proposed Continuous-Time
Modulator Architecture
implementation for its low
We chose a continuous-time
power consumption potential. Prior implementations of basemodulators use single-bit topologies
band continuous-time
with limited dynamic range [21] or limited bandwidth [4]–[6].
Better than 80-dB dynamic ranges are achieved in [5] and
[6] over 100- and 200-kHz signal bandwidths, respectively,
utilizing similar architectures with an OSR of 50–65. However,
clock jitter of less than 7 ps is required (as simulated in [6])
to meet the design target. The architectures used in [5] and
[6] have difficulty obtaining higher signal bandwidth (such as
1.1 MHz) and over 80-dB dynamic range. Simple calculations
suggest that 110–140 MHz clock frequency and less than
1.3-ps clock jitter are required for 1.1-MHz signal bandwidth.
This low value of clock jitter is difficult to achieve even with
high-quality crystal oscillators.
As discussed earlier, to achieve high resolution at a low
OSR, we may use multiloop cascaded topologies or multibit
single-loop topologies. In multiloop cascaded topologies,
perfect matching is required between the analog noise-shaping
characteristic and the digital noise cancellation logic. Thus,
multiloop topologies are viable solutions for switched-capacitor implementations, thanks to the excellent matching
properties of on-chip capacitors [12]. However, for continuous-time multiloop cascaded implementations, large RC
time-constant variation introduces mismatch between the
analog noise-shaping transfer function and the digital noise
cancellation characteristic. Significant SNR degradation may
result. On the other hand, single-loop topologies are very
tolerant of nonidealities such as RC time-constant variation and
finite amplifier gain. For these reasons, a single-loop multibit
architecture is chosen in this work.
modulator
Our proposed third-order continuous-time
with multibit internal quantization is shown in Fig. 2. The actual
implementation uses a 5-bit quantizer. The modulator architecture design is derived from a conventional continuous-time
modulator as shown in Fig. 3(a). One clock delay is purposely
introduced in front of DAC_A in the main noise-shaping loop,
YAN AND SÁNCHEZ-SINENCIO: CONTINUOUS-TIME
Fig. 2. Proposed continuous-time multibit
MODULATOR WITH 88-dB DYNAMIC RANGE AND 1.1-MHz SIGNAL BANDWIDTH
77
61 architecture.
Loop filter
Input
x(t)
ADC
@Fs
Output
Y(n)
H(s)
DAC
(a)
ADC
Loop filter
@Fs
Input
x(t)
Output
Y(n)
H'(s)
DAC_B
DAC_A
as illustrated in Fig. 3(b), to accommodate the nonzero time
delay of the internal ADC. To keep the output of the new loop
filter unchanged at the sampling instants, a feedback path is
added from the output to the input of the internal ADC, formed
, where
is the clock period)
by a half clock cycle (
delay and DAC_B. The clock timing diagram of Fig. 3(b) is
shown in Fig. 3(c). A D latch is used in front of DAC_B, as
shown in Fig. 2. When CLK is low, the D latch holds the data;
whereas when CLK is high, it simply works as a digital buffer,
and any change at the input propagates instantly to the output.
Thus, the operation of this modulator is not affected even if the
time delay of the internal ADC varies from zero to nearly one
clock period.
Thanks to the architectural improvements, the total time delay
of the internal ADC and the feedback DAC is relaxed to
nearly one clock period, instead of almost zero in conventional
modulators. Thus, a low-power flash ADC
continuous-time
with longer delay can be tolerated. Note that the total time delay
is given by
z-1/2
z-1/2
(b)
Ts=28.4ns
S/H
(1)
Flash
ADC
,
, and
are the time delays of
where
the ADC, DAC_A, and DAC_B in Fig. 2, respectively. We as.
sume
Because DAC_A is clocked by a clean system clock, any
signal-dependent ADC delay is absorbed by the D latch in front
of DAC_A. Thus, SNR degradation due to signal-dependent
delay and metastability is eliminated or minimized.
Another way to view the proposed architecture can be
explained as follows. The conventional continuous-time
modulator as shown in Fig. 3(a) is redrawn in Fig. 4(a), with
the loop open at the interconnection between the digital output
and the DAC input, as labeled as
. To study the
noise-shaping loop filter, an impulse input
is applied
at the DAC input, as shown in Fig. 4(a) and (b). Usually, the
is obtained through impulse
continuous-time loop filter
invariant transform (IIT) [20]. The loop filter input starts at
, to have valid output values at sampling instants
(
), as illustrated in Fig. 4(c). The sampler
, and the ADC digital output is
samples the analog input at
in close loop. Thus, zero time
immediately needed also at
delay is required for the internal ADC, which is not possible to
DAC_A
DAC_B
(c)
61
Fig. 3. Continuous-time
modulator architectures. (a) Conventional
architecture. (b) Proposed architecture. (c) Clock timing diagram of proposed
architecture (DAC_B is level triggered instead of edge triggered).
realize in the real world. In our proposed architecture, the first
) of the loop filter impulse response
nonzero sample (at
is specially synthesized by DAC_B [Fig. 4(d)], instead of from
[see Fig. 4(f)]. The input of
the output of main loop filter
is delayed by one clock period , starting from
[see Fig. 4(e)]. If we combine the outputs of DAC_B and
together, we can have exactly the same sampled output values
as that shown in Fig. 4(c) at the sampling instants. Thus, the
modulator architecture in Fig. 4(f) can be obtained.
In summary, the proposed architectural solution eliminates
performance degradation due to the nonzero excess loop delay
78
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Loop filter
Input
x(t)=0
ADC
@Fs
TABLE I
COEFFICIENT VALUES OF THE CONTINUOUS-TIME MULTIBIT
ARCHITECTURE IN FIG. 2
Output
Y(n)
H(s)
61
Y'(n)
DAC
(a)
input impulse Y'(n)
time
t=0
Ts
2Ts
3Ts
4Ts
(b)
40
time
20
(c)
STF
time
STF and NTF (dB)
0
(d)
time
(e)
20
NTF
40
60
ADC
Loop filter
@Fs
Input
x(t)=0
H'(s)
DAC_B
DAC_A
z-1/2
80
Output
Y(n)
(f)
z-1/2
0
2
4
6
8
10
12
Frequency (MHz)
14
16
18
Fig. 5. STF (signal transfer function) and NTF (noise transfer function) plots.
Y’(n)
Fig. 4. Loop filter time-domain impulse response (dashed curves are
continuous-time waveforms; dots are sampled values in front of the ADC).
(a) Conventional structure in Fig. 3(a) with loop opened. (b) Loop filter input
. (c) Loop filter output of the conventional architecture. (d) Output of
DAC_B in Fig. 3(b). (e) Output of the main loop filter
. (f) Proposed
architecture in Fig. 3(b) with loop opened.
Y (n)
100
H (s)
and signal-dependent delay of the internal ADC [19]. Or, in
other words, the nonzero excess loop delay is accommodated
in the architecture level design. The power consumption of the
internal multibit flash ADC is effectively reduced, thanks to the
relaxed time delay requirement.
Nonidealities (such as noise, offset, and nonlinearity) of
DAC_B are suppressed by over 50 dB thanks to the high gain
within the signal bandwidth.
of the main loop filter
Thus, DAC_B nonlinearity due to the mismatches is not a
concern in this design. However, nonidealities of DAC_A are
directly superimposed upon the input signal. Thus, DAC_A
requires an accuracy better than the target resolution of the
modulator—14 bits in our case. Proper sizing of the DAC
unity elements and careful layout may only achieve around
10-bit matching accuracy. Dynamic element matching (DEM)
[12] and current calibration (as used in current steering DACs)
[22], [23] are possible solutions to linearize the feedback DAC
(DAC_A). In our design, current calibration is used to achieve
better than 14-bit linearity with the advantages of low power
consumption and simple implementation as compared to DEM
techniques.
The feedback path
shifts two zeros (with conjugate frequencies in the plane) out of dc in the noise transfer function (NTF) to lower overall quantization noise within the signal
bandwidth, and hence improves SNR. Without , large signal
swings have been observed at the outputs of the loop filter inis added, the signal amplitude at the input
tegrators. After
of the internal ADC tends to increase, because the feedforward
is in phase with the signal through the loop
signal through
modulator at low
filter. However, the high loop gain of the
frequencies tries to keep the ADC input signal level relatively
constant by reducing (low-frequency) signal swings at the integrator outputs. Thus, signal swings at the integrator outputs are
is added. With smaller
reduced after the feedforward path
signal swings, the integrator gains of to can be scaled up to
modsuppress circuit noise. The stability of this multistage
ulator is ensured by gradually clipping integrator outputs from
the last stage to the preceding stages when a large signal occurs
at the modulator input. As the stages with clipped outputs do
not contribute to signal gain, the loop filter order can be effectively reduced from the third order to the first order [24]. The
loop filter coefficients are scaled accordingly so that the three
integrators have gradually increased signal levels from the first
stage to the third stage to guarantee stability of the modulator
when a large input signal is presented. The coefficient values of
the proposed architecture in Fig. 2 are listed in Table I. Note that
is the gain of DAC_A, and
is the
in Table I,
gain of DAC_B.
The signal transfer function (STF) and NTF plots of proposed
architecture are shown in Fig. 5. The gain of the STF within
1.1-MHz signal bandwidth varies less than 0.2 dB as simulated.
YAN AND SÁNCHEZ-SINENCIO: CONTINUOUS-TIME
MODULATOR WITH 88-dB DYNAMIC RANGE AND 1.1-MHz SIGNAL BANDWIDTH
79
D. Clock Jitter Sensitivity
Note that the sampling error introduced by the clock jitter
at the internal ADC input1 is significantly suppressed by over
50 dB due to the high gain of the noise-shaping filter at signal
frequencies. Thus, the sampling clock jitter of the internal ADC
will not be considered further in this paper.
However, the timing error of the feedback DAC in the main
loop (DAC_A in Fig. 2) directly degrades the SNR performance
of the modulator. To reduce clock jitter sensitivity, multibit
NRZ—instead of RZ—DAC pulse shaping is utilized. Traditionally, RZ feedback DACs have been used in continuous-time
modulators to overcome inter-symbol interference due
to unequal rising and falling edges of the feedback DAC
waveform. However, a multibit RZ DAC is more sensitive to
clock jitter than a multibit NRZ DAC.
As illustrated in Fig. 6(a), assuming that the duty cycle of the
RZ pulse shaping is 0.5, the amplitude of the RZ DAC has to be
twice as high as that of the NRZ DAC, to keep the area of the
DAC output waveform unchanged. If we assume that the noise
introduced by the random clock jitter has a white spectrum, we
can derive that the SNR improvement (in dB) of NRZ pulse
shaping over RZ pulse shaping as
SNR
dB
Fig. 6. Feedback DAC pulse shaping. (a) NRZ and RZ pulse shaping for a
multibit DAC. (b) Symmetric rising and falling edges of a fully differential
signal.
(2)
where
is the variance of the NRZ DAC output
current, and
is the variance of
[see
Fig. 6(a)].
Behavioral level simulations reveal that, with 20-ps rms clock
modujitter and 5-bit internal quantization, the SNR of the
lator with a 5-bit RZ DAC is 66.5 dB, whereas SNR improves to
89 dB if a 5-bit NRZ DAC is used. Ref. [6] does not disclose the
SNR that can be achieved by 7-ps rms clock jitter. If we assume
the achieved SNR is their SNR target of 70 dB over 200-kHz FM
bandwidth and 90 dB over 9-kHz AM bandwidth [6], and that
half of the noise power is contributed by circuit noise, the clock
jitter sensitivity of our architecture is reduced by 33 dB. This is
in good agreement with intuitive estimation of the improvement
by the 5-bit quantization and NRZ DAC pulse shaping.
The advantage of RZ feedback DAC pulse shaping over NRZ
pulse shaping is the immunity of the RZ DAC to asymmetry of
DAC rising and falling edges [4]. In fact, in a carefully designed
fully differential system, as illustrated in Fig. 6(b), even though
and
may have different rising and falling slopes [25],
the rising and falling edges of the differential signal (
) are intrinsically symmetric.
If we simply replace the RZ DAC in earlier
architectures
[4], [5] with an NRZ DAC, nonzero (signal-dependent) quantizer delay may result in SNR performance degradation or even
instability [19], [20]. As discussed earlier, our proposed architecture in Fig. 2 solves this zero time delay problem of the internal ADC and the DAC. Instead, the maximum total delay of
the ADC and the DAC is relaxed to nearly one clock period.
1In real implementation, the internal flash ADC is preceded by a
sample-and-hold (S/H) circuit.
Fig. 7.
Simulated SNR versus normalized RC time constant.
E. SNR Versus Normalized RC Time Constant
modulator with
The simulated SNR performance of the
dB input signal (only quantization noise is considered)
versus the normalized RC time constant associated with the
loop filter is shown in Fig. 7. The transfer functions of the
(
), where
has a
integrators in Fig. 2 are
nominal value of , the system clock period. If the integrator
deviates from its nominal value, the
time constant
system performance degrades as shown in Fig. 7. The axis
in Fig. 7 is
, the normalized time constant; and axis is
modulator SNR. When the RC time constant
the simulated
is smaller, a better SNR may result due to the higher loop filter
gain. However, the system becomes unstable when the RC
time constant decreases to approximately 0.88. If the RC time
constant is larger than nominal, although the modulator is more
stable, less efficient noise shaping results due to smaller loop
filter gain, and hence the SNR performance degrades.
shown in Fig. 2 has been optimized
The feedback path
for a flat and high SNR with a normalized RC time constant between 0.95 and 1.15, as illustrated in Fig. 7. In real design, the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
M 9 M 10
M7
M8
V CMFB1
DAC_A
RZ
IDAC_A-
vI1+
vI1-
CI1
RIN
v O1-
vO1vIA1+
RIN
IDAC_A+
v O1+
M3
vIA1-
vO1+
M4
v IA1+
M1
RZ
CI1
IBIAS
M6
M5
M 11 M 12
bias
circuit
M2
v IA1-
DAC_A
(a)
(b)
M 13
Fig. 8. First-stage integrator. (a) Overall structure. (b) Telescopic amplifier used in (a).
normalized RC time constant is set to 1.05, rendering a system
time constant tolerance for only 2-dB SNR variawith a
tion. CMOS technologies usually do not have tight control over
absolute values of Rs and Cs, so an automatic RC time constant
tuning circuit is needed to achieve assured performance without
any in-factory trimming or calibration. In practice, circuit noise
usually dominates the total noise budget, thus, the SNR of the
modulator has even less dependence on RC time
realized
constant variation.
III. CIRCUIT DESIGN AND IMPLEMENTATION
The implementation of the proposed continuous-time
modulator architecture as depicted in Fig. 2
multibit
involves the circuit design of a number of building blocks,
including the noise-shaping loop filter, RC time constant
tuning circuit, sample-and-hold (S/H) circuit, flash quantizer,
current steering feedback DACs, and DAC current calibration
circuit. Extensive behavioral-level simulations using Matlab
SIMULINK and macromodeling in Cadence have been performed to extract performance requirements for the various
building blocks. Transistor-level circuit design then followed
to meet the system-level requirements.
A. Noise-Shaping Loop Filter
There are three practical continuous-time integrator struc-C; and 3) MOSFET-C integrators.
tures: 1) active-RC; 2)
Active-RC integrators have the advantages of better linearity
-C integrators usually can
and larger signal swing, whereas
operate at higher frequencies with less power consumption.
MOSFET-C integrators, which have the advantage of continuous time-constant tunability at the cost of higher nonlinearity,
are not used in our design due to the high linearity requirement
in our design. Three integrators in Fig. 2 have decreasing performance requirements (in terms of noise, offset, and linearity)
from the first stage to the third stage. Noise and linearity of
the entire modulator is primarily determined by the first-stage
integrator, thus an active-RC integrator is chosen for its excellent linearity [4]. The second- and third-stage integrators
- type, because their nonidealities are noise shaped
are of
by the first order and the second order, respectively, and the
performance requirements are relaxed.
1) First-Stage Integrator: Thanks to the high input
impedance of subsequent transconductor stages, the amplifier
in the first-stage active-RC integrator does not need to drive a
pure resistive load as in the case of all active-RC structures,
thus a simple single-stage amplifier can be used. A telescopic
amplifier structure was chosen for its fast speed operation and
low power consumption [Fig. 8(b)]. Since there are five layers
of transistors cascoded between supply rails, the telescopic
structure has the disadvantage of low signal swing. Yet this is
not a problem in our design: system level simulations reveal
that the output signal swing of the first-stage integrator is
V with a full-scale input, while the maximum output
swing of the amplifier is more than 1.5 V (on each side),
over three times larger than the highest possible signal swing.
There are two benefits of this arrangement. First, the amplifier
operates at the central linear part of the input/output transfer
around
characteristic. The open loop gain varies within
1.8 kV/V (65.1 dB) as simulated, thus very good closed-loop
linearity can be obtained. Second, the large voltage headroom
keeps the first integrator in the active mode to maintain stability
of the system, even when the second- and the third-stage
integrators saturate due to a large input signal [24]. The ’s in
Fig. 8 are small value resistors of around 100 , to cancel the
right-half-plane zero in the integrator transfer function.
The feedback current-steering DAC_A injects output current
to the amplifier input (virtual ground) of the first-stage integrator [Fig. 8(a)]. In a current steering DAC, as different numbers of current sources branch to the DAC output with different
input digital codes [26], the DAC presents varying finite output
impedance, and thus signal distortion may result. This effect is
significantly reduced by the low impedance at the virtual ground
input of the amplifier.
2) Second- and Third-Stage Integrators: The second- and
third-stage integrators do not require high linearity, therefore
- integrators for low power conthey are implemented as
sumption. Nonidealities (such as offset, noise, and nonlinearity)
YAN AND SÁNCHEZ-SINENCIO: CONTINUOUS-TIME
M9 M10
M105
MODULATOR WITH 88-dB DYNAMIC RANGE AND 1.1-MHz SIGNAL BANDWIDTH
M104
to CMFB of
1st stage
M103
psrc1
RS2
VCMFB1
A1a
M11 M12
VCM1
vO1+
vO1-
M102
M101
1st-stage
integrator
amplifier
output stage
RS2
A
M
M21
1b
22
vO2-
vO2+
M23
M24
A2
CI2
4p
simplified CMFB circuit
of the 1st-stage integrator
Fig. 9.
vO1+
(vI2+)
81
2nd stage
integrator
vO1(vI2-)
CI2
4p
Vb
VCMFB2
M23
M24
Second-stage integrator and CMFB circuit for the first-stage integrator.
of the second-stage integrator are attenuated by the gain of the
first-stage integrator, around 20 dB at 1.1 MHz. Nonidealities
of the third-stage integrator are suppressed by the cascaded gain
(35 dB in our design) of the first- and second-stage integrators.
Although the second-stage integrator performance requirements are relaxed compared with the first stage, care should be
taken to ensure that its nonlinearity does not degrade the performance of the entire modulator. Resistive source degeneration
is used in the operational transconductance amplifier (OTA).
PMOS transistors are chosen as the input transistors, as the substrate terminal of a PMOS transistor can be tied to the source
terminal in this n-well CMOS technology, to avoid any body
modulation effect. Amplifiers A1a and A1b in Fig. 9 are added
to improve the linearity of the OTA. As they only drive the gates
of the input PMOS transistors, small quiescent current is consumed. Thermal and flicker noise of amplifiers A1a and A1b
are not an issue, because the noise referred to the modulator
input are attenuated by the gain of the first-stage integrator at
signal frequencies. Due to the relatively large (
)
source degeneration resistors (
’s in Fig. 9), the integrator
DC gain is only 30 dB without A2. By adding A2, the integrator
dc gain improves to over 80 dB. Amplifiers A1a, A1b, and A2
are simple single-stage amplifiers with a gain of approximately
60 dB. The third-stage integrator is a scaled-down version of the
second-stage integrator.
3) Common-Mode Feedback: The common-mode feedback
(CMFB) circuit for the first-stage integrator is shown in Fig. 9.
The common-mode voltage [27] is extracted from node psrc1
’s). Care has
between the two source degeneration resistors (
been taken to ensure enough phase margin of the CMFB loop,
which is better than 60 degrees in our design. The unity-gain
bandwidth of the CMFB circuit is similar to that of the differential path to ensure a stable common mode output voltage. CMFB
circuits for the second- and third-stage integrators have similar
structures.
B. RC Time Constant Tuning
As discussed in Section II-E, automatic tuning is needed to
modulator stability and SNR performance over
ensure the
RZ
CMAIN
CI
R IN
CI
8CLSB
vO
vI
4CLSB
2CLSB
R IN
(a)
RZ
CI
4 bit control
word
CLSB
(b)
Fig. 10. RC time constant tuning. (a) Active-RC integrator. (b) Discretely
tunable capacitor.
large RC time constant variations. Transconductance tuning in
- filters and MOSFET tuning in MOSFET-C filters are
widely used in continuous-time filters. However, due to nonlinearity associated with active components, the achievable linearity (on the order of 60 dB) of these filters cannot satisfy
our design requirements. Therefore, a discrete capacitor tuning
scheme [28] is employed to calibrate the time constant of the ac- integrators. Measured data from MOSIS of
tive-RC and
polysilicon resistance and poly–poly capacitance of this 0.5- m
CMOS technology reveal that the RC product maximum/minimum ratio is around 1.3. Leaving enough safe margin for a
successful first-time silicon realization, we chose RC product
tuning range to be 2.0. As shown in Fig. 10, each integration
capacitor in the noise-shaping loop filter is actually a capacitor
bank that can be tuned by a 4-bit control word for a tuning ac.
curacy of better than
C. Current Summation and Sample-and-Hold Circuits
The current summation circuit in front of the 5-bit flash ADC
is shown in Fig. 11. Output currents of feedforward paths to
(see Fig. 2) add at nodes A and B, and then the currents are
folded up to drive two resistors ( ’s). is implemented with
, A3-A5, and two
’s.
and
in Fig. 11
correspond to the In signal in Fig. 2. Simple single-stage amplifiers A3–A5 are used to improve linearity. The S/H amplifier
following the current summation circuit uses a double sampling
82
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 11.
Current summation and sample-and-hold circuit.
VG1A
0.8V
iO+
M1A
VG1B
VS
M1B
VG1A
Conventional switching scheme
VG1B
ITAIL VS
MB2
VG1A
0.8V
iO-
slower falling
edge
VG1B
MB1
VS
High crossing switching scheme
Fig. 12.
High crossing switching scheme for current steering DACs.
technique to relax the amplifier bandwidth requirement.
in Fig. 11 is the input common-mode voltage of the sampling
network. The S/H output drives a 5-bit flash ADC, whose thermometer code output feeds the feedback DACs.
D. Feedback DACs and Current Calibration
DAC_A and DAC_B are implemented as current steering
DACs for two reasons: 1) their potential for high-speed operation and 2) the convenience to interface the DAC output
current with the continuous-time loop filter. Reduced-swing
high crossing current switch drivers, as shown in Fig. 12, are
utilized to minimize clock feedthrough effect and transient
glitch energy [23]. The crossing point of the two switch control
signals is increased by slowing down the falling edge of the
control signals [29], to reduce glitch energy due to charging
and discharging parasitic capacitance at the drain node of the
) as shown in Fig. 12. The parasitic
tail current source (
capacitance at the drain node of the tail current source is min(2 (4.5 m/0.6 m))
imized through proper sizing of
and
(4.2 m/0.6 m). When
and switch transistors
a switch transistor is turned on, it works in the saturation region
instead of the linear region to provide an additional level of
cascoding for a high output impedance.
Even though DAC_A is a 5-bit DAC, its linearity must exceed 14 bit. Any nonlinearity of DAC_A will introduce distortion or raise the noise floor of the entire modulator. Low
cost CMOS technologies usually offer 10-bit matching accuracy. Current calibration is used to improve the matching accuracy of the current sources from 10 to 14 bits. The current calibration principle is illustrated in Fig. 13(a) [22]. In calibration
turns to the center tap and
closes.
mode, switch
and
The current difference between the reference current
(usually 90%–97% of
) is forced
the drain current of
to flow through
, with a certain
on
.
actu. In output mode,
ally can be the gate capacitance of
opens and
turns left or right (depending on the input data
or
(positive or negative DAC output). As
bit) to
of
is preserved on
, the drain current of
remains
and
remains
unchanged, thus the total current through
. An extra spare current source is added as shown
equal to
in Fig. 13(b), which takes the position of the current source that
is being calibrated, thus operation of the DAC is not interrupted.
All the current sources, including the spare one, are calibrated
one by one continuously and periodically by the same reference
.
current source
Earlier current calibration circuits [22], [23] similar to Fig. 13
have the following drawbacks [26]. First, enough current margin
must remain to leave enough safe margin for the drain current
. If
conducts a drain current larger than
through
due to random mismatch, the calibration circuit will fail to operate. On the other hand, conservative design with a large drain
will render a larger
for
, which results
current of
.
in the drain current being more sensitive to variations in
Moreover, because of the single-ended design, the matching of
unity currents through different cells suffers from nonuniform
clock feedthrough (due to mismatches associated with the
switches in different cells) and the voltage drop on
capacitors during calibration intervals. Hence, DAC linearity degrades, and distortion is introduced. A differential bidirectional
current calibration circuit proposed by Razavi [26] overcomes
the above drawbacks. Fig. 14(c) depicts the current calibration
circuit revised from Razavi’s scheme. Because the OTA formed
to
can source or sink output current,
conducts
by
instead of slightly
a drain current with a nominal value of
. The output current of the OTA is not sensismaller than
tive to the common-mode voltage change at the inputs because
capacitors drop at similar rates.
voltages on the two
The schematic of the high crossing switch driver is shown in
Fig. 14(a). D-flip-flops precede the switch drivers to synchro-
YAN AND SÁNCHEZ-SINENCIO: CONTINUOUS-TIME
Fig. 13.
MODULATOR WITH 88-dB DYNAMIC RANGE AND 1.1-MHz SIGNAL BANDWIDTH
83
Conventional DAC current calibration. (a) Calibration principle. (b) DAC overall structure.
Fig. 14. Schematics of DAC_A current cell circuit. (a) High crossing switch driver. (b) D-flip-flops to synchronize current switches and inverters to reduce
interference from the noisy digital supply. (c) Differential bidirectional current calibration circuit revised with DAC current steering switches.
nize the switching of the current cells as shown in Fig. 14(b).
Since the digital supply may have voltage transients on the order
of hundreds of millivolts, due to large digital current spikes
through the supply rail impedance, the D-flip-flops are followed
by inverters that are powered by a dedicated supply to provide
isolation between the switch drivers and the noisy digital circuits. The clock which drives the feedback DAC_A is the most
critical clock signal in the entire modulator, because any clock
jitter or timing error will modulate the DAC output pulsewidth,
and hence introduce noise or distortion. Thus, a clock buffering
scheme similar to the scheme employed in [23] was adopted to
minimize the clock jitter at DAC_A caused by thermal noise of
the clock buffers.
DAC_B has a relaxed requirement for matching accuracy due
to the noise shaping at the summing node in front of the quantizer, thus current calibration is not needed.
84
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004
Fig. 16. Measured power spectrum density (65536-point FFT) plots with
) and 2:4-dB (1.82 V
) input signals.
100-kHz 33-dB (54 mV
0
Fig. 15. Chip microphotograph. The chip area is 2.4
the pads.
2 2.4 mm
0
not including
IV. EXPERIMENTAL RESULTS
The continuous-time
modulator has been fabricated in
a 0.5- m n-well double-poly triple-metal CMOS technology
through MOSIS. The chip microphotograph is shown in Fig. 15,
with a die area (excluding the pads) of 2.4 2.4 mm . In the
layout, care has been taken to isolate noisy digital circuits and
sensitive analog function blocks. Unused silicon areas are filled
with capacitors for decoupling power supplies. To minimize
possible switching noise interference from the system clock
input, the clock signal is applied to the chip using a low-swing
fully differential sinusoidal signal instead of full-swing digital
pulses. The input sinusoidal clock signal is amplified and
clipped to full logic swing inside the chip. The 5-bit output of
the internal quantizer also consists of low swing differential
signals, which are amplified to full digital swing by off-chip
comparators assembled on the custom PCB board.
The experimental output PSD plots (65536 bins from 0 to )
with 100 kHz
-dB (54 mV
) and
-dB (1.82 V
)
input signals are depicted in Fig. 16. The full scale input am, which is also the differential
plitude (or 0 dB) is 2.4 V
full-scale input range of the internal ADC. Measured SNR and
signal-to-noise-plus-distortion ratio (SNDR) versus input signal
level at 100 kHz are shown in Fig. 17. No idle tones have been
observed during the testing even when the input level is zero
(modulator input terminated with a 50- resistor).
Fig. 18 shows the two-tone inter-modulation test. The two
frequencies are 800 and 825 kHz, and the signal levels are both
dB (0.795 V
). From the PSD plot, IM3 components at
least 80 dB lower than the signal level are observed. The same
intermodulation spectrum was observed on a Rohde & Schwarz
FSEB spectrum analyzer, when the combined signal was applied
directly to that analyzer. That means the input signal applied to
Fig. 17. Measured SNR (top curve) and SNDR (bottom curve) versus input
signal level at 100-kHz.
the
modulator was not clean enough. Thus, the measurement results might be limited by the test setup.
modulator achieves 88-dB dyThis continuous-time
namic range,2 84-dB SNR, 83-dB SNDR, and 93-dB SFDR
over 1.1-MHz signal bandwidth with an oversampling ratio of
16, while dissipating 62 mW from a 3.3-V supply. Experimental
results are summarized in Table II. All 36 prototype chips from
MOSIS work and reach the full 14-bit SNR performance.
modulaA performance comparison of continuous-time
tors published in recent years is depicted in Fig. 19. Note that
11 and 5.5 times improvement in the signal bandwidth has been
achieved compared with [5] and [6], respectively. Because this
modulator, we
is the first time we have ever implemented a
were very conservative in the design to make sure that the first
silicon realization would work. Thus, the power consumption
2The dynamic range is defined as the signal level difference (in dB) between
the full scale input and the input signal level when SNR is 0 dB.
YAN AND SÁNCHEZ-SINENCIO: CONTINUOUS-TIME
MODULATOR WITH 88-dB DYNAMIC RANGE AND 1.1-MHz SIGNAL BANDWIDTH
85
0
20
dB/bin
40
60
80
100
120
140
6
6.5
7
7.5
8
8.5
Frequency (Hz)
9
9.5
10
10.5
5
x 10
Fig. 18. Output spectrum of two-tone inter-modulation test (at 800 and
825 kHz).
Fig. 19. Dynamic range comparison with recent continuous-time
publications [4]–[6], [21], [30].
TABLE II
PERFORMANCE SUMMARY
61
ACKNOWLEDGMENT
The authors acknowledge Y. Li, B. Xia, Y.-I. Park, T.-C. Tan,
and L. Wang for their technical help, support, and discussions.
They are very grateful to the anonymous reviewers for their
valuable suggestions and comments to improve the quality of
this paper. Thanks also go to A. Tate and B. Trotter for their
time spent in proofreading the draft of this article. The prototype IC chips were fabricated through MOSIS. The cordial assistance and support from V. C. Tyree and other staff members
at MOSIS are greatly appreciated.
and silicon area are not optimal. For example, the flash quantizer
works well at over 100-MHz clock frequencies as simulated,
whereas the actual clock frequency is only 35.2 MHz. Power
consumption can be further reduced in future implementations.
V. CONCLUSION
A continuous-time
modulator with an enhanced architecture achieving an 88-dB dynamic range over a 1.1-MHz
input signal bandwidth has been proposed and implemented
in a 0.5- m CMOS technology. Highlights of the proposed
architecture include: 1) multibit quantization is deployed to
improve resolution and bandwidth; 2) NRZ feedback DAC
pulse shaping and multibit quantization are utilized to reduce
clock jitter sensitivity; 3) the excess loop delay problem of
modulators is eliminated
conventional continuous-time
by the proposed loop filter architecture; 4) a sound continuous-time noise-shaping loop filter design with discrete-tunable
capacitors achieves a high and stable SNR over large process
variations. Clock jitter sensitivity of the proposed architecture
is improved by around 33 dB over prior work [6] as simulated
and calculated. Experimental and theoretical results are in good
agreement.
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61
Shouli Yan (M’98) received the B.S. degree in electronic engineering and the M.S. degree in computer
science and engineering, both from Shanghai Jiao
Tong University, P. R. China, in 1992 and 1995,
respectively, and the Ph.D. degree in electrical
engineering from Texas A&M University, College
Station, in 2002.
He has been with the Department of Electrical
and Computer Engineering, University of Texas at
Austin, as an Assistant Professor, since 2002. He
was a Lecturer and Researcher with the Department
of Electronic Engineering, Shanghai Jiao Tong University, from 1995 to 1997.
He worked as a Graduate Research and Teaching Assistant at the Department
of Electrical Engineering, Texas A&M University, from 1997 to 2002. In fall
1999, he was with Mixed-Signal Products, Texas Instruments, Inc., Dallas,
as a Design Engineer for his internships. His research interests include data
conversion, RF circuits, and high-performance analog and mixed-mode
integrated circuits.
61
61
Edgar Sánchez-Sinencio (M’74–SM’83–F’92) was
born in Mexico City, Mexico. He received the degree in communications and electronic engineering
(Professional degree) from the National Polytechnic
Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, Stanford, CA, and the
Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1966, 1970, and 1973, respectively.
In 1974, he held an industrial Postdoctoral position with the Central Research Laboratories, Nippon
Electric Company, Ltd., Kawasaki, Japan. From 1976
to 1983, he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He is currently the Kilby Chair Professor and Director of the Analog and Mixed-Signal
Center, Texas A&M University, College Station. He is a coauthor of the book
Switched Capacitor Circuits (New York: Van Nostrand-Reinhold, 1984), and
co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems
(New York: IEEE Press, 1999). He has been the author and co-author of 108
journal papers and 192 conference papers. His current research interests are
in the area of RF-communication circuits and analog and mixed-mode circuit
design.
Dr. Sánchez-Sinencio is the former Editor-in-Chief of the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II. He is a former
IEEE Circuits and Systems Society Vice President–Publications. In November
1995, he was awarded an Honoris Causa Doctorate by the National Institute
for Astrophysics, Optics and Electronics, Mexico, the first honorary degree
awarded for Microelectronic Circuit Design contributions. He was corecipient
of the 1995 Guillemin-Cauer Award for his work on cellular networks. He
was also the corecipient of the 1997 Darlington Award for his work on
high-frequency filters. He received the IEEE Circuits and Systems Society
Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society
Representative to the Solid-State Circuits Society (2000–2002), and is currently
a member of the IEEE Solid-State Circuits Award Committee.