SFR Access
External SFR registers will be used for communication between the micro-controller and
the video pipeline. These external registers will be found in this block, where the microcontroller has read access and the pipeline will have write access.
Interface Signals
Signal Name
clk
reset
Type
Input
Input
Bits
Description
1 System Clock 50 MHz
1 System Reset
PIPE_DATAX
PIPE_DATAY
newframe
Input
Input
Input
8 X coord. to be sent into micro-ctrl
8 Y coord. to be sent into micro-ctrl
1 Frame delimiter
sfr_rd
sfr_wr
sfr_addr
Input
Input
Input
1 micro-cntrl sfr read signal
1 micro-cntrl sfr write signal
8 micro-cntrl sfr address line
SFR_INT
SFR_DATA
Output
Output
1 interrupt signal to micro-cntrl
8 data line into micro-cntrl
Functional Description
When the pipeline has a new value for the x, y coordinates for communication to the
master board, that information needs to get read into the micro-controller. Currently,
once a newframe signal is received, this block will set an interrupt on the microcontroller. The interrupt routine will then attempt to access two external registers reading
off the x, y coordinates. These registers (A9 and B9 respectively), are unused SFR
registers. The micro-controller will interpret these reads as external SFR reads and will
go outside the micro-controller to read the registers. This SFR_Access block is listening
on the SFR bus for these requests and will put the correct data on the SFR_DATA_IN
line where the micro-controller will complete the read.
Interface Timing
See Figure 1. Once a newframe delimiter is received from the pipeline, an interrupt is set
on the micro-controller. The interrupt routine will attempt to read external SFR registers
and this block will respond by putting the correct data on the SFR_DATA_IN line
(micro-controller interface). Notice that the communication with the micro-controller
needs to take into account the clock speed of the micro-controller at 12.5 MHz and this
block’s 50 MHz clock. The DW8051 spec sheet at:
http://www.cs.washington.edu/education/courses/477/02sp/docs/DW8051_databook.pdf
Shows the timing for external SFR reads on the DW8051 (page 200).
Figure 1. Timing Diagram for SFR_Access
a. newframe is asserted, X and Y coordinates are registered internal to SFR_Access
b. sfr_int is asserted, driving an interrupt routine in the micro-controller that will
eventually read the external x,y coordinate SFR registers. sfr_int must be held high for
16 clock cycles to ensure that the much slower micro-controller sees the interrupt.
c. the sfr_rd finally comes and the x-coordinate is grabbed first.
d. the Y coordinate is put on the sfr_data line knowing that the next external SFR read
will be to that register.