IEEE UGIM Symposium Program
Morning
Boise River Festival
Sun,
June 29
Mon,
June 30
7:30-8:30 Registration & Breakfast (Student
Union, Jordan Ballroom)
8:30-10:10
Session 1: Plenary (Jordan BC)
10:20-12:00
Session 2: Microelectronics Research and
Education Partnerships (Jordan BC)
Tues,
July 1
7:30-8:30 Breakfast (Jordan)
8:30-10:10
Session 5: Microelectronics Education I (Jordan
BC)
10:20-12:00
Session 6: Microelectronics Education II (Jordan
BC)
Wed.,
July 2
7:30-8:30 Breakfast (Engineering ET110)
8:30-10:10
Session 9: SOI Devices (ET 110)
10:20-12:20
Session 10: MEMs and Sensors (ET 110)
Session 1:
June 29-July 2, 2003
Afternoon
2:00-4:00
Lab Managers Workshop (Engineering ET 110)
“Microlab Management: How I do it” Katalin Voros
4:00-5:00
Idaho Microfab Lab Tours (ET 110)
6:00-10 Boise River Festival Finale Show & Fireworks
12:00-1:30 Lunch (Tablerock),Poster Session (Jordan A)
1:30-3:10
Session 3A: Semiconductor Processing I (Jordan B)
Session 3B: CMOS Mixed-Signal Circuits (Jordan C)
3:20-5:00
Session 4A: Semiconductor Processing II (Jordan B)
Session 4B: SOI Mixed-Signal Circuits (Jordan C)
5:00 Evening Free
12:00-1:30 Lunch (Tablerock),Poster Session (Jordan A)
1:30-3:10
Session 7A: Nano/BioTechnology (Jordan B)
Session 7B: Devices & Materials I (Jordan C)
3:20-5:00
Session 8A: Packaging (Jordan B)
Session 8B: Devices & Materials II (Jordan C)
6:00-9:00
Basque Cultural Banquet (Downtown Basque Block)
12:20 Symposium Adjourns
Plenary Session
Co-Chairs:
Stephen Parke, Boise State University
James Zhou, Georgia Institute of Technology
Tom Jiang, Micron Technology
1.1
Sustaining the Silicon Revolution: Challenges and Opportunities
Tsu Jae King, University of California, Berkeley
1.2
Mutual Dependence, Mutual Success: Collaboration Benefits All
Steve Appleton, Micron Technology CEO
1.3
It’s the Little Things That Matter
Larry Craig, Idaho’s Senior Senator
Session 2:
Boise State University
Microelectronics Research & Education Partnerships
Co-Chairs:
Beau Farmer, New Jersey Institute of Technolog
Robert Pearson, Virginia Commonwealth University
2.1
The MESA Institute – A University Partnership Program for Microsystems
Regan Stinnett, Sandia National Laboratories
2.2
WIMS Comprehensive Education Program
Leo C. McAfee, Jr., University of Michigan
2.3
Building Academic, Research, and Commercialization Programs in Micro
and Nano Science and Engineering at the University of Utah
Ian R Harvey, Mark S. Miller, Steve Blair, Bruce K. Gale, Tim Ameel, Terry Ring, University of Utah
2.4
Laboratory Facilities of the Microsystems Technology Laboratories (MTL) at Massachusetts
Institute of Technology
Vicky Diadiuk, Massachusetts Institute of Technology
2.5
Workforce Development: A Professional Training System Integrating High Technology
Industry and Academia
Andrew Hoff, Richard Gilbert, Eric Persson, University of South Florida;
Nihat Gurmen, University of Michigan
Session 3A:
Semiconductor Processing I
Co-Chairs:
John Shott, Stanford University
Jagdish Prasad, AMI Semiconductor
3A.1
Coral-Software to Help Operate and Manage Advanced University Laboratories
Bill Murray, Mike Bell, John Shott, Stanford University
Ike Lin, Tom Lohman, Massachusetts Institute of Technology
3A.2
Surface Preparation Solutions for Sub-90nm IC Technology
E.G. Baiya, J.J. Rosato, M.R. Yalamanchili, SCP Global Technologies
3A.3
Characterization of the Effect of TiN Oxidation on Via Resistance
Krishna Gunturu, Thomas Haskett, Todd Corsetti, Mike Engle, Jagdish Prasad, AMI Semiconductor
3A.4
SU-8 as an Electron Beam Lithography Resist
Fred Williamson, Eric A. Shields, University of Minnesota
3A.5
Resist Process Characterization and Optimization for ArF Lithography
Charles Manu, Micron Technology, Inc.
Session 3B:
CMOS Mixed-Signal Circuits
Co-Chairs:
Ben Blalock, University of Tennessee, Knoxville
Craig Christensen, AMI Semiconductor
3B.1
Mixed Signal Design in the Microelectronics Curriculum
R. Jacob Baker, Boise State University
3B.2
A Low Power, Low Datarate Integrated 433 MHz RF Transceiver in CMOS
Craig Christensen, AMI Semiconductor
3B.3
System Approach for Low 1/f Noise, High IP2 Dynamic Range CMOS
Mixer Design Andrei R. Petrov, AMI Seimconductor
3B.4
Quick Start Crystal Oscillator Circuit
Shane Blanchard, AMI Semiconductor
3B.5
Clock and Data Recovery Circuits with Fast Acquisition and Low Jitter
Ruiyuan Zhang, George La Rue, Washington State University
Session 4A:
4A.1
Semiconductor Processing II
Co-Chairs:
John Shott, Stanford University
Jagdish Pradsad, AMI Semiconductor
A Laboratory Information Management System (LIMS) for an Academic
Microchip Fabrication Facility
Robert W. Hendricks, Matthew R. Learn, Virginia Polytech and State University
4A.2
High Resolution Metal Lift-Off Characterization
Akil K. Sutton, Steven Steen, IBM T.J. Watson Research Center
4A.3
Manufacturing Reliable Unlanded Vias Without CVD Barrier Layers
Mark Nelson, Jagdish Prasad, Brett Williams, Keith Ross, Deborah Florence,
AMI Semiconductor
4A.4
A Novel Clustering and Declustering Algorithm for Fuzzy Classification of
Wafer Defects Tarek A. El Doker, David R. Scott, Northern Arizona University
4A.5
Experimental Investigation of the Mechanism for CMP Micro-Scratch
Formation Shayne Aytes, Keith Mortensen, John Naughton, Jim Armstrong, Chuck Russell, Keith Ross,
John Giraud, Don Hooper, Harriet Alexander, Todd Corsetti, Mark Nelson, Mike Engle, John Spicer,
Jagdish Prasad, AMI Semiconductor
Session 4B:
4B.1
SOI Mixed-Signal Circuits
Co-Chairs:
Ben Blalock, University of Tennessee, Knoxville
Craig Christensen, AMI Semiconductor
Micropower, Low-Noise, SOI CMOS Preamplifiers for Deep Space Missions
D.M. Binkley, D.H. Ihme, University of North Carolina, Charlotte
B.J. Blalock, University of Tennessee, Knoxville
M.M. Mojarradi, Jet Propulsion Laboratory
4B.2
A 435MHz High-Gain Low-Power LNA in 0.35um SOI CMOS
Douglas Huang, Ertan Zencir, Numan Dogan, NC A&T State University
Ercument Arvas, Syracuse University
4B.3
High Voltage Bandgap Reference Design Using Microwave SOI Technology
Vinesh Sukumar, Dong Pan, David Cox, Herbert L. Hess, Harry W. Li, Kevin Buck, Seeni Subramanium,
University of Idaho
M.M. Mojarradi, Jet Propulsion Laboratory
4B.4
Development of Robust Analog Electronics at the University of Tennessee for
NASA/JPL Extreme Environment Applications
S.C. Terry, B.J. Blalock, J.R. Jackson, S. Chen, University of Tennessee Knoxville
M.M. Mojarradi, E.A. Kolawa, Jet Propulsion Laboratory
4B.5
A Low Voltage to High Voltage Level Shifter Circuit for MEMS Application
Dong Pan, Micron Technology
Harry W. Li, Bogdan M. Wilamowski, University of Idaho
Session 5:
Microelectronics Education I
Co-Chairs:
Karl Hirschman, Rochester Institute of Technology
Siddhartha Duttagupta, Indian Institute of Technology, Bombay
5.1
Training at a University Research Center: The interface between users
and facilities Zhiping (James) Zhou, Georgia Institute of Technology
5.2
Semiconductor Process and Device Modeling: A Graduate Course/
Undergraduate Elective in Microelectonic Engineering at RIT
Karl D. Hirschman, Jeremiah Hebding, Robert Saxer, Keith Tabakman,
Rochester Institute of Technology
5.3
Use of the Myers-Briggs Type Indicator in an Undergraduate
Microelectronics Course, Robert E. Pearson, Virginia Commonwealth University
Anthony J. Bell Jr., John R. Croley, DuPont Kevlar
5.4
A Lecture and Hands-On Laboratory Course: Introduction to
Micromachining and MEMS
Jack W. Judy, Paulo S. Motta, UCLA
5.5
Hands-On MEMS
Luc Frechette, Vijay Modi, Columbia University
Floyd Miller, Lehigh University
K.R. Farmer, New Jersey Institute of Technology
Session 6:
Microelectronics Education II
Co-Chairs:
Karl Hirschman, Rochester Institute of Technology
Siddhartha Duttagupta, Indian Institute of Technology, Bombay
6.1
Past and Current Status of Microelectronics Education for Undergraduates
Lynn Fuller, Rochester Institute of Technology
6.2
Challenges and Opportunities for Universities to Support Future Technology
Developments in the Semiconductor Industry: Staying on Moore's Law
Jagdish Prasad, AMI Semiconductor
6.3
Testing of Metal Gate PMOS Digital Integrated Circuits
Lynn Fuller, Kekuut Hoomkwap, Sushil Shakya, Suebphong Yenrudee,
Rochester Institute of Technology
6.4
Optimization of Contact Interface Resistance for CMOS Circuits
Akil K. Sutton, Biren C. Patel, Devin K. Brown, Leslie O. George, Zhiping Zhou,
Eric V. Woods, Georgia Institute of Technology
6.5
The High School Technology Initiative: A novel approach to encourage
students to follow science and technology career paths
Andrew M. Hoff, Richard Gilbert, Eric Roe, University of South Florida; Marilyn Barger, Hillsborough
Community College; Michael Lesiecki, MATEC
Session 7A:
Nano/Biotechnology
Co-Chairs:
Greg Cibuzar, University of Minnesota
Doug Hackler, American Semiconductor, Inc.
7A.1
Development of a New Technique for DNA Single Base Pair Mismatch Analysis
Greg Cibuzar, Mark Fisher, Fred Williamson, Martin Blumenfeld, Piratheepan Suntharalingam, Jesse R.
Grenz, Brian G. Van Ness, Kyoung Joon Kim, Avram Bar-Cohen, Eric Eccleston, University of Minnesota
7A.2
Bridging the Gap between Classical and Quantum Transport in Nanoscale MOSFETs:
Schrodinger Equation Monte Carlo-2D
Leonard F. Register, Wanqiang Chen, Sanjay K. Banerjee, University of Texas Austin
7A.3
An Interdigitated Electrode Detector for the Identification of a Single Specific DNA Molecule
Fragment
Lynn Fuller, Reinaldo Vega, Robert Manley, Vee Chee Hwang, Dan Jansen, Rochester Institute of
Technology; An Pham, Nate Wescott, Mike Connelly, Integrated Nano-Technologies, LLC
7A.4
Modeling the Effects of Quantum Exchange in Nanoscale Spaced Double-Quantum-Well Systems
J.R. Rodriguez, J.C. Diaz-Velez, C.B. Hanna, Boise State University
7A.5
Enhanced Fluorescence Biosensing Using an Array of Metallic Nanoapertures
Yongdong Liu, Steve Blair, University of Utah
Session 7B:
Devices & Materials I
Co-Chairs:
Sunit Tyagi, Intel
Leonard F. Register, University of Texas Austin
7B.1
An Overview of Double-Gate MOSFETs, Gerold Neudeck, Purdue University
7B.2
A Simulated Annealing Approach for Automatic Extraction of Device and Material
Parameters of MOS with SiO2/High-K Gate Stacks
Fei Li, Leonard F. Register, Sanjay K. Banerjee, University of Texas, Austin
Sivakumar P. Mudanai, Intel; Yang-Yu Fan, Lovotlech; Wei Zhao, University of Notre Dame
7B.3
Quest for the Ultimate Sub-50nm CMOS Transistor Structure
A. Rambhatla S.A. Parke, Boise State University; D.R. Hackler American Semiconductor, Inc.
7B.4
Gate Controlled Punch Through Transistor
Xiangli Li, Huadian Pan, Bogdan M. Wilamowski, University of Idaho
7B.5
Enhanced Hot-Carrier Induced Degradation in pMOSFETs Stressed Under High Gate Voltage
Jone F. Chen, Chih-Pin Tsao, National Cheng Kung University; T.-C. Ong, TSMC Taiwan
Session 8A:
Packaging
Co-Chairs:
Syed Ahmad,
Quinn Tong, National Starch
8A.1
Neural Network Modeling of the Resistance of Metallized Vias formed by Laser
Ablation in Polymer Dielectrics
Ronald Setia, Gary S. May, Georgia Institute of Technology
8A.2
Flip-Chip-In-a-Package Solder Joint Reliability Simulation
Steven Groothuis Tom Jiang, Micron Technology; Yong Du, Advanced Micro Devices
8A.3
Determination and Optimization of Film Adhesive Cure in Board-On-Chip Packaged
Semiconductors J. Rumps, C. Bradbury, B. Fosbinder, Micron Technology
8A.4
Application for WLP at Positive Working Photosensitive Polybenzoxazole
Takashi Hirano Kagehisa Yamamoto, Ken Imamura, Sumitomo Bakelite Co., Tochigi, Japan
8A.5
Printable Die Attach Adhesives for High Speed DRAM Packaging
Kevin Becker, Ablestick, Timmy Lin, ChipMOS Technologies.
Session 8B:
Devices & Materials II
Co-Chairs:
Sunit Tyagi, Intel
Leonard F. Register, University of Texas Austin
8B.1
New highly reliable IC bonding film and its development
Kazuhiko Ohashi Osamu Yokomizo, Yumi Tabuchi, Japan Gore-Tex, Inc.
C.P. Ganatra, W.L. Gore & Associates
Shozo Nakamura, Hiroshima Institute of Technology
8B.2
Gate Dielectric Degradation Effects on nMOS Devices Using a Noise Model Approach
C.E. Lawrence, B.J. Cheek, T.E. Lawrence, Jake Baker, Amy J. Moll, W.B. Knowlton, Boise State
University; Santosh Kumar, Cypress Semiconductor; Amr Haggag, University of Illinois
8B.3
Integration of BaTiO3 Ferroelectric Thin Films with GaAs for Functional Devices
T. Murphy, D. Chen, J. Phillips, University of Michigan
8B.4
Modeling and Design of Polythiophene Gate Electrode ChemFETs for Environmental
Pollutant Sensing T. Vamsi Krishna, D. Russell, J. Hartman, J. Jessing, Boise State University
8B.5
Challenges in Integration of Resonant Interband Tunnel Devices with CMOS
Stephen Sudirgo, Branislav Curanovic, Sean L. Rommel, Karl D. Hirschman, Santosh K. Kurinec,
Niu Jin, Anthony Rice, Paul R. Berger, Phillip E. Thompson, Rochester Institute of Technology,
The Ohio State University, Naval Research Laboratory
Session 9:
Silicon-On-Insulator Devices
Co-Chairs:
Gerold Neudeck, Purdue University
Mohamed A. Osman, Washington State University
9.1
A Planar 6.3nm Thin-body SOI MOSFET Using Tunnel Epitaxy and Nitrided Gate Oxides
Shibly S. Ahmed, Gerold W. Neudeck, John P. Denton, Mark Stidham, Purdue University
9.2
Threshold Voltage Control for Deep Sub-micron Fully Depleted SOI MOSFET
Xiangli Li and Bogdan M. Wilamowski, University of Idaho; S.A. Parke, Boise State University
9.3
Three-Dimensional Simulation of Body Contact Structures in PD SOI MOSFETs
Arash Daghighi, Mohamed A. Osman, Washington State University
9.4
Optimizing Dynamic-Threshold DTMOS Device Performance in an SOI Embedded DRAM
F. Burke, C.S. Kim, A. Rambhatla, Y. Zhao, S.A.. Parke, Boise State University
J. Zahurak, Micron Technology Inc.
9.5
A Method to Overcome Self-Heating Effects in SOI MOSFETs
Bryan Cole, Micron Technology; S.A. Parke, Boise State University
Session 10:
MEMS and Sensors
Co-Chairs:
Jack Judy, UCLA
Jeff Jessing, Boise State University
10.1
Integrated Microsensors and Microelectronics for Environmental Monitoring
Steven M. Martin, Timothy D. Strong, Fadi H. Gebara, Gerald H. Keeler, Richard B. Brown,
University of Michigan Keith L. Kraver, Sensor Products Division, SPS
10.2
Fabrication of a Silicon Micro-scalpel with a Nanometer Cutting Edge
Gerold W. Neudeck, John P. Denton, Mark Stidham, Purdue University
10.3
Piezoelectric Polyimide Tactile Sensor
G.M. Atkinson, R.E. Pearson, Z. Ounaies,, J.A Midkiff, Virginia Commonwealth University
J.S. Harrison and C. Park, NASA Langley Research Center
10.4
Theory and Experiment Study of Fluid Behavior of a Peristaltic Micropump
Sangkwon Na, Shane Ridgeway, Li Cao, Iowa State University
10.5
Bulk Micromachined Pressure Sensor
Lynn Fuller, Stephen Sudirgo, Rochester Institute of Technology
10.6
Thermal Sensor Microfabrication and Related Undergraduate Research Projects
David J. Lawrence, Steven L. Hearn, Gerald R. Taylor, Jr., James Madison University
Poster Session
P1
Fabrication of a PMOS Transistor at NGEE ANN POLYTECHNIC's IC Fabrication Facility
Matthew Philip NGEE ANN Polytechnic, Singapore
P2
Fabrication of an MOS Capacitor Structure at NGEE ANN POLYTECHNIC's IC Fabrication
Facility Matthew Philip NGEE ANN Polytechnic, Singapore
P3
A Device to Demonstrate the Haynes-Shockley Experiment Matthew Philip NGEE ANN
Polytechnic, Singapore Matthew Philip
NGEE ANN Polytechnic, Singapore
P4
Teaching Vacuum Technology Using Spreadsheet Calculations
Robert E. Pearson
Virginia Commonwealth University
P5
Source/Drain Optimization of the Dynamic-Threshold DTMOS Device in a 0.15um
SOI Embedded DRAM Technology
F. Burke [1], A. Rambhatla [1], J. Zahurak [2], S.A. Parke [1] [1]Boise State University, [2]Micron
Technology
Optimization of Bosch Etch Process for Through-Wafer Interconnects
Linda Kenoyer, Rex Oxford, Joe Lindsey, Amy Moll Boise State University
P6
P7
A Low-Voltage, Low-Power 1.5GHz CMOS LNA Design
Zhangfa Liu, S.A. Parke Boise State University
P8
Low-latency Multiple Clock Domain Interfacing Without Alteration of Local Clocks
Scott F. Smith [1], James F. Frenzel [2]
[1]Boise State University, [2]University of Idaho
P9
The Design of Low Noise Amplifiers Based on BSIM3v3 Model
Chang-Sun Kim, S.A. Parke
Boise State University
P10
A Benzene Selective Electrode
Lisa R. Warner, Dale D. Russell
Boise State University
P11
Temperature Fluctuations and 1/f Noise in Electron Devices
L. Forbes, X.Y. Wang, C.W. Zhang Oregon State University
P12
Simulation of Timing Jitter in Ring Oscillators
C.W. Zhang, L. Forbes
Oregon State University
P13
An Overview of Algorithms in Gnucap
Albert Davis
Idaho State University
P14
Flexible PV Technology Development Program at IIT Bombay
Siddhartha P. Duttagupta Indian Institute of Technology, Bombay
P15
Automated Testing and Parameter Extraction of Solar Cells Fabricated from
6-8 inch Large Test Wafers M.G. Guvench, A.M. Denis, C. Gurcan[1], D. MacDonald[2]
[1]University of Southern Maine, [2]National Semiconductor
P16
Rectangular Polysilicon Diaphragm Fabrication Characterization
Eric Woods, Zhiping Zhou Georgia Institute of Technology
P17
High Performance Direct Digital Frequency Synthesizers
Zhihe Zhou, David Betowski, Xuan Li, George La Rue, Valeriu Beiu Washington State University
P18
Overview of Fully Depleted Silicon-On-Insulator (SOI) Technology
Phuoc T. Tran Micron Technology, Inc.
P19
Interfacial Fracture Mechanics: Chip-Level Interconnect Reliability
Steven Groothuis [1], Guotao Wang [2], Paul S. Ho [2]
[1]Micron Technology, [2]University of Texas Austin
P20
Optimized Pattern Fill Process For Improved CMP Uniformity and Interconnect Capacitance
Mark Nelson
AMI Semiconductor
P21
An Electronic Wafer Traveler System for an Academic Microchip Fabrication Facility
Awais Sheikh, Steven D. Sheetz, Robert W. Hendricks
Virginia Polytechnic Institute and State University
P22
In-Situ Depth Monitoring of the Deep Reactive Ion Etch Process
Y. Imura, B.X. Li, K.R. Farmer
New Jersey Institute of Technology
P23
Reactive Ion Etching in an Academic Integrated Circuit Fabrication Laboratory
Sean Jellish [1], Robert W. Hendricks [2] [1]University of Virginia,
[2]Virginia Polytechnic Institute and State University
P24
Top-Edge Profile Control for SU-8 Structural Photoresist
S.J. Lee [1], W. Shi [1], P. Maciel [2], S.W. Cha [3] [1]San Jose State University,
[2]Quintel Corporation, [3]Stanford University
P25
A Fabrication Laboratory Course Based on GaAs MESFETs
Kenneth P. Roenker, Ron Flenniken, Peter B. Kosel University of Cincinnati