Final Year Project – Progress Report
Final Year Project
SEAN KELLY
Electronic Engineering
Design of voltage regulator module (VRM) circuit for testing of
magnetic components
Supervisor: Dr. Maeve Duffy
Jan 2005
Sean Kelly
Final Year Project – Progress Report
Contents
Acknowledgements ............................................................................................................. 3
References ........................................................................................................................... 3
Project Outline .................................................................................................................... 4
Project Description.......................................................................................................... 4
Background ..................................................................................................................... 4
Buck Converter ................................................................................................................... 6
Description ...................................................................................................................... 6
Operation......................................................................................................................... 8
Multiphase Topologies.................................................................................................... 9
Proposals for tackling project ........................................................................................... 11
Research ........................................................................................................................ 11
Ordering ........................................................................................................................ 11
Pspice ............................................................................................................................ 11
Progression to date ............................................................................................................ 12
VRM 10.1 Specification ............................................................................................... 12
Initial Design Spec ........................................................................................................ 12
Design Procedure .......................................................................................................... 13
Component Selection ........................................................................................................ 21
Output Capacitance ....................................................................................................... 21
Output Inductance ......................................................................................................... 21
Power Switch ................................................................................................................ 22
Pspice ............................................................................................................................ 23
Detailed Task List and Project Plan .................................................................................. 25
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Acknowledgements
I would like to thank my supervisor Dr. Maeve Duffy for the time and effort she put into
helping me throughout the year.
I would also like to thank the lab technicians Myles, Martin and Aodh for all their help.
References
Intel’s website was used to get Intel VRM 10.1 Specification and the Xeon processor
datasheet.
Analog Devices website used to get datasheets for the controller ICs and MOSFET
drivers.
The ORCad website was used to gain knowledge of pspice.
Notes in ‘Electrical Power and Machines’ and ‘Power Electronics’ were used throughout
this project.
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Final Year Project – Progress Report
1. Project Outline
1.1
Project Description
The aim of this project is to design, build and test a voltage regulator module circuit
(VRM) that can be used to compare the performance of different magnetic component
designs. The VRM will be used to convert the input voltage (typically 12V) to a
lower level which will supply a microprocessor load e.g. the Intel Pentium.
The work will include circuit design and simulation, component modeling and design
and circuit testing.
1.2
Background
Voltage regulator modules are a special class of power converter circuits used to
supply microprocessor loads e.g. the Intel Pentium. The VRM converts the system
bus voltage (typically 12 V) to a lower level.
While current operating voltages are in the range of 1 - 1.5 V, it is expected that the
required operating voltages in the next few years will decrease below 1 V while
increasing the drawn current (the required current can easily exceed 100A) from the
power supply in order to reduce the power consumption while increasing the
microprocessor speed.
With such low voltage levels, one of the main challenges of VRM design is to
maintain the constant output voltage under varying and transient load (current)
conditions, when the microprocessor switches from one state to the other, voltage
drop spikes occur, these spikes must be limited.
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Final Year Project – Progress Report
The main limit is caused by the large inductance values required to maintain ripple
levels for steady-state operation. The standard industry solution is a multi-phase buck
converter, in which the inductance is distributed between several phases that are
controlled in parallel.
A buck derived voltage regulator module (VRM) will be designed to satisfy these
requirements.
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2. Buck Converter
2.1
Description
The most common power converter topology is the buck power converter, sometimes
called a step down power converter. Power supply designers choose the buck power
converter because the output voltage is always less than the input voltage in the same
polarity and is not isolated from the input.
The buck regulator circuit is a switching regulator. It uses an inductor and a capacitor
as energy storage elements so that energy can be transferred from the input to the
output in discrete packets. The advantage of using switching regulators is that they
offer higher efficiency than linear regulators. The one disadvantage is noise or ripple,
the ripple will need to be minimized through careful component selection.
A requirement of the design is to have high current slew rate (up to 930 A/μs) to
increase switching speed of microprocessor from one state to the other but this causes
voltage drop spikes at the processor power supply. To achieve high current slew rate
the inductor Lo should be as small as possible. This in turn while achieving faster
transient response will cause the output voltage ripple to increase.
To reduce output voltage ripple, the switching frequency should be increased but this
lowers efficiency. This means that the selection of the switching devices will be an
important issue. The output voltage ripple can also be reduced by increasing the
output capacitance, this means a large capacitor in practical design.
The input current for a buck power converter is discontinuous due to the power
switch, the current pulses from 0 to Io every switching cycle. The output current for a
buck power converter is continuous because the output current is supplied by the
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Final Year Project – Progress Report
output inductor/capacitor combination; the output capacitor never supplies the entire
load current for continuous inductor current mode operation.
Buck Converter
Buck Waveforms
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2.2
Operation
This circuit can operate in 3 ways.
Mode 1
The first state corresponds to the case when the switch is ON. In this state, the current
through the inductor rises, and the energy stored in it increases, during this state the
inductor acquires energy.
Vi  Lo
di L
I
 Vo  Lo   Vo
dt
DT
I
When the switch is closed, the diode is in the OFF state. The diode is there so there
will always be a current source for the inductor.
Mode 2
The second state is when the switch is OFF and the diode is ON. In this state, the
inductor current free-wheels through the diode and the inductor supplies energy to
the RC network at the output. The energy in the inductor falls in this state.
0  Vo  Lo
di L
I 
 Vo  Lo
dt
(1  D)T
II
When the switch is open, the inductor discharges its energy. When all of its energy
has discharged, the current falls to zero and tends to reverse, but the diode blocks
conduction in the reverse direction. In the third state both the diode and the switch are
OFF, in this state the capacitor discharges its energy and the inductor is at rest with
no energy stored in it.
There cannot be a net change in flux in the inductor or it would saturate over a
number of cycles. The increase in current while the switch is on must exactly equal
the decrease in current while the switch is open.
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Final Year Project – Progress Report
Combining I and II:
Vi  Vo
Vo
DT 
(1  D )T
Lo
Lo
Vo = DVi
Average output voltage is determined by the duty cycle D of the switch and is less
than the input voltage.
2.3
Multiphase Topologies
While there is no real limit for a single phase buck regulator, the advantages of
designing with multiphase converters become apparent as load currents increase to
their current large values.
These advantages include:

Reduced input-ripple current.

Substantially decreasing the number of input capacitors.

Reduced output-ripple voltage due to an effective multiplication of the ripple
frequency.

Reduced component temperature achieved by distributing the losses over
more components

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Reduced-height external components.
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Final Year Project – Progress Report
Multiphase Interleaved Buck Converter
Multiphase converters are essentially multiple buck regulators operated in parallel
with their switching frequencies synchronized and phase shifted by 360/n degrees,
(where n identifies each phase). Paralleling converters makes output regulation
slightly more complex. This problem is solved with a current-mode control IC that
regulates each inductor current in addition to the output voltage.
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3. Proposals for tackling project
3.1
Research
Review of buck converter to understand the modes of operation.
Review of VRM circuit topologies for Intel VRM 10.1 specification.
Once these are understood initial circuit design can be undertaken.
3.2
Ordering
Once all circuit values have been calculated and components chosen they will have to
be ordered. This will include Controller IC, MOSFET drivers, MOSFETs, capacitors
etc.
3.3
Pspice
Pspice is a software package used to simulate power electronic circuits.
The student version is available on the ORCAD website, this was downloaded and
can be used for simulation of the circuits once design procedure is completed.
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Final Year Project – Progress Report
4. Progression to date
4.1
VRM 10.1 Specification
The Voltage Regulator Module (VRM) 10.1 Design guidelines defines DC-to-DC
converters to help meet the power requirements of computer systems using Intel®
Xeon™ processor with 800 MHz system bus.
The document defines electrical, thermal and mechanical specifications for VRM
10.1.
The voltage regulator is plugged into a baseboard, where the baseboard is designed to
support more than one processor.
4.2
Initial Design Spec
The design parameters for a typical Intel VRM 10.1 compliant CPU application are:

Input Voltage
=
12 V

VID setting voltage (VVID)
=
1.3 V

Duty Cycle (D)
=
0.108

Nominal output voltage at no load (VONL)
=
1.28 V

Nominal output voltage at 120A load (VOFL)
=
1.13 V

Static output voltage drop based on a 125mΩ load line (RO) from no load to
full load

VD = VONL - VOFL
=
150 mV

Maximum output Current (IO)
=
120 A

Maximum output current step (d IO)
=
105 A

Number of phases (n)
=
4

Switching frequency per phase (fSW)
=
500 kHz
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4.3
Design Procedure

Setting clock frequency
RT

=
1
 27k
n  fSW  4.7 pF
=
1
 27k
4  500k  4.7 pF
=
79.4kΩ
Soft Start & Current Limit Latch off delay times
CDLY
=
42nF
Choosing the closest 1 % standard capacitor
CDLY
=
39nF
RDLY
=
1.96  tDELAY
CDLY
=
452kΩ
Choosing the closest 5 % standard resistor
RDLY =

470kΩ
Inductor Selection
L
≥
VVID  RO  (1  (n  D))
fSW  VRIPPLE
≥
1.3V  1.25m  (1  (4  0.108))
500kHz  10mV
≥
184 nH
Choose inductor value
L
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=
320 nH
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Final Year Project – Progress Report
IR
=
VVID  (1  D)
fSW  L
=
7.25 A
IR 50% of max DC current in inductor
Inductor should not saturate at peak current of 33.625 A
DCR (DC Resistance)
1 - 1½ times droop resistance (RO)
use DCR of 1.4mΩ

Output Droop Resistance
RO
=
RPH(X) =
=

RCS
 RL
RPH ( X )
1.4m
 100k
1.25m
112 kΩ
Inductor DCR temperature correction
Inductor’s DCR used as sense element and copper wire is source of the DCR,
need to compensate for temperature changes of the inductors winding.
Temperature coefficient of copper = 0.39 % / 0C = 0.0039
A
=
RTH (50 0 C )
RTH ( 25 0 C )
B
=
RTH (90 0 C )
RTH ( 25 0 C )
Relative values of RCS for each temperature 500C & 900C
r1=
=
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1
1  (TC  (T 1  25))
0.9112
r2=
=
1
1  (TC  (T 2  25))
0.7978
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Final Year Project – Progress Report
Relative values for RCS1, RCS2 and RTH
rCS2 =
rCS1 =
rTH =
( A  B)  r1  r 2  A  (1  B)  r 2  B  (1  A)  r1
= 0.7195
A  (1  B)  r1  B  (1  A)  r 2  ( A  B)
(1  A)
1
A

1  rCS 2 r1  rCS 2
= 0.3795
1
=
1
1

1  rCS 2 rCS 1
RTH
=
k
=
rTH  RCS
RTH ( ACTUAL)
RTH (CALCULATED )
1.075
=
118.28kΩ
=
0.8455
Calculate RCS1 and RCS2
RCS  k  rCS1 R
RCS1
=
=
35.3kΩ
RCS2
= RCS  ((1  k )  (k  rCS 2)) =
83.9kΩ
Choosing closest 1 % resistor gives:
RCS1 = 35.7 kΩ
RCS2 = 84.5 kΩ
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Final Year Project – Progress Report

Output Offset
The Intel specification requires that at no load the nominal output voltage of the
regulator be offset to a value lower than the nominal voltage corresponding to the
VID code.
Offset set by constant current source from FB pin through RB
RB
=
VVID  VONL
IFB
=
1.3V  1.28V
=
15.5A
1.29kΩ
Choosing closest 1 % standard resistor gives
RB

=
1.3 kΩ
COUT Selection
Ceramic Capacitance
Use 18 X 10μF 1206 capacitors
Cz
=
180 μF
Bulk Capacitance
Cx(MIN) ≥
≥
=
Cx(MAX)≤
Where k =
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L  IO
 CZ
Vrl
n  ( RO 
)  VVID
IO
320nH  100 A
 180F
50mV
4  (1.25m 
)  1.3V
100 A
3.25 mF
L
nK 2 RO
-ln (
2

VERR
)
VV
VV
V
nKRO 2
 ( 1  (tV VID 
)  1)  C Z
VVID
VV
L
=
5.2
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Final Year Project – Progress Report
*
The VRM must be capable of accepting voltage level changes of 12.5 mV
steps every 5 μs, up to 36 steps (450 mV) in 180 μs
VV = 450 mV,
tV = 180 μs,
VERR = 2.5 mV.
Cx(MAX)≤
320nH  450mV
180s  1.3V  4  5.2  1.25m 2
 ( 1 (
)  1)  180F
2
2
450mV  320nH
4  5.2  1.25m  1.3V
Cx(MAX)≤
26.9mF
Use eight 560 μF Al-Poly capacitors with a typical ESR of 5mΩ each yields Cx =
4.48 mF with an Rx = 0.63mΩ
Lx
≤
CZ  RO  Q 2
≤
180F  1.25m 2  2 ≤
2
563pF
Where Q is limited to 2 to ensure a critically damped system.

Power MOSFETS
Guideline is to limit power dissipation to 1 W per MOSFET
Synchronous MOSFETs
With conduction losses being dominant
The power dissipated in each synchronous MOSFET
PSF
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IO 2 1
n IR 2
)  (
) ]  RDS ( SF )
nSF
12
nSF
=
(1  D)  [(
=
(1  0.108)  [(
120 A 2 1
4  7.25 A 2
)  (
) ]  4.8m
8
12
8
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Final Year Project – Progress Report
PSF
=
968 mW
Main MOSFETs
There are two main power dissipation components in main MOSFETs
Switching loss per main MOSFET:
PS(MF) =
2  f SW 
VCC  I O
n
 RG  MF  C ISS
nMF
n
=
2  500kHz 
=
315 mW
12V  120
8
 3   584 pF
8
4
Conduction loss per main MOSFET:
PC(MF) =
D  [(
IO 2 1
n IR 2
)  (
) ]  RDS ( MF )
nMF
12
nMF
=
0.108  [(
=
460 mW
120 2 1
4  7.25 2
)  (
) ]  19m
8
12
8
The power dissipated in each main MOSFET
PMF
=
775 mW
Used ONSEMICONDUCTOR NTD40N02 as the main MOSFET (eight total nMF
= 8) with a CISS = 584 pF and RDS(MF) = 19 mΩ.
Used ONSEMICONDUCTOR NTD110N02 as the synchronous MOSFET (eight
total nSF = 8) with a CISS = 2710 pF and RDS(SF) = 4.8 mΩ.
Power dissipation in the driver per phase
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Final Year Project – Progress Report
PDRV
=
[
f SW
 (nMF  QGMF  nSF  QGSF )  I CC ]  VCC
2 n
=
[
500kHz
 (8  5.78nC  8  28nC )  6mA]  12V
2 4
=
275 mW
in each driver which is below 400mW dissipation limit

Ramp Resistor Selection
RR
=
AR  L
3  AD  RDS  C R
=
0.2  320nH
3  5  2.4m  5 pF
=
356 kΩ
Choosing closest 1 % standard resistor gives
RR
=
357 kΩ
Internal ramp voltage magnitude determined by:
VR

AR  (1  D)  VVID
RR  C R  f SW
=
0.2  (1  0.108)  1.3V
357k  5 pF  500kHz
=
0.26
=
260 mV
Comp Pin Ramp
VRT
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=
=
VR
2  (1  n  D)
1
n  f SW  C X  RO
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Final Year Project – Progress Report
=
=

260mV
2  (1  4  0.108)
1
4  500kHz  4.48mF  1.25m
274 mV
Current Limit Set Point
RLIM
=
ALIM  VLIM
I LIM  RO
=
10.4mV / A  3V
120 A  1.25m
=
208 kΩ
Choosing closest 1 % standard resistor gives
RLIM
=
IPHLIM =
205 kΩ
VCOMP( MAX )  VR  VBIAS
AD  RDS ( MAX )

IR
2
=
3.3V  260mV  1.2V 7.25 A

5  3m
2
=
126 A
The per phase initial duty cycle is determined by:
DMAX =
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D
VCOMP( MAX )  VBIAS
=
0.108 
=
0.82
VRT
3.3V  1.2V
274mV
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Final Year Project – Progress Report
5. Component Selection
5.1
Output Capacitance
In switching power supply power stages, the function of output capacitance is to store
energy. The energy is stored in the capacitor’s electric field due to the voltage
applied. The function of a capacitor is to attempt to maintain a constant voltage.
Ceramic capacitors have excellent high frequency characteristics so will be used in
this case.
Ceramic capacitance of 180 μF is used made up of 18 10 μF MLC capacitors.
The bulk capacitors help determine the output ripple voltage and its transient
response, selection is dominated by ESR.
Bulk capacitance of 4.48 mF is used made up of 8 560 μF Al-Poly capacitors.
5.2
Output Inductance
In switching power supply power stages, the function of inductors is to store energy.
The energy is stored in their magnetic field due to the current flowing.
The function of an inductor is usually to attempt to maintain a constant current or
sometimes to limit the rate of change of current flow.
Inductor value of 320 nH is chosen.
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Final Year Project – Progress Report
5.3
Power Switch
Main MOSFET
In switching power supply power stages, the function of the main power switch is to
control the flow of energy from the input power source to the output voltage.
As switching losses dominate, need a device with low gate charge and gate-drain
capacitance.
Chose ONSEMICONDUCTOR NTD40N02 for main MOSFET.
Synchronous MOSFET
The synchronous MOSFET conducts when the power switch turns off and provides a
path for the inductor current.
Conduction losses dominate switching losses so operating two MOSFETs in parallel
reduces RDS(ON) and lowers conduction losses.
Chose ONSEMICONDUCTOR NTD110N02 for synchronous MOSFET.
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Final Year Project – Progress Report
5.4
Pspice
Pspice is a software package used to simulate power electronic circuits.
The model of a multi-phase interleaving buck converter can be simplified as a singlephase buck converter. The equivalent inductance in the simplified model is 1/n of the
inductance in each phase. The equivalent switching frequency of the simplified model
is n times the switching frequency in each phase. So the multi-phase interleaving
buck converter can be analyzed in the same way as a single-phase buck converter.
The MOSFET pspice models, NTD40N03R (upper MOSFET) and NTD110N02R
(synchronous MOSFET), were downloaded from the ONSEMICONDUCTOR
website for more accurate testing.
Output voltage is found to be 1V. This deviation from the expected 1.3V is mainly
due to power losses in the MOSFETs, as when more MOSFETs are added to the
circuit in parallel the output voltage tends to 1.3V. There will also be discrepancies
due to the fact that the equivalent series resistance (ESR) and equivalent series
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Final Year Project – Progress Report
inductance (ESL) of the output capacitance has not been taken into account at this
stage.
Output Voltage Waveform
Inductor & Capacitor Waveforms
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Final Year Project – Progress Report
6. Detailed Task List and Project Plan
This is a list of tasks to be completed during the project:

Complete simulation of circuit in SPICE.

Analysis of the circuit design and redesign to allow for non-ideal aspects of
components.

Design and simulation of circuit under transient load changes, build and test
circuit. Analyse using SPICE

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Design, build and test circuit using commercial components.
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Final Year Project – Progress Report
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