Dept of ECE
CIRCUIT DIAGRAM:
For Modulation:
For Demodulation:
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Dept of ECE
Analog Communications Lab
EXP NO:1
DATE :
AMPLITUDE MODULATION & DEMODULATION
AIM: a) To generate Amplitude Modulated wave & to calculate the modulation index
b) To implement AM using MATLAB.
APPARATUS REQUIRED:
Equipment
Transistor
Diode
Resistors
Capacitors
CRO
Function Generator
Regulated Power supply
Connecting probes
Specification/Range
SL100
OA79
56kΩ,5.6kΩ,560kΩ,
10kΩ - 2, 16kΩ(DRB)
100µF,10µF,0.01µF
(0-20) MHz
1MHz
(0-30V),1A
Quantity
1
1
1 each
1 each
1
2
1
As required
THEORY:
Amplitude modulation is defined as a process in which the amplitude of the carrier wave c(t) is
varied linearly with the instantaneous amplitude of the message signal m(t).The standard form the
amplitude modulated wave is defined as
s (t)=Ac[1+Kam(t)] cos 2πfct
where Ka is called amplitude sensitivity of the modulator
The Demodulation circuit is used to recover the message signal from the incoming AM wave at the
receiver. An Envelop detector is simple and yet highly effective device that is well suited for the
demodulation of AM wave for which the % of modulation is less than 100%.An Envelop detector
produces an output signal that follows the envelop of the input wave exactly.
Modulation index is defined as m=(Vmax –Vmin)/(Vmax+Vmin)
PROCEDURE:
1. The circuit is connected as per the circuit diagram.
2. Switch on +12 V Vcc supply.
3. Apply sinusoidal signal of 1kHz frequency and amplitude 2 Vp-p as modulating signal,and carrier
signal of frequency 11 kHz and amplitude 15 Vp-p.
4. Now slowly increase the amplitude of the modulating signal up to 7V and note down values Vmax
and Vmin.
5. Calculate the modulation index using the equation.
6. Find the value of R from fm=1/2πRC taking C=0.01µF.
7. Connect the circuit diagram for Demodulation.
8. Feed the AM wave to the demodulator circuit and observe the output.
9. Note down the frequency and amplitude of the demodulated o/p waveform.
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EXPECTED WAVEFORMS:
Observation table:
S.No
Am(volts)
Vmax
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Vmin
m
%m
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PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
VIVA Questions:
1. AM is Defined as ____________
2. Draw its spectrum___________
3. Draw the phase representation of an amplitude modulated wave___
4. Modulation index is defined as_____
5. The different degrees of modulation _______
6. What are the limitations of square law modulator __________
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7. Compare linear and nonlinear modulators
8. AM Demodulator is ___________
9. Detection process _________
10. The different types of distortions that occur in an envelope detector are__________
CIRCUIT DIAGRAM:
DSB-SC Modulator
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EXP NO:2
DATE :
DSB-SC MODULATION& DEMODULATION
AIM: (a) To generate the DSB-SC Modulated wave and to observe the phase reversal at the zero
crossing of the modulating signal.
(b) To implement DSB-SC using MATLAB.
APPARATUS REQUIRED:
Name of the component Specification Quantity
IC 1496
1
Resistors
6.8kΩ
1
10kΩ,3.9kΩ 2 each
1kΩ,51kΩ
3each
Capacitors
0.1µF
4
Variable Resistor
CRO
0-50kΩ
(0-20MHz)
1
1
Function Generator
1MHz
2
Regulated power supply
0-30V,1A
1
THEORY:
Balanced modulator is used for generating DSB-SC signal.A balanced modulator consists of
two standard amplitude modulators arranged in a balanced configuration so as to suppress the carrier
wave.The two modulators are identical except the reversal of sign of the modulating signal applied to
them.
The IC MC1496 is used as Modulator in this experiment. MC 1496 is a monolithic integrated
circuit balanced modulator/Demodulator, is versatile and can be used up to 200 Mhz. Multiplier: A
balanced modulator is essentially a multiplier. The output of the MC 1496 balanced modulator is
proportional to the product of the two input signals. If you apply the same sinusoidal signal to both
inputs of a ballooned modulator, the output will be the square of the input signal AM-DSB/SC: If you
use two sinusoidal signals with deferent frequencies at the two inputs of a balanced modulator
(multiplier) you can produce AMDSB/ SC modulation. This is generally accomplished using a highfrequency “carrier” sinusoid and a lower frequency “modulation” waveform (such as an audio signal
from microphone).
PROCEDURE:
1. Connect the circuit diagram as shown in Fig.1.
2. Carrier signal of 1Vp-p amplitude and frequency of 83 kHz is applied to pin no.10
3. An AF signal of 0.5 Vp-p amplitude and frequency of 5kHz is applied to pin no.1
4. Observe the DSB-SC waveform at pin no.12.
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EXPECTED WAVWFORM:
OBSERVATION TABLE:
Signal
Amplitude(Volts)
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Frequency(Hz)
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Output:
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PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
VIVA Questions:
1. The two ways of generating DSB_SC are ________
2. The applications of balanced modulator are ________
3. The advantages of suppressing the carrier ________
4. The advantages of balanced modulator __________
5. The advantages of Ring modulator __________
6. The expression for the output voltage of a balanced modulator is _________
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CIRCUIT DIAGRAM:
FM Modulator:
FM Demodulator:
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EXP NO:3
DATE :
FREQUENCY MODULATION & DEMODULATION
AIM: a) To generate the frequency modulated signal and to find the modulation index.
b) To demodulate the frequency modulated signal using FM detector.
c) To implement FM using MATLAB.
APPARATUS REQUIRED:
THEORY:
The process in which the frequency of the carrier is varied in accordance with the instantaneous
amplitude of the modulating signal is called “Frequency modulation”.An FM wave can be represented
mathematically as
S(t)=Ac cos [2πfct +β sin2πfmt]
Where Ac is the amplitude & fc is the frequency of the carrier wave.
Β is the modulation index of the FM Wave.
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EXPECTED WAVEFORMS:
OBSERVATION TABLE:
S.No
Am(Volts)
Tmax(sec)
fmin(kHz)
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Δf(kHz)
β
BW
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Frequency modulation is much immune to noise than amplitude modulation and significantly more
immune than phase modulation. A single noise frequency will affect the output of the receiver only if it
falls within its pass band.
PROCEDURE:
1. Connect the circuit as per the given circuit diagram.
2. Switch on the power supply.
3. Measure the frequency of the carrier signal at the FM o/p terminal with input terminals open and plot
the same on graph.
4. Apply the modulating signal of 500 Hz with 1Vp-p.
5. Trace the modulated wave on the CRO and plot the same on graph.
6. Find the modulation index by measuring minimum & maximum frequency deviations from the
carrier frequency using the CRO.
7. Repeat steps 5&6 by changing the amplitude and/or frequency of the modulating signal.
PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
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VIVA Questions:
1.Define frequency modulation?
2.Mention the advantages of indirect method of FM generation?
3.Define modulation index and frequency deviation of FM?
4.What are the advantages of FM?
5.What is narrow band FM?
6.Compare narrow band FM and wide band FM?
7.Differrntiate FM and AM?
8.How FM wave can be converted into PM wave?
9,State the principle of reactance tube modulator?
10.Draw the circuit of varactor diode modulator?
11.What is the bandwidth of FM system?
12.Want is the function of FM discriminator?
13.How does ratio detector differ from fosterseely discriminator?
14.What is meant by linear detector?
15.What are the drawbacks of slope detector?
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Analog Communications Lab
Dept of ECE
BLOCK DIAGRAM:
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EXP NO:4
Analog Communications Lab
DATE :
STUDY OF SPECTRUM ANALYZER
AIM: To study the spectrum analyzer and to analyze the spectrums of AM & FM signals.
APPARATUS REQUIRED:
THEORY:
PROCEDURE:
PRECAUTIONS:
RESULT:
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CIRCUIT DIAGRAM:
Pre-Emphasis Circuit:
De-Emphasis Circuit:
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Dept of ECE
EXP NO:5
Analog Communications Lab
DATE :
PRE-EMPHASIS & DE-EMPHASIS
AIM: To study the functioning of Pre-Emphasis and De-Emphasis circuits.
APPARATUS REQUIRED:
THEORY:
Frequency modulation is much immune to noise than amplitude modulation and significantly more
immune than phase modulation. A single noise frequency will affect the output of the receiver only if it falls
within its pass band.
The noise has a greater effect on the higher modulating frequencies than on lower ones. Thus, if the
higher frequencies were artificially boosted at the transmitter and correspondingly cut at the receiver,
improvement in noise immunity could be expected. This booting of the higher frequencies, in accordance
with a pre-arranged curve, is termed pre-emphasis, and the compensation at the receiver is called
deemphasis. If the two modulating signals have the same initial amplitude, and one of them is preemphasized to (say) twice this amplitude, whereas the other is unaffected (being at a much lower frequency)
then the receiver will naturally have to de-emphasize the first signal by a factor of 2, to ensure that both
signals have the same amplitude in the output of the receiver. Before demodulation, i.e. while susceptible to
noise interference the emphasized signal had twice the deviation it would have had without pre-emphasis,
and was thus more immune to noise. Alternatively, it is seen that when this signal is de-emphasized any
noise sideband voltages are de-emphasized with it, and therefore have a correspondingly lower amplitude
than they would have had without emphasis again their effect on the output is reduced. The amount of
preemphasis in U.S FM broadcasting, and in the sound transmissions accompanying television, has been
standardized at 75 microseconds, whereas a number of other services, notably CCIR and Australian TV
sound transmission, use 50 micro second.
PROCEDURE:
PRE-EMPHASIS
1. Connect the circuit as per the circuit diagram
2. Apply a sine wave to the input terminals of 2 VP-P (Vi)
3. By varying the input frequency with fixed amplitude, note down the output amplitude (Vo) with
respect to the input frequency.
4. Calculate the gain using the formula
Gain = 20 log (VO/ VI) db
Where VO = output voltage in volts.
VI = Input voltage in volts.
And plot the frequency response.
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EXPECTED WAVEFORMS:
OBSERVATION TABLE:
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II-DE-EMPHASIS
1. Connect the circuit as per circuit diagram.
2. Repeat steps 2,3 & 4 of Pre-Emphasis to de-emphasis also.
PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
VIVA Questions:
1. What is the need for pre-emphasis?
2. Explain the operation of pre-emphasis circuit?
3. Pre-emphasis operation is similar to high pass filter explain how?
4. De-emphasis operation is similar to low pass filter justify?
5. What is de-emphasis?
6. Draw the frequency response of a pre-emphasis circuit?
7. Draw the frequency response of a de-emphasis circuit?
8. Give the formula for the cutoff frequency of the pre-emphasis circuit?
9. What is the significance of the 3db down frequency?
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Dept of ECE
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CIRCUIT DIAGRAM:
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Analog Communications Lab
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Dept of ECE
Analog Communications Lab
EXP NO:6
DATE :
VERIFICATION OF SAMPLING THEOREM
AIM: To verify the sampling theorem.
APPARATUS REQUIRED:
S.No
1
Equipment
DCL-01 kit
2
Connecting chords
3
Power supply
4
CRO(0-20MHz)
THEORY:
The kit is used to study Analog Signal Sampling and its Reconstruction. It basically
consists of functional blocks, namely Function Generator, Sampling Control Logic, Clock section,
Sampling Circuitry and Filter Section.
FUNCTION GENERATOR: This Block generates two sine wave signals of 1 KHz and 2 KHz
frequency. This sine wave generation is done by feeding 16 KHz and 32 KHz clock to the shift register.
The serial to parallel shift register with the resistive ladder network at the output generates 1 KHz and 2
KHz sine waves respectively by the serial shift operation. The R-C active filter suppresses the ripple
and smoothens the sine wave. The unity gain amplifier buffer takes care of the impedance matching
between sine wave generation and sampling circuit.
SAMPLING CONTROL LOGIC: This unit generates two main signals used in the study of
Sampling Theorem, namely the analog signals (5V pp, frequency 1 KHz and 2 KHz) and sampling
signal of frequency 2 KHz, 4 KHz, 8 KHz, 16 KHz, 32 KHz, and 64 KHz.
The 6.4 MHz Crystal Oscillator generates the 6.4 MHz clock. The decade counter divides the frequency
by 10 and the ripple counter generates the basic sampling frequencies from 2 KHz to 64 KHz and the
other control frequencies.
From among the various available sampling frequencies, required sampling frequency is selected by
using the Frequency selectable switch. The selected sampling frequency is indicated by means of
corresponding LED.
CLOCK SECTION: This section facilitates the user to have his choice of external or internal clock
feeding to the sampling section by using a switch (SW4).
SAMPLING CIRCUITRY: The unit has three parts namely, Natural Sampling Circuit, Flat top
Sampling Circuit, and Sample and Hold Circuit.
The Natural sampling section takes sine wave as analog input and samples the analog input at
the rate equal to the sampling signal.
For sample and hold circuit, the output is taken across a capacitor, which holds the level of the samples
until the next sample arrives. For flat top sampling clock used is inverted to that of sample and hold
circuit. Output of flat top sampling circuit is pulses with flat top and top corresponds to the level of
analog signal at the instant of rising edge of the clock signal.
FILTER SECTION: Two types of Filters are provided on board, viz., 2nd Order and 4th Order Low
Pass Butterworth Filter.
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MODEL WAVEFORMS:
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PROCEDURE:
Refer to Block Diagram & Carry out the following connections and switch settings.
1. Connect power supply in proper polarity to the kit DCL-01 & switch it on.
2. Keep all the switch faults (except switch 1) in OFF position.
3. Connect the 1 KHz, 5Vpp Sine wave signal, generated onboard, to the BUF IN post of the
BUFFER.
4. Connect the sampling frequency clock in the internal mode INT CLK using switch (SW4).
5. Using clock selector switch (S1) select 8 KHz sampling frequency.
6. Using switch SW2 select 50% duty cycle.
7. Connect BUF OUT post of the BUFFER to the IN post of the Flat Top Sampling block/
8. Sample & Hold block/Natural Sampling block by means of the Connecting chords provided
9. Connect the OUT post of the Flat Top Sampling block/ Sample & Hold block/ Natural Sampling
block to the input IN1 post of the 2nd Order Low Pass Butterworth Filter.
RESULT:
VIVA QUESTIONS:
1.What are the types of sampling?
2.State sampling theorem?
3.What happens when fs < 2 fm ?
4.How will be the reconstructed signal when fs >= 2fm?
5.Explain the operation of sampling circuit?
6. Explain the operation of re-construction circuit?
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OBSERVATION TABLE:
Signal
Amplitude(volts) Frequency(KHz)
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Dept of ECE
CIRCUIT DIAGRAM:
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Analog Communications Lab
EXP NO:7
DATE :
TIME DIVISION MULTIPLEXING
AIM: To study Time Division Multiplexing and Demultiplexing, using Pulse Amplitude Modulation
and Demodulation and to reconstruct the signals at the Receiver, using Filters.
APPARATUS REQUIRED:
THEORY:
1. The Onboard Function Generator,
2. The Transmitter,
3. The Receiver with the associated synchronization circuitry.
ONBOARD FUNCTION GENERATOR:
This basically provides four Amplitude Variable each (0 - 5 V) synchronized sine waves, each
250Hz, 500Hz, 1KHz, and 2Khz and an amplitude variable DC level (0-5V).
TRANSMITTER: The Transmitter Section consists of four Analog Input signals from the
Function generator fed to the four channels of the Multiplexer where the signals fed are Time
Division Multiplexed after undergoing the sampling. The sampling process makes the signals
Pulse Amplitude Modulated. The frequencies for sampling are given from the decoder.
RECEIVER: The Receiver Section consists of a Demultiplexer that demultiplexes the four Time
Division Multiplexed signals, which it receives from the transmitter. This Demultiplexed signals
are then fed to the reconstruction circuit, which is the filter section. The receiver timing logic is
very similar to the transmitter timing logic. The demultiplexer based on the control signals C0,
C1, C2, C3 assigns the information to the corresponding channels. The success of the
demultiplexer operation is fully dependent on how exactly, RXCH0, RXCH1, RXCH2, RXCH3
signals match with the TXCH0, TXCH1, TXCH2, TXCH3 signals. Thus, to ensure the proper
demultiplexing, two dividers are reset by the RXCH0 signal, which corresponds with the TXCH0.
The demultiplexed signals are then given to the corresponding reconstruction units. The signal
reconstruction unit is a 4th order Active Low Pass Butterworth Filter provided for each receiver
channel. They filter out the sampling frequency and their harmonics from the demultiplexed
signal and recover the base band by an integrate action. The cut-off frequency of the 4th Order
Low Pass Butterworth Filter is 3.4KHz.
PROCEDURE:
1. Refer to Block Diagram & Carry out the following connections and switch settings.
2. Connect power supply in proper polarity to the kit DCL-02 & switch it on.
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MODEL WAVEFORMS:
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3. Keep all the switch faults in off position
4. Connect 250Hz, sine wave signal from the Function Generator to the multiplexer inputs channel
CH0, by means of the connecting chords provided.
5. Connect 500Hz, sine wave signal from the Function Generator to the multiplexer inputs channel
CH1, by means of the connecting chords provided.
6. Connect 1 KHz, sine wave signal from the Function Generator to the multiplexer inputs channel
CH2, by means of the connecting chords provided.
7.
Connect 2 KHz, sine wave signal from the Function Generator to the multiplexer inputs channel
CH3, by means of the connecting chords provided.
8. Set the amplitude of the input sine wave as desired.
9. Connect the multiplexer output TXD of the transmitter section to the demultiplexer input RXD
of the receiver section.
10. Connect the sampling clock TX CLK of the transmitter section to the corresponding RX CLK of
the receiver section respectively.
11. Connect the Channel Identification Clock TXSYNC of the transmitter section to the
corresponding RX SYNC of the receiver section respectively.
12. Connect the output of the receiver section CH0 to the IN0 of the filter section.
13. Connect the output of the receiver section CH1 to the IN1 of the filter section.
14. Connect the output of the receiver section CH2 to the IN2 of the filter section.
15. Connect the output of the receiver section CH3 to the IN3 of the filter section.
16. Observe the reconstructed output of filters at out 0.
17. Observe the reconstructed output of filters at out 1.
18. Observe the reconstructed output of filters at out 2.
19. Observe the reconstructed output of filters at out 3.
RESULT:
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CIRCUIT DIAGRAM:
PAM Modulator
PAM Demodulator
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Analog Communications Lab
EXP NO:8
DATE :
PULSE AMPLITUDE MODULATION
AIM: To Perform Pulse amplitude modulation and Demodulation and to draw the observed waveforms.
APPARATUS REQUIRED :
S.No
Component
1.
Bread Board
-
1
2.
Power Supply
(0-30v)
1
3.
Transistor BC 107
SL100
2
4.
Resistors
5.
Capacitors
6.
CRO
7.
Function generator
8.
Connecting wires
Range/Specification
1KΩ,4.7 KΩ
,10KΩ,47kΩ
0.1µF
Quantity
1 each
1 each
1
0-20MHz
1
1MHz
2
THEORY:
PAM is the simplest form of data modulation.The amplitude of uniformly spaced pulses is
varied in proportion to the corresponding values of the continuous message m(t).
A PAM consists of a sequence of flat topped pulses.The amplitude of each pulse corresponds to
the value of the message signal x(t) at leading edge of each pulse.
The Pulse amplitude modulation is the process in which the amplitude of regularly spaced
rectangular pulses vary with the instantaneous sample values of a continuous signal in one-one
fashion.A PAM wave is represented mathematically as
Where
x (nTs) represents the nth sample of the message signal x(t)
K is the sampling period
Ka is the constant of amplitude sensitivity
P(t) denotes the pulse.
PAM is of two types
1) Double polarity PAM-This is the PAM wave which consists of both positive and negative pulses.
2) Single polarity PAM-This PAM consists of either negative or positive pulses.In this fixed dc level is
added to the to ensure single polarity signal.
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EXPECTED WAVEFORMS:
Dual polarity & single polarity PAM:
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Analog Communications Lab
PROCEDURE:
1. A circuit is constructed as shown in fig
2. Set the modulating frequency to 1KHz and sampling frequency to25KHz.
3. Apply the 12V supply from the RPS.
4. Observe the output on the CRO.
5. Feed the modulated wave to the low pass filter (Demodulation circuit).
6. Note down the amplitude and time period of the demodulated wave.
7. Plot the waveforms on the graph sheet.
PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
VIVA Questions:
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CIRCUIT DIAGRAM:
PWM Modulator
PWM demodulator
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Analog Communications Lab
EXP NO:9
DATE :
PULSE WIDTH MODULATION & DEMODULATION
AIM: To implement the pulse width modulation & Demodulation circuits and to draw the observed
waveforms.
APPARATUS REQUIRED:
Component
IC 555
Resistors
Capcitors
RPS
CRO
Function generator
Connecting wires
Specification/Range Quantity
1
8.2kΩ,1.5kΩ
1,2
0.01uF,1uF
1,2
0-30v,2A
30 MHz
1MHz
2
THEORY:
The Pulse width modulation, the width of each pulse depends on instantaneous voltage of
baseband signal at the sampling instant. The samples of the message signal are used to vary the width of
individual pulse.
There are many forms of modulation for communicating information, when a high frequency
signal has amplitude varied in response to a lower frequency signal. These signals are used for radio
wavelength because the higher frequency carrier signal needs for efficient radiation of the signal. When
communication by pulse was introduced, the amplitude, the frequency and pulse width become possible
modulation option.
For a single phase inverter modulated by a sine tooth comparison, if we compare a sinewave of
magnitude from -2 to +2 with a triangle from -1 to +1 with linear relation from the input signal and
average signal will be lost. Once the same wave reaches the peak of the triangle other pulse will be of
maximum width and modulation will then separate. The modulation length is the ratio of the current
signal to the case when saturation is just starting.
PROCEDURE:
1.
2.
3.
4.
5.
6.
Connections are given as per circuit diagram.
Apply a trigger signal of frequency 2KHz with amplitude of 5v(p-p).
Observe the sample signal at pin 3.
Apply the ac signal at pin 5 and vary the amplitude.
Note that as the control input is varied output pulse width is also varied.
Observe that the pulse width increases during the positive slope condition and decreases under
negative slope condition. Pulse width is maximum at the positive peak and minimum at the
negative of the sinusoidal signal. Record the observations.
7. Feed the PWM waveform to the demodulation circuit and observe the demodulated signal
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EXPECTED WAVEFORMS:
OBSERVATION TABLE:
Signal
Frequency(Hz) Amplitude(Volts)
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PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
VIVA Questions:
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CIRCUIT DIAGRAM:
Pulse position modulator
OBSERVATION TABLE:
Signal
Frequency(Hz) Amplitude(Volts)
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Analog Communications Lab
EXP NO:10
DATE :
PULSE POSITION MODULATION
AIM: To implement the pulse width modulation circuit and to draw the observed waveforms.
APPARATUS REQUIRED:
Component
IC 555
Resistors
Capacitors
RPS
CRO
Function generator
Connecting wires
Specification/Range Quantity
1
3.9kΩ,3kΩ
1each
0.01uF,1uF
1,2
0-30v,2A
1
30 MHz
1
1MHz
2
THEORY:
PPM is the process in which the position of a standard pulse is varied as a function of the
amplitude of the sampled modulating signal.
Assuming the centre of each pulse occurs at the instant of T,2T,… the modulating signal results
the entire pulse by amount of ΔTsin ωt .
The noise produces small disturbing, effects on the time position of the modulating pulse train
and as a result PPM waves have a better performance with respect to signal to noise ratio in
comparision PAM and PWM.
The simplest arrangement for producing PAM pulse train is to produce PWM signal at first and
effected them to monostable multivibrator at the leading edge of each PWM pulse circuit is triggered
while its return to stable state.
PROCEDURE:
1.
2.
3.
4.
5.
Connect the circuit as per the circuit diagram.
Apply the modulating signal of 2V (p-p) to the control pin 5 using function generator.
Observe the PPM output at pin 3 and observe the position pulses on the CRO.
Now by varying the amplitude of the modulating signal,note down the position of the pulses.
Observe the output on CRO.
PRECAUTIONS:
1. Check the connections before giving the power supply
2. Observations should be done carefully.
RESULT:
Turbomachinery Institute of Technology & Sciences
Dept of ECE
EXPECTED WAVWFORMS:
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Analog Communications Lab
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Dept of ECE
Analog Communications Lab
CIRCUIT DIAGRAM:
BASIC PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER
Turbomachinery Institute of Technology & Sciences
43
Dept of ECE
Analog Communications Lab
EXP NO:11
DATE :
FREQUENCY SYNTHESIZER
AIM: To study the operation of frequency synthesizer.
APPARATUS REQUIRED:
Equipment
Range
Quantity
Frequency Synthesizer Trainer
CRO
(0-20) MHz
Connecting cords & probes
THEORY:
The frequency synthesizer is not a frequency generator in the same sense as an oscillator, but is a
frequency converter, which uses a phased-locked loop and digital counters in a phase-error feedback system to
keep the outputs running in a fixed phase relation to the reference signal. Output frequency stabilities are
determined by the stability of the reference oscillator, which is typically a crystal controlled oscillator
circuit.
The principles of the frequency synthesizer were developed about 1930 but only found application
in very sophisticated equipment because of the cost of the components. Microcircuit chips designed
especially for this application are available now at very low cost, and frequency synthesizers are finding
increasing application for channel selection in communications equipment.
Phased-Locked Loop (PLL)
The heart of the frequency synthesizer is the phase-locked loop. A simple phase-locked loop is
illustrated in figure and its operation may be described as follows. A stable oscillator produces a squarewave reference frequency fr which provides one of the inputs to the phase-detector circuit. This reference
frequency may be any convenient value, but it is usually chosen so that a crystal oscillator circuit may be
used. A voltage controlled oscillator (VCO) generates the final output frequency fo and is designed so that it
will tune over the whole range from the minimum frequency to the maximum frequency desired. Its output
is fed directly to the load and also is used to drive a programmable binary counter that provides the function
of frequency division (N, where N is the number programmed in to the counter). The output of the counter
is a square wave at the reference frequency which provides the second input to the phase comparator circuit.
Turbomachinery Institute of Technology & Sciences
Dept of ECE
44
Analog Communications Lab
The phase comparator is a circuit which provides a DC signal whose amplitude is proportional to the
phase difference between the difference signal fr and counter output fo / N. this DC signal is filtered to
smooth out noise and slow the response of the circuit to prevent over shoot or oscillations and is applied as
the control input to the VCO. When the phase difference between the two signals fr and fo / N is zero, the DC
output from the phase comparator is just exactly that needed to tune the VCO to the frequency Nf r . If a
phase difference
exists between the two, the bias applied to the VCO will change in a direction to raise or lower the
frequency fo just sufficiently so that the phase difference will disappear. Once the VCO output reaches the
value Nfr , it will “lock on to” that frequency, and the feedback loop prevent it from drifting. The output
frequency fo is adjusted to a new value by changing the number by which the counter divides. This is
accomplished by means of thumb wheel switches or by means of a register into which a new number for N
can be entered to control the set point of the counter. The number N is the number of pulses that the counter
will count before it repeats, coded in binary.
PROCEDURE:
PRECAUTIONS:
RESULT:
QUESTIONS:
1. The need for Frequency Synthesizer in communications receivers ______
Turbomachinery Institute of Technology & Sciences
Dept of ECE
Circuit Diagram:
Block Diagram:
Turbomachinery Institute of Technology & Sciences
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Analog Communications Lab
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Dept of ECE
Analog Communications Lab
EXP NO:12
DATE :
AGC CHARATERISTICS
AIM: To observe the AGC Characteristics.
APPARATUS REQUIRED:
Equipment
Range
Quantity
Automatic Gain Control Trainer
CRO
(0-20) MHz
Connecting cords & probes
THEORY:
A Simple AGC is a system by means of which the overall gain of a radio receiver is varied
automatically with the changing strength of the received signal, to keep the output substantially constant. A
dc bias voltage, derived from the detector. The devices used in those stages are ones whose trans
conductance and
hence gain depends on the applied bias voltage or current. It may be noted in passing that, for correct AGC
operation, this relationship between applied bias and transconductance need not to be strictly linear, as long
as transconductance drops significantly with increased bias. All modern receivers are furnished with AGC,
which enables tuning to stations of varying signal strengths without appreciable change in the size of the o/p
signal thus AGC “irons out” input signal amplitude variations, and the gain control does not have to be re adjusted every time the receiver is tuned from one station to another, except when the change in signal
strengths is enormous. In addition, AGC helps to smooth out the rapid fading which may occur with long
distance short-wave reception and prevents the overloading of the last IF amplifier which might otherwise
have occurred.
BLOCK DIAGRAM DESCRIPTION:
1. RF Generator: Colpitts oscillator using FET is used here to generate RF signal of 455 KHz frequency to
use as carrier signal in this Experiment. Adjustments for amplitude and frequency are provided on panel for
ease of operation.
2. AF Generator: Low frequency signal of approximately 1 KHz is generated using OP-AMP based weinbridge oscillator, required amplification and adjustable attenuation are provided.
3. Regulated power supply: This consists of bridge rectifier, capacitor filters and three terminal regulators
to provide required DC voltages in the circuit i.e. +12v, _12v, +6v @150 mA each.
4. AM Modulator: Modulator section illustrates the circuit of modulating amplifier employing a transistor
(BC
107) as an active device in common emitter amplifier mode.R1 and R2 establishes a quiescent forward bias
for the transistor .The modulating signal is fed at the emitter section causes the bias to increase or decrease
Turbomachinery Institute of Technology & Sciences
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Dept of ECE
Analog Communications Lab
TABULAR COLUMN:
S.NO AM Signal Strength (mV) Detector Output (mV)
EXPECTED WAVEFORMS:
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Dept of ECE
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Analog Communications Lab
in accordance with the modulating signal.R4 is emitter resistance and C3 is by pass capacitor for
carrier. Thus the carrier signal applied at the base gets amplified more when the amplitude of the
modulating signal is at its maximum and less when the signal by the modulating signal output is
amplitude-modulated signal. C2 couples the modulated signal to output of the Modulator.
5. Detector and AGC Stage:
This circuit incorporates two-stage amplifier, diode detector and AGC circuit.
a. 1st IF Amplifier:
Q2 (BF 495C) acts as 1st IF Amplifier. The base of Q2 is connected through R5 (68K0 to the detector
output. R6 (100E) and C4 (47n) is decoupling filter for +B line. The base potential depends on R4
(220k) base biasing resistor and the detector current supplied by R5. The detector current is
proportional to the signal strength received. This controls the bias of Q2 (BF 495C) automatically to the
signal received. This is called A.G.C. C6 (4.7/16) is used as base bias and AGC decoupling capacitor.
The output of Q2 is available across the secondary of L8 (IF T2), the primary of which is tuned to IF by
the capacitor C18 (2n7). This output is given to the base of
Q3 (BF 495D).
b. 2nd IF Amplifier:
Q3 (BF 195C) acts as 2nd IF amplifier. The base bias for Q3 is provided by R7 (180k), C7 (47n) is used
to keep the end 4 of L8 (IFT2) at ground potential for IF signal. The collector of Q3 is connected to the
L9 (IFT3). L9 contains 200pf capacitor inside across the primary. The output of Q3 is available across
the secondary of L9, the primary of which is tuned by the internal 200pf capacitor. R8 (220E), C8 (47n)
consists the decoupling circuit for the collector supply of Q3. The output of Q3 is coupled to detector
diode D1 (OA 79).
c. Detector:
Modulated IF signal from the secondary of L9 (IFT3) is fed to the detector diode D1. D1
rectifies the modulated IF signal & IF component of modulated signal is filtered by C8 (22n), R9
(680E0 & C14 (22n). R9 is the detector load resistor. The detected signal (AF signal) is given to the
volume control P2 (10k Log) though maximum audio output-limiting resistor r21 (10k). It is also given
to AGC circuit made of R5 (68k) and C6 (a.7/16).
d. AGC
The sound received from the LS will depend on the strength of the signals received at the
antenna. The strength of the received signals can vary widely due to fading. This will cause variations
in sound which can be annoying. Moreover, the strength of signals can also be too large in close
vicinity of MW transmitters causing overloading of the 2nd IF amplifier.
Automatic gain control (AGC) is used to minimize the variations in sound with changes in signal
strength & to prevent overloading. The operation of AGC depends on the fact that the gain obtained
from any transistor depend on its collector current & becomes less when the collector current is reduced
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Dept of ECE
Analog Communications Lab
to cut off .For AGC, DC voltage obtained from the detection of IF signals is applied to the 1st amplifier
transistor base in such a way that an increase in this voltages reduces the gain of the transistor.
The result is that when the strength of the incoming signal increases, the DC voltage also increases and
this tends to reduce the gain of the amplifier thus not permitting the output to change much. Here R5
(68k) & C6 (4.7/16) performs this function. C6 (4.7/16) is the AGC decoupling capacitor to by pass any
AF signals and keep the bias steady.
PROCEDURE:
1. As the circuit is already wired you just have to trace the circuit according to the circuit diagram given
above.
2. Connect the trainer to the mains and switch on the power supply.
3. Measures the output voltages of the regulated power supply circuit i.e. +12v and -12v, +6@150ma.
4. Observe outputs of RF and AF signal generator using CRO, note that RF voltage is approximately
50mVpp of 455KHz frequency and AF voltage is 5Vpp of 1KHz frequency.
5. Now vary the amplitude of AFsignal and observe the AM wave at output, note the percentage of
modulation for different values of AF signal.
% Modulation= (B – A) / (B + A) X 100
6. Now adjust the modulation index to 30% by varying the amplitudes of RF & AF signals simultaneously.
7. Connect AM output to the input of AGC and also to the CRO channel –1.
8. Connect AGC link to the feedback network through OA79 diode
9. Now connect CRO channel – 2 at output. The detected audio signal of 1KHz will be observed.
10. Calculate the voltage gain by measuring the amplitude of output signal (Vo) waveform, using formula
A = Vo/Vi.
11. Now vary input level of 455 KHz IF signal and observe detected 1KHz audio signal with and without
AGC link. The output will be distorted when AGC link removed i.e. there is no AGC action.
12. This explains AGC effect in Radio circuit.
PRECAUTIONS:
RESULT:
QUESTIONS:
1. The need for AGC in communications receivers ______
2. Mention different types of AGC and suggest the best one _____________
Turbomachinery Institute of Technology & Sciences
Dept of ECE
Block Diagram:
Circuit Diagram:
Turbomachinery Institute of Technology & Sciences
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Analog Communications Lab
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Dept of ECE
Analog Communications Lab
EXP NO:13
DATE :
PLL AS FM DEMODULATOR
AIM: To study the characteristics of PLL.
APPARATUS REQUIRED:
S. No.
1.
2.
3.
4.
Component
IC
Potentiometer
Resistors
Capacitors
Specification
565
5K
4.7K_, 1K
1μF
0.1μF
0.01μF
5.
6.
7.
8.
9.
Function Generator
Regulated power supply
Bread board
CRO
Connecting wires
1MHz
(0-12)V
Quantity
1
1
2
2
2
4
2
1
1
0-20MHz
1
Single Strand As required
THEORY:
Phase Locked Loop is a versatile electronic servo system that compares the phase and frequency of a given
signal with an internally generated reference signal. It is used in various applications like frequency
multiplication, FM detector, AM modulator & De modulator and FSK etc.,
Free running frequency (f0):
When there is no input signal applied to pin no:2 of PLL,it is in free running mode and the free running
frequency is determined by the circuit elements Rt and Ct and is given by f0 = 0.3/(RtCt) where Rt is the
timing resistor ,Ct is the timing capacitor
Lock range of PLL (fL):
Lock range of PLL is in the range of frequencies in which PLL will remain lock, and this is given by
fL = 8f0 /VCC Where f0 is the free running frequency ,VCC = Vcc –(- Vcc) = 2 Vcc
Capture range (fC):
The capture range of PLL is the range of frequencies over which PLL acquires the lock. This is
given by
R = 3.6 X 103 
Turbomachinery Institute of Technology & Sciences
Where fL is the lock range and CC is filter capacitor
52
Dept of ECE
Analog Communications Lab
Table 1: Free running frequency:
Rt value (pot
resistance)
Theoretical value Practical value
(Frequency)
(Frequency)
Table 2:Lock range
Theoretical Value
(Frequency)
Practical Value
(Frequency)
Table 3: Capture range:
Filter Capacitor (CC Theoretical value Practical value
Characteristics of PLL:
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Dept of ECE
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Analog Communications Lab
PROCEDURE:
Free running frequency:
1. Make the Connections according to the circuit diagram and switch on the power supply.
2. Observe the output of the square wave generator-using oscilloscope and measure the frequency range.
The frequency range should be around 1KHz to 10KHz.
3. Calculate the free running frequency range of the circuit for different values of timing capacitor andRt.
4. Connect 0.1F capacitor (CC) to the circuit and open the loop by removing short between pin 4 and 5.
Measure the minimum and maximum free running frequencies obtainable at the output of the PLL (Pin 4)by
varying the pot. Compare your results with your calculation from step 3 (theoretical value). Simultaneously
you can observe the output signal using CRO.
Lock range:
5. Calculate the lock range of the circuit for a 5KHz free running frequency and record in table 2.
6. Connect pins 4,5 with the help of springs and adjust potentiometer to get a free running frequency of
5KHz . Connect square wave generator output to the input of PLL circuit. Provide a 5KHz square signal of 1
Vpp approximately (make this input frequency as close to the Vcc frequency as possible).
7. Observe the input & Output of the PLL.
8. Observe the input and output frequencies while slowly increasing the frequency of the square wave at the
input. For some range output and input are equal (This is known as lock Range and PLL is said to be in lock
with the input signal). Record the frequency at which the PLL breaks lock. (Output frequency of the PLL
will be around VCO frequency and in oscilloscope you will see a jittery waveform when it breaks lock
instead of clean square wave). This frequency is called as upper end of the lock range and records this as F2.
9. Beginning at 5KHz, slowly decrease the frequency of the input and determine the frequency at which the
PLL breaks lock on the low end record it as F1
10. Find the lock range from F2 – F1 and compare with the theoretical values from step5.
Capture range:
11. Calculate the capture range of the circuit for a 5KHz free-running frequency (consider filter capacitor
(CC) is 0.1µF).
12. With the oscilloscope and counter still on pin 4, slowly increase the input frequency from minimum (say
1KHz), Record frequency (as F3) at which the input and output frequencies of the PLL areequal, this is
known as lower end of the capture range.
13. Now keep input frequency at maximum possible (say 10KHz) and slowly reduce and record the
frequency (as F4) at which the input and output frequencies of PLL are equal. This is known as upper end of
the capture range.
14. Find capture range from F4 – F3 and compare it with the theoretical value (from step 11)
15. Repeat the steps from 11 to 14 with CC value 0.2µF
Turbomachinery Institute of Technology & Sciences
Dept of ECE
54
PRECAUTIONS:
RESULT:
QUESTIONS
1.What are the applications of PLL?
2.What is a PLL?
3.What is a VCO?
4. Define the lkock range of a PLL?
5.Define the capture range of PLL?
6.Give the expression for free running frequency f0 of a PLL?
7.What is meant by the free running frequency of a PLL?
8.Give the expressions for lock range & capture range of a PLL?
Turbomachinery Institute of Technology & Sciences
Analog Communications Lab