(Regd. Under I.T.U Act 1926)
Circle President: - Com. R.L. Moudgil Circle Secretary:-Com. Balbir Singh
H.N. 2329, TELEHOS EMP. Co-op. Qtr NO. 76, Sanchar Colony
HB Society, Sector 50-C Block-D, BRS Nagar
Chandigarh-160047 Ludhiana
Cell No.94171-82626 Cell No. 9417001515__________
Ref. No. BSNLEU/Org. PB/12-13/31 Dated at Ldh. the 28-06- 2013.
To
The Chief General Manager,
Punjab Telecom Circle,
Chandigarh.
Sub: Regarding Mistakes in JTO LICE Held on Dated 02/06/2013.Grant of Grace Marks thereof
Sir.
Kindly refer to my earlier letter dated 15-06-2013 on the subject mentioned above. In this regard I would like to convey you that we have gone through the question paper as well as the answer key uploaded on
Intranet site of Punjab circle. The complete illustrations with references of various sources are given below.
JTO Lice Exam. 2013 for Question nos. 11, 14, 36, 58, 65, 72,83, 84, 88, 140 & 142.

Reference
Oxford
: LONGMAN
English
Contemporary Dictionary.
Dictionary.
So No answer is possible.
Correct word is
Rendezvous ( French : rendez-vous), to visit, to meet, tryst )

Options: (a) is rising (b) Rose (c) will rise (d) rises
Discrepancy- Incomplete Question. Subject is missing
Its answer may be either option (b) rose or option (d) rises. If we consider Rose as a Noun
(name of hotel, building etc.) then answer is option (b), but if we consider Sun as Noun then answer is option (d).
Kindly refer the following description-:

The Rose is located in Hauz Khas Village, in the heart of South Delhi.
Dating back to the 13th century Hauz Khas
Village is the outcome of a successful marriage between rural setting and urban chic, with ruins as backdrop. It has abundant greenery, birdlife, and ancient monuments. It also has a jumble of art galleries, furniture stores, fabulous restaurants, boutiques, antique furniture and private houses.
The Rose - which overlooks a quiet aspect of the village, surrounded by forest, and watched over by birds and peacocks - runs an art gallery, a cafe, and offers short and long term accommodations as P.G. accommodation and service apartments.
Each furniture and decor has been personally chosen, providing an elegant and relaxing atmosphere.
We provide wifi internet, daily housekeeping, daily laundry, airport pick up, car rental, flight and train booking - plus our proven personal touch - our staff will go out of their way to entertain personal requests, run small errands, and help you discover the city.
Tasty in house food is available for breakfast, lunch, and dinner, making your stay at the Rose even more comfortable.
Our unique style and quality standards have been confirmed by reputed organizations and publications such as: French
Embassy, Italian Embassy, Japanese Embassy, JICA, Unesco, EEU, Save the Children, Alliance Francaise, BBC, AFP,
Sopexa, Accenture, CNN Go, Outlook Traveller, Livemint, and more.

This question is definitely out of syllabus.
Moreover the Name of Gautam Budha mother was Mahamaya.
So no correct answer exists in the options.


(a) Throughput (b) MHZ (c) Flaps (d) None of these
Discrepancy- In above question correct answer is missing. Correct answer is MFLOPS /
MIPS. So option (d) is correct but in Key answer given is (a)
Please refer text book Microprocessors and Microcomputers by B. RAM page no-21 answer given is MFLOPS/MIPS and also following Description-:
MIPS (the company name):
It is unfortunate that the term MIPS is used as a processor benchmark as well as a shorthand form of a company name, so first I better make the distinction clear. The company responsible for the CPU designs in the N64 is MTI, an abbreviation for MIPS Technologies Inc.
, but many people (incuding myself) refer to the company as just MIPS.
MIPS (the benchmark):
The processor benchmark called MIPS has nothing to do with the company name. In the context of CPU performance measurement, MIPS stands for 'Million Instructions Per Second' and is probably the most useless benchmark ever invented. The rest of this page concerns MIPS as a benchmark, not the company (also discussed here are the MFLOPS and SPEC benchmarks, plus a comment on memory bandwidth).
The MIPS rating of a CPU refers to how many low-level machine code instructions a processor can execute in one second. Unfortunately, using this number as a way of measuring processor performance is completely pointless because no two chips use exactly the same kind of instructions, execution method, etc. For example: on one chip, a single instruction may do many things when executed (CISC = Complex Instruction Set Computing), whereas on another chip a single instruction may do very little but is dealt with more efficiently (RISC = Reduced
Instruction Set Computing). Also, different instructions on the same chip often do vastly different amounts of work (eg. a simple arithmetic instruction might take just 1 clock cycle to complete, whereas doing something like floating point division or a square root operation might take 20 to 50 clock cycles).
People who design processors and people like me who are interested in how they work, etc., almost never use a processor's 'MIPS' rating when discussing performance because it's effectively meaningless (like many people, I did at one time used to think that a CPU's MIPS rating was all important. Ironically, an employee at MIPS Technologies Inc. corrected my faulty beliefs when I asked him about the performance of the R8000.
MIPS numbers are often very high because of how processors work, but in fact the number tells one absolutely nothing about what the processor can actually do or how it works (ie. a processor with a lower MIPS rating may actually be a better chip because its instructions are doing more work per clock cycle). There are dozens of different processor and system benchmarks, such as
SPEC, Linpack, MFLOP, STREAM, Viewperf, etc. One should always use the test that is most relevant to one's area of interest and the system concerned. With games consoles, however, this

is a bit of a problem because no one has yet made a 'games console' benchmark test - people have to use existing benchmarks which were never designed for the job.
An example: imagine a 32bit processor running at 400MHz. It might be rated at 400MIPS. Now consider a 64bit processor running at 200MHz. It might be rated at 200MIPS (assume a simple design in each case). But suppose my task involves 64bit fp processing (eg. computational fluid dynamics, or audio processing, etc.): the 32bit processor would take many more clock cycles to complete a single 64bit fp multiply since its registers are only of a 32bit word length. The 32bit
CPU would take at least twice as long to carry out such an operation. Thus, for 64bit operations, the 32bit processor would be much slower than the 64bit processor. Now think of it the other way round: suppose one's task only involved 32bit operations. Unless the 64bit registers in the
64bit CPU could be treated as two 32bit registers, the 32bit CPU would be much faster. It all depends on the processing requirements.
The situation in real life is far more complicated though, because real CPUs rarely do one thing at a time and in just one clock cycle. Simple arithmetic operations may take 1 cycle, an integer multiply might take 2 cycles, a fp multiply might take 5 clock cycles, a complex square root operation in a CISC design take 20 cycles, and so on. Worse, some CPUs are designed to do more than one of the same kind of operation at once, ie. they have more than one of a particular kind of processing unit. CPUs such as SGI's R10000 series (or later equivalents), the HP PA8000 series, the old Alpha 21x64 series, etc. often have 2 or more integer processing units, multiple fp processing units and at least one load/store unit. Sometimes, they may have special units too, for example to accelerate square root calculations.
But it doesn't stop there! Today, there are technologies such as MMX (from Intel) which is designed to allow a 64bit integer register to be treated as multiple 32bit, 16bit or 8bit integer registers, and also MDMX (from MIPS Technologies Inc.) which does the same but is more powerful in that it also allows the same register splitting to be done with fp registers and includes a 192bit accumulator register, although at present SGI hasn't implemented MDMX in any of their available CPUs. These new ideas enable many more calculations to be performed in the same amount of time compared to older designs. An example: Gouraud shading involves 32bit fp operations; using a 64bit fp register as two 'separate' 32bit fp registers will (at best) double the processing ability of the CPU.
So that's the MIPS benchmark dealt with, ie. it's useless, so ignore it. Since I mentioned fp calculations, that leads nicely onto the MFLOPS benchmark.
MFLOPS
People often mean MFLOPS to mean different things, but a general definition would be the number of full word-size fp multiply operations that can be performed per second (the M stands for 'Million'). Obviously, fp add or subtract operations take less time and slowest of all is fp divide. Older CPUs take many clock cycles to complete one FLOP and so, even at a high clock speeds, their FLOP rate can be low. An example is the 486DX4/100 which is rated at about
6MFLOPS. Compare this to the 200MHz R4400 which is rated at about 35MFLOPS. For older processors, clock speed is clearly no indication of MFLOP rate.
Newer designs don't mean things become clearer - if anything the situation is more complex, since the situation is often the reverse: CPUs like the R10000 can do two fp operations each clock cycle, giving it a rating of 400MFLOPS at 200MHz. The R8000 is even more confusing

since it has two fp execution units, each capable of doing two fp ops/clock, giving it a rating of
360MFLOPS at 90MHz! (that's ten times faster than an Intel P90).
Again, the nature of the task is important. A 64bit CPU that can do 400MFLOPS may be fine, but if one's work only needs 32bit processing then much of the CPU's capabilities are being wasted. CPUs like the R5000 address this problem, aiming at markets that do not need 64bit floating point (fp for short) processing. Future designs like MDMX will solve the wastage problem, but it will also make the measuring of CPU performance even harder. Perhaps
CPU capability is a better metric, but no one has devised such a test yet. There are just a wide variety of benchmarks and one must use the most appropriate test as a basis for decision making.
All this talk of MFLOPS is fine, but it misses one very important point: memory bandwidth. A fast CPU may sound impressive, and PR people will always talk in terms of theoretical peak performance, etc., but in reality a CPU's best possible performance totally depends on the rate at which it can access data from the various kinds of memory (L1 / L2 cache and main RAM). A fast CPU in a system with low memory bandwidth will not perform anywhere near its theoretical peak (eg. 500MHz Alpha). I have studied the effect of this on the 195MHz R10000 and the results are very interesting. If you want to know more about the whole issue of memory bandwidth, then see STREAM Memory Bandwidth site.
What is important here with regard to the N64 is that SGI have given it a very high memory bandwidth indeed (500MB/sec peak, ie. almost 4 times faster than PCI). The N64's memory design uses Rambus technology, which is also used in SGI's IMPACT graphics technology.

Reference : Data Communication and Networking 4th by Behrouz A Frauzan.
Data Communication and Networking by Tannen Bomb
So no answer can be determines among the given options.

This topic was neither specified in the syllabus and it’s not the part of Diploma level
Curriculum.
This question is definitely out of syllabus.

a) Primary Signal b) Measured variable c) Output d) All of the above.
Measurement refers to input signal (primary signal in transducer), measured variable, output signal and dynamic response.
Reference
: Reference book Integrated course in electrical technology by J.B.Gupta page no. 785 attached for reference
Answer in the provisional answer Key is C (Output) .But according to reference attached, Answer should be (D) All of the above.


Discrepancy- Meaning of Question does not match in English version and
Hindi version. In English version instruments is given but in hindi version measuring instrument is given in question.
If follow English version answer should be option (D)
If follow Hindi version answer should be option (A)

1
 Q - 88
a) Thermo couple b) Moving coil c) Moving iron d) none of the above
Moving coil instruments are of two types
A) Permanent magnet type (D.C. only)
B) Dynamometer type (A.C and D.C. both)
Reference No 1
: Reference book -Integrated course in electrical engineering by J.B. Gupta page no.792 is attached for reference.
Reference no 2
Electrical technology vol.-! by B.L. Thereja page no. 316
According to question all three choices (thermocouple, moving coil, moving iron ) measures A.C. and D.C. both
Answer in the provisional answer Key is B (Moving Coil) .But according to reference attached, Answer should be (D) None of the above.
Reference

Reference 2


Q - 140
:-
Reference:
Reference book Electronic Communication Systems by Wayne tomse page no. 26 is attached.
Answer in the provisional answer Key is C (1000 DBm) .But according to reference no answer is available in the options.

Options: (a) AM (B) FM (c) PM (d) ASK
Discrepancy - No Answer Option. (Correct answer is QPSK)
Kindly refer the following description-:
Overview
This paper is part of the Wireless Standards White Paper Series
Table of Contents
1.
2.
3.
Introduction
Strengths and Weaknesses of IS-95(CDMA) and GSM (TDMA)
Technical Specifications
4.
5.
6.
7.
8.
GSM (TDMA)
IS-95 (CDMA)
Applications and future Generations (3G)
National Instruments Hardware for IS-95 (CDMA) and GSM (TDMA)
CDMA and GSM (TDMA) Software Solutions
1. Introduction
IS-95, or cdmaOne, and GSM (Global System for Mobile Communication) are two fundamental technologies enabling today's cellular phone networks. IS-95 and GSM are 2G technologies implemented using CDMA (code division multiple access) and TDMA
(time division multiple access) respectively. Approximately 80% of the mobile communications industry uses GSM technology, with
IS-95 following at approximately 10-15%. As the market shifts to 3G technologies, GSM is moving towards the implementation of
Wideband CDMA (W-CDMA), while the successor of IS-95 is CDMA 2000. The following document gives a technical overview of all these technologies.
Back to Top
2. Strengths and Weaknesses of IS-95(CDMA) and GSM (TDMA)
Both IS-95 and GSM are the most commonly used mobile communication technologies for cellular networks. Given the derivation from different multiple access schemes, both technologies persist with strengths and weaknesses. A summary of these qualities can be seen below in Figure 1. More detail about how CDMA and TDMA are structured and differ will be discussed in the following sections.

Figure 1: IS-95(CDMA) and GSM(TDMA) Summary
Back to Top
3. Technical Specifications
The technologies behind IS-95 and GSM are CDMA and TDMA, respectively. While both CDMA and TDMA use the same overall frequency range, they differ in how that range is divided up. TDMA uses time to divide the spectrum, allowing each communication the entire spectrum over a discrete time period. CDMA however allows every communication to have the entire spectrum all of the time. See Figure 2 below.
Figure 2.
TDMA and CDMA Spectrum Division
Back to Top
4. GSM (TDMA)
There are three OSI layers involved with GSM: the physical Layer, the data layer, and signaling protocol layer. The physical layer is implemented with TDMA, using Gaussian Frequency Shift Keying (GFSK) as the modulation scheme. The common frequency range of GSM is in the 850-900 MHz range with channel spacing of 200 kHz. Peak data rates are around 14.4 kbps.
For TDMA, the signal is divided by time using the fundamental unit of a burst period. This burst period lasts approximately 15/26 ms and is grouped together by 8 bursts into a frame. A single traffic channel is defined by grouping 26 frames together; giving a total timeframe of 120 ms. These traffic channels are used to transfer speech and data.
Additional control channels also exist for the following purposes:





Broadcast Control Channel (BCCH) serves for BS identification, broadcasts, and frequency allocations.
Frequency Correction Channel (FCCH) and Synchronization Channel (SCH) – used for synchronization, and physical layer definition (time slots, burst time…)
Random Access Channel (RACH) used by mobile to request access to the network.
Paging Channel (PCH) used for locating the mobile user

Access Grant Channel (AGCH) used to obtain a dedicated channel.
The data layer consists of the same protocol used in Integrated Services Digital Network or ISDN. The signaling protocol layer is further subdivided into three categories:



Radio Resource Management
Mobility Management
Connection Management

Back to Top
5. IS-95 (CDMA)
IS-95 consists of a physical layer implemented by CDMA. The modulation scheme commonly used is quadrature-phase shift keying (QPSK).
The common frequency bands in the US and Korea are 825-849 MHz with channel spacing of 1.23 MHz. The data transfer rate is 9.6-115 kbps depending on which revision of the technology is being used.
Instead of segregating the spectrum by time, CDMA uses a unique spreading code technique to differentiate the channels. The signal is transmitted below noise level and is received through a correlator for dispreading of the wanted signal. This wanted signal is then processed through a narrow bandpass filter to reject unwanted signals. The codes, one/zero sequences, used to differentiate signals are designed and generated at a much higher rate than the baseband information. This rate is referred to as a chip rate rather than a bit rate. The relationship between chip rate and bit rate can be seen in Figure 3. The Spread Factor used in CDMA is defined as equation 1.
Figure 3
Equation 1
Thanking you.
Yours Faithfully
(BALBIR SINGH)
Circle Secretary,
BSNLEU Punjab