Patent 2339164
[p. 1/19]
RUSSIAN FEDERATION
(19)
RU(11)
2339164(13) C1
(51)
Int.Cl.:
H04B7/04 (2006.01)
FEDERAL AGENCY FOR
INTELLECTUAL
PROPERTY, PATENTS,
AND TRADEMARKS
(12)
PATENT SPECIFICATION
Status: as of 07 November 2011: in effect
Fee: calculated for 5 years, from 15 May 2011 through 14 May 2012
Application :2007117785/09, 14 May 2007
(24) Date from which patent may have effect
14 May 2007
(45) Publication date: 20 November 2008
(72) Inventor(s):
Vorontsov, Valeriy Leonidovich (RU)
(73) Assignee:
Vorontsov, Valeriy Leonidovich (RU)
(56) List of documents cited in the search report: RU
2052898, C1, 20 Jan 1996. SU 1262737, A1, 07 Oct 1986.
RU 2151406, C1, 20 Jun 2000. RU 38509, U1, 20.06.2004.
EP 1139585, A2, 04 Oct 2001.
Address for correspondence:
125009, Moscow, PO Box 184, YUS Patent Law
Firm, V.V. Kur'yanov (for V. L. Vorontsov)
(54) METHOD FOR DETERMINING RELIABILITY WEIGHTING PARAMETERS FOR PROCESSING
RECEIVED MULTI-POSITION SIGNALS
(57) Abstract:
The invention relates to radio communications and may be used in receiving diversity digital signals by
telemetry. The technical result is an increase in data processing speed and noise immunity in the presence
of arbitrary noise. For this purpose, using n diversity channels, m-position signals (including information
and test signals) are received which are transformed to blocks of elementary data, each of which
represents pulsed r-bit signals in parallel binary code, accompanied by clock pulses and separated by
markers, where m = 2r, m ≥ 1. In each channel, the number of matches for r-bit test signals Ntestreli,
i=1,2,...,n, where Ntestreli is the number of matches in the 1st channel. The blocks of elementary data in
each channel are distributed in order of decrease in the number of matches Ntestreln ≥ Ntestreln-1 ≥
...Ntestreli...Ntestrel2 ≥ Ntestrel1. The combinations {Wki} of reliability weighting parameters (RWPs) are
calculated, {Wki}nopt, k = 1,...,q, with Wk1 < Wk2 < ...Wk,i ... < Wk,n-1Wk,n, where k is the number assigned to
the combination, i is the channel number, and q is the number of combinations. The corresponding pulsed
r-bit test signals are compared for identity and the weighted-sum reliability estimates for them are calculated
using the formula
e = 1, 2, ..., m,
where Wki is the RWP for the k-th combination for the i-th diversity channel, e is the value of the position
in the m-position test signal. Among the calculated weighted-sum reliability estimates W, the maximum
weighted-sum reliability estimate is determined along with the corresponding position egentestk.
Patent 2339164
[p. 2/19]
The weighted-sum reliability estimates are calculated for the next r-bit test signals and the maximum
weighted-sum reliability estimate and the corresponding position egentestk (k = 1, 2, ..., q) are determined.
The values of the positions egentestk (k = 1, 2, ..., q) of the test signals are compared with their reference
values. The number of matches is determined. All the above-indicated operations for determining the
number of matches are repeated for each k-th combination, and from them the combination k = h is
selected that has the maximum number of matches along with the egentesth corresponding to it, and
the RWPs corresponding to the h-th combination is used for processing the received m-position signals.
The method makes it possible to increase the data processing speed and the noise immunity in the
presence of arbitrary noise. 10 drawings, 3 tables.
Fig. 1
KEY to Fig. 1
d
c
c
d
c
"D"
RESET
"A"
"T", b
"M", a
"M"
RESET
"M", a
d
d
d
"T", b
c, "START MODE 2"
"START MODE 3"
d
The invention relates to radio communications and may be used, for example, in
receiving diversity digital signals by telemetry.
Diversity is accomplished:
in space (when receiving at different antennas);
in frequency;
in time;
in polarization (based on connection of channels with different polarization of the radio
signal relative to the autoselector).
However, diversity reception not only creates advantages due to expansion of the
selection capabilities but also accentuates problems connected with processing large
amounts of data. In this case, the problem especially involves selection of a processing
method ensuring high reliability of the data in a generalized data file.
A method is known in the prior art for diversity reception, involving reception of a multiply
repeated telemetry datum and recording the datum received a greater number of times than
other data (majorization). [A. P. Manovtsev, Introduction to Digital Radiotelemetry [in
Russian], Sov. Radio (1967), p. 295]
A limitation of this method is the poor noise immunity when the data in a significant
number of diversity channels are distorted by noise.
A method is known in the prior art for diversity reception of packets of digital information,
involving estimation of the reliability of the data in each received packet corresponding to the
same transmitted packet, and selection in the generalized data file of the packet with the most
reliable data (autoselection). ["Autoselection method for packet digital information,". USSR
Inventor's Certificate 1262737, Byul. Izobr. No. 37 (1986).]
Patent 2339164
[p. 3/19]
The major limitation of this method is the elimination of the possibility for complementarity
of the packet data corresponding to the same transmitted packet and distorted by noise to
different extents.
Thus autoselection, majorization, and their various modifications do not ensure high
reliability.
The method of diversity reception of multi-position signals, including information and test
signals, comes closest. [Russian Federation Patent 2052898, H04B 7/04, G08C 19/28, publ. 20
January 1996].
In this method, it is proposed to increase the reliability of data, selected from analog
realizations of multi-position signals, by adaptation to the noise conditions based on controlling
the functional correspondence between the generalized data and the data arriving from the
diversity channels. The method for diversity reception of data realized in this way provides the
advantages of both majorization and autoselection. It is based on reliability estimates obtained
using test data selected from the blocks of data received through the diversity channels:
Wkij = Ak – Bij,
Wkij = 0 for Ak < Bij
where Ak is the set maximum value of the reliability estimate for received data after its k-th
correction;
Wkij is the value of the reliability estimate for the received data after the k-th correction of
its set maximum value (Ak), for the condition that unreliable test data in the i-th diversity
channel is read in the presence of j unreliable test data among those corresponding to the same
transmitted datum;
Wke is the value of the weighted-sum reliability estimate for the value of the test datum e after
the k-th correction of the set maximum value of the estimate (Ak), if the value of e was repeated
in the test data in the i1-th, i2-th,..., im-th diversity channels corresponding to the same
transmitted datum.
By selecting the values of Ak, to be measured with step A and within the range from Amin
to Amax, its optimal value (Aopt) is obtained, ensuring the minimum number of unreliable
generalized test data. The value of Aopt obtained is used to calculate the optimal estimates Wijopt,
which then are extended to the received information data.
In the method presented as the closest analog, the capabilities for improving noise immunity
by diversity reception of multi-position signals are insufficiently realized due to the use of
inexpedient reliability weighting parameters. They are inexpedient because several (two or
more) combinations of the reliability weighting characters used establish the same functional
relationship. In this case, additional (besides those used) combinations of reliability weighting
parameters exist that provide a new functional relationship. As a result, a rather large data file
has to be processed, and the method is not distinguished by high speed or good noise immunity.
The aim of the invention is to improve the efficiency of diversity reception of multiposition signals.
The technical result which may be achieved in implementation of the invention is to increase
the data processing speed and the noise immunity in the presence of arbitrary noise.
Patent 2339164
[p. 4/19]
In order to solve the problem posed with achievement of the indicated technical result, the
RWPs are determined for processing m-position signals received through n diversity channels,
including information and test signals, which are transformed to blocks of elementary data,
each of which represents pulsed r-bit signals in parallel binary code, accompanied by clock
pulses and separated by markers, where m = 2r, m ≥ 2,
the time delays of the signals through the n diversity channels are compensated,
an address is assigned to each pulsed r-bit signal and they are stored,
the pulsed r-bit test signals are compared with the corresponding references,
in each channel the number of matches of the r-bit test signals Ntestreli, i = 1, 2, ... n are
determined, where Ntestreli is the number of matches in the i-th channel,
the blocks of elementary data in each channel are distributed in order of decrease in the
number of matches Ntestreln≥Ntestreln-1≥...Ntestreli...Ntestrel2≥Ntestrel1, ordering their
numbering relative to Ntestreli, and the order of the distribution of blocks of elementary data is
stored,
the combinations {Wki} of RWPs are precalculated for the pulsed r-bit test signals in each
block of elementary data {Wki}nopt, k = 1, ..., q,
and Wk1 < Wk2 < ...Wk,i... <Wk,n-1 <Wk,n, where k is the number assigned to the combination, i
is the channel number, and q is the number of combinations,
the corresponding pulsed r-bit test signals in each block of elementary data are compared
for identity and the weighted-sum reliability estimates (Wke) are calculated for them for each
r-bit test signal in the block of elementary data, using the formula
e = 1, 2, ..., m,
where Wki is the reliability weighting parameter of the k-th combination for the ordered i-th
diversity channel,
i1, i2 are the ordered diversity channel numbers for identical pulsed r-bit test signals,
e is the value of the position in the m-position test signal,
among the calculated weighted-sum reliability estimates Wke, e = 1, 2, ..., m, the maximum
weighted-sum reliability estimate and the position egentestk (k = 1, 2, ..., q) corresponding to it
for the pulsed r-bit test signal are determined,
the weighted-sum reliability estimates are calculated for the next r-bit test signals, and the
maximum weighted-sum reliability estimate and the position egentestk (k=1, 2, ..., q)
corresponding to it are determined,
the values of the positions egentestk (k = 1, 2, ..., q) of the test signals are compared with their
reference values and the number of matches are determined,
all the above-indicated operations for determining the number of matches are repeated for
each k-th combination, and from them the combination k = h is selected with the maximum
number of matches and the egentesth corresponding to it, and the reliability weighting
parameters corresponding to the h-th combination is used for processing the received mposition signals.
Thus in the claimed method, all possible reliability weighting parameters of the data for the
diversity channels can be represented by a finite (and relatively small) set of W ({Wki}; k = 1,
..., q; i = 1, ..., n), which is a qn matrix (where q is the number of combinations of the values
of the reliability weighting parameters for the data in the diversity channels, while n is the
number of diversity channels).
Patent 2339164
[p. 5/19]
This makes it possible, by sorting through the q combinations among the a priori
calculated reliability parameters {Wki}, to select the one providing the highest reliability of
the generalized data and to ensure the highest data processing speed. As a result, a new
method is successfully created to determine the reliability weighting parameters (RWPs)
for processing received multi-position signals, under any noise conditions providing a
reliability no worse than autoselection or majorization, and providing better reliability
under favorable conditions.
The indicated advantages and also the features of the present invention are explained by
the best embodiment of the invention, with references to the attached drawings.
Fig. 1 shows the block diagram for a device realizing the claimed method for determining the
reliability weighting parameters, and also their application for processing received multiposition signals;
Fig. 2 shows the block diagram for the switching unit in Fig. 1;
Fig. 3 shows the block diagram for the shaper in Fig. 1;
Fig. 4 shows a representation of the output signal for a diversity channel;
Fig. 5 shows the timing for operation of the device;
Fig. 6 shows a representation of the signals at the output of the diversity channels, at the
input of the storage device in Fig. 1;
Fig. 7 shows representations of the signals at the output of the storage device in Fig. 1;
Fig. 8 shows the structure of the output (generalized) signal at the output of the device;
Fig. 9 shows the flow chart of the algorithm for selecting the combination {Whi} using
the programmable logic array (PLA) in Fig. 1;
Fig. 10 shows the flow chart of the algorithm for the PLA in Fig. 1 forming a sequence of
pulsed r-bit signals in parallel binary code, containing information signals
The dotted lines for the signals in the drawings (Figs. 4, 6, 7, 8) represent possible forms for
these signals, while the solid lines show the signals which are known a priori. An exception is
the fragments in Figs. 4 and 6 (an example is given for representation by the solid lines of
specific levels of the four-position signals and their corresponding two-bit signals in parallel
binary code, following the first marker, shown on these drawings). On the diagrams, time (t) is
given along the x-axis while the voltage (u) is given along the y-axis.
Since the claimed method for determining the RWPs and also their application for processing
received multi-position signals is realized during operation of the device, it is described in detail
in the section describing the operation of the device.
The device for receiving multi-position signals (Fig. 1) contains: storage device 1, memory
unit 2, controller 3, switching unit 4, shaper 5, trigger 6, decoder 7, pulse shapers 8 and 9,
delay element 10, OR gate 11, trigger 12, programmable logic array (PLA) 13, switch 14,
binary counters 15, 161, ..., 16n, 17, delay element 18, decoder 19, delay element 20, bank of
delay elements 21, comparator 22, delay element 23, gate 24, registers 25 and 26, gate 27,
delay element 28.
Switching unit 4 (Fig. 2) contains register 29, decoder 30, bus line cross-connect unit 31,
combiner 32, gates 331, ..., 33q.
Shaper 5 (Fig. 3) contains gates 341, ..., 34n, cross-connect unit 31, comparators
361, ..., 36r.
The inputs of storage device 1 are the inputs for the device (Fig. 1), to which the pulsed r-bit
signals of the n diversity channels are fed in parallel binary code, accompanied by clock
pulses and separated by markers, including information and test signals (see Fig. 6). (It is
assumed that transformation of the original structure of the signals, represented in Fig .4, to the
structure in Fig. 6 has already been accomplished and is done in the usual fashion.) The outputs
of storage device 1 are connected to data busses "D" and to address busses "A" of memory unit
2, where the address busses are also connected to the first output of controller 3.
Patent 2339164
[p. 6/19]
The data busses are connected to the first input of switching unit 4, the output of which
is connected to the bus lines of the first input of PLA 13. Some of the bus lines of the first
input of PLA 13 are also connected to the address busses. The marker pulse line of the
data bus is additionally connected to the counting input of binary counter 15, to the control
input of gate 24, and through delay element 28 to the input of binary counter 17 for
resetting the counter to the zero state (RESET "0") , while the clock pulse line is
additionally connected to the control input of gate 27.
The READ/WRITE input of memory unit 2 is connected to the output of trigger 6.
The bus lines of the second output of controller 3 are connected to the first input of switch
14 and through bank 21 of delay elements to the information inputs of register 26, while its
third output is connected to the first input of trigger 6, the RESET "0" input of binary counter
15, the second input of switching unit 4, the second input of trigger 12, and the RESET "0"
inputs of registers 25 and 26. The first input of controller 3 is connected to the output of pulse
shaper 8, the second input of trigger 6, the third input of switching unit 4, the control input of
shaper 5, and through delay element 18 to the RESET "0" inputs of binary counters 161, ...,
16n. The second input of controller 3 is connected to the output of OR gate 11, to the first input
of trigger 12.
The information outputs of binary counter 15 are connected to the corresponding inputs of
decoder 7.
The first output of decoder 7 is connected to the input of pulse shaper 8, and its second output
is connected to the input of pulse shaper 9.
The output of pulse shaper 9 through delay element 10 is connected to the second input
of OR gate 11, the first input of which through delay element 20 is connected to the output
of decoder 19.
The output of trigger 12 is connected to the control input of switch 14 and the third input of
PLA 13.
The second input of switch 14 is connected to the output of gate 27, and its output is
connected to the second output of PLA 13.
The bus lines of the first output of PLA 13 are connected to the counting inputs of binary
counters 161, ..., 16n, the second output of PLA 13 is connected to the counting input of binary
counter 17, while the third output of PLA 13 is the output of the device.
The information outputs of binary counters 161, ..., 16n are connected to the corresponding
information inputs of shaper 5, the output of which is connected to the fourth input of switching
unit 4.
The information outputs of binary counter 17 are connected to the corresponding information
inputs of register 25, decoder 19, and the bus lines comprising the first input of comparator 22.
The second input of comparator 22 is connected to the output of gate 24, while its output is
connected through delay element 23 to the control inputs of registers 25 and 26, at which the
signal arrives that allows rewriting of the input data into the register.
The inputs of gate 24 are connected to the information outputs of register 25, while the inputs
of gate 27 are connected to the information outputs of register 26.
Functional relationships of switching unit 4 (Fig. 2) The information inputs of register 29 are
the fourth input of switching unit 4, while its information outputs are the input of decoder 30.
The RESET "0" input of register 29 is connected to the third input of unit 4, while its control
input (at which the signal arrives that allows rewriting of the input data into the register) is
connected to the second input of unit 4. The outputs of decoder 30 are connected to the
corresponding control inputs of gates 331, ..., 33q. The information inputs of gates 331, ..., 33q
are connected to the corresponding outputs of bus line cross-connect unit 31, while their
outputs are connected to the inputs of combiner 32, the output of which is the output of
switching unit 4. The first input of switching unit 4 is the input of bus line cross-connect unit
31.
Patent 2339164
[p. 7/19]
For each input bus line of unit 31 there must be q output busses, the composition of the
input lines for each separate gate among 331, ..., 33q is analogous to the composition of the
input bus lines of unit 31, but in this case the variants of the distribution of r-bit signals for
different diversity channels are different for each line. For two variants selected at random,
it is always observed that the elementary data of the j-th diversity channel arrive at least at
the location of the r-bit signals of the i-th diversity channel (i, j = 1, 2, ..., n; i ≠ j ) , where
i and j are the diversity channel numbers while n is the total number of channels.
Functional relationships for shaper 5 (Fig. 3). The information inputs of gates 341, ..., 34n are
the information inputs of shaper 5, their control inputs are connected to the control input of
shaper 5, while the outputs of gates 341, ..., 34n are connected to the inputs of cross-connect
unit 35 and, with the help of this unit, are connected in pairs to comparators 361, ..., 36s. For
example, if n = 5, then the pairs of gate numbers (diversity channel numbers) are associated as
follows: 1,2; 1,3; 1,4; 1,5; 2,3; 2,4; 2,5; 3,4; 3,5; 4,5. The outputs of comparators 361, ..., 36s
are the output of shaper 5.
The device (Fig. 1) operates as follows.
For specified values of n (the number of diversity channels) and m (the number of signal
positions), the set of RWPs from which the optimal combination of RWPs (providing the
highest reliability of the output r-bit signals) is selected from the results of processing the test rbit signals in the device are calculated in advance (a priori), and this optimal combination is
used for processing the information r-bit signals. The set of RWPs {Wki}, k = 1, ..., q i = 1, ..., n
(where q is the number of calculated RWP combinations, n is the number of diversity
channels) represents an nq matrix. Each individual weighting parameter Wki relates to the k-th
combination and to the i-th diversity channel. The higher the value of an individual RWP
compared with other individual RWPs included in the same combination, the greater the weight
of the r-bit signal corresponding to it. If the values of the positions of several r-bit signals,
arriving from different diversity channels and corresponding to the same transmitted signal, are
the same, then the values of the individual RWPs corresponding to each of them are summed,
and as a result a weighted-sum reliability estimate Wke is obtained for the identified position e
of the m-position signal. When the method is implemented using the device (Fig. 1),
information about Wki and Wke is contained in the data generated in this device and
transformed in it during its operation, which are represented in the form of an ensemble of
electrical signals.
At the inputs of the device, r-bit signals arrive in parallel binary code, comprising blocks of
elementary data of n diversity channels, where the structures of the signals are identical at the
input and output (see Figs. 6 and 8). The input r-bit signals, with the help of a receiver (not
shown in Fig. 1), are formed from w-position signals (for example, a representation of a fourposition signal is shown in Fig. 4).
During processing of the r-bit signals containing blocks of elementary data, the device
sequentially operates in three modes (Fig. 5).
When the device is turned on, command signals arrive from controller 3 that are analogous
to those arriving at the end of operation in the third mode. The device is made ready to operate
with the r-bit signals comprising blocks of elementary data in the diversity channels, in order to
obtain r-bit signals of the generalized block of elementary data.
The device is operated in the first mode to order the diversity channels according to the
reliability Ntestreli of the r-bit signals arriving at the inputs of the device (where Ntestreli is
the number of reliable test r-bit signals in the block of elementary data for the i-th diversity
channel).
Operation of the device in the first mode involves the following.
At the inputs of the device (the inputs of storage device 1, Fig. 1), r-bit pulsed signals arrive
in parallel binary code, accompanied by clock pulses "T" and separated by markers "M".
Patent 2339164
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"T" is an indicator of the presence of an r-bit signal, while "M" is an indicator of the
end of a block of elementary data and appears simultaneously with the last r-bit signal of
the block of elementary data. Fig. 6 shows representations of signals with blocks of
elementary data for four-position signals (m = 4, r = 2).
Compensation of signal time delays occurs in storage device 1. From its output, the
temporally coincident r-bit signals of the blocks of elementary data (Fig. 7) (information and
test signals), accompanied by address data, arrive at busses "D" and "A" respectively (Fig. 1).
The state of trigger 6 is selected by ensuring that memory unit 2 is reset to the WRITE state,
therefore r-bit signals arriving from storage device 1 (Fig. 7) arrive at the memory elements of
memory unit 2, and the address of the r-bit signal corresponds to the memory element
number. Signals from the output of storage device 1 through switching unit 4 arrive at the first
input of PLA 13.
PLA 13 is programmed by receiving only test r-bit signals arriving at its input to which
certain addresses correspond. If the test r-bit signals are not distorted by noise (i.e., are
reliable), then they match the corresponding reference signals. In this case, a pulse appears in
each bus line for the first output of PLA 13, arriving at the counting input of the corresponding
binary counter 161, ..., 16n and changing its state to one. If the test r-bit signal of the i-th
diversity channel is unreliable, then PLA 13 does not deliver a pulse to the counting input of
binary counter 16i. At the end of the operating cycle of storage device 1, the states of binary
counters 161, ..., 16n will determine the values of Ntestreli, i = 1, ..., n.
The end of the operating cycle for storage device 1 coincides with the M signal, fed from the
output of storage device 1 to the counting input of binary counter 15, the state of which
becomes "1". The corresponding signals from the information outputs of binary counter 15
arrive at the inputs of decoder 7, initiating a signal at its first output for which the leading edge
coincides with the leading edge of the pulse formed by pulse shaper 8, which arrives at the first
input of controller 3 and shifts the device to the second mode. At the same time, this signal
("START MODE 2") arrives at the second input of trigger 6, changes its state, and from the
output of trigger 6 the READ signal arrives at the READ/WRITE input of memory unit 2.
At the same time, the signal "START MODE 2" arrives at the control inputs of switching unit
4 and shaper 5, allowing generation of a switching programming code datum and writing this
datum into the register of the switching unit 4. Depending on the value of the switching program
code datum, the distribution of r-bit signals over output busses of switching unit 4 changes.
And r-bit signals with the minimum value of Ntestreli arrive at the location of the bus lines for
the first diversity channel, and the signals with Ntestrelj arrive at the location of the lines for
the second diversity channel, where Ntestrelj ≥ Ntestreli and so forth. Data arrive at the location of
the lines for the n-th (and last) diversity channel for which the value of Ntestrels is maximum. If it
turns out that the Ntestreli and Ntestrelj to be compared are equal, where i > j, then Ntestreli >
Ntestrelj is selected in order to avoid conflicts relative to the operating logic of shaper 5. Thus if
all the test r-bit signals are reliable in the blocks of elementary data for all the diversity channels
corresponding to the same transmitted block of elementary data, then according to the operating
logic of shaper 15, Ntestreln > Ntestreln-1 > ..... > Ntestrel2 > Ntestrel1.
Thus in the claimed method, the numbers i = 1, ..., n of the diversity channels are ordered
according to Ntestreli. To each diversity channel is assigned a number, depending on the value of
Ntestreli, i = 1, ..., n.. The ordering rule is: Ntestreln ≥ Ntestreln-1 ≥ ...Ntestreli..... Ntestrel2 ≥
Ntestrel1. Such ordering corresponds to the structure of the RWP combinations: in the
combinations, the values of the individual RWPs are placed from left to right in order of
increase.
Patent 2339164
[p. 9/19]
There is no longer any need to rearrange the individual RWPs within the combination (the
number of such rearrangements is equal to n!, i.e., 120 for n = 5), and the amount of
computations in implementation of the method is considerably reduced.
The signal "START MODE 2", delayed by half a repetition period for "T" (1/2 TT) in
delay element 18, arrives at the RESET "0" inputs of the binary counters 161, ..., 16n and
resets their state to "0".
The operation of the device in the second mode is accomplished with the aim of selecting
the optimal combination of RWPs, to which corresponds the maximum number of reliable test
r-bit signals in the generalized block of elementary data (the flow chart of the algorithm for
operation of the device in the second mode is presented in Fig. 9).
Operation of the device in the second mode involves the following.
Address data from the first output of controller 3 arrives at the address busses "A", initiating
output of test r-bit signals from the corresponding memory elements of memory unit 2. The
number of test data output cycles is equal to q (where q is the number of all RWP
combinations). Simultaneously with the address data, data containing information about the
number assigned to the RWP combination arrive at the second output of controller 3, where an
unchanged data sequence on the number assigned to the k-th RWP combination corresponds to
changing address data for the k-th cycle..
Data on the number assigned to the RWP combinations from the second output of controller
3 arrive through switch 14 at the second input of PLA 13. Such an operating mode for switch
14 is specified by the signal arriving from the output of trigger 12. At the same time, this signal
arrives at the third input of PLA 13, ensuring its operation in the second mode.
PLA 13 in the second mode is programmed so that the test r-bit signals arriving at its first
input, accompanied by address data, are transformed according to the RWP combination
(information about which is contained in the data arriving at the second input of PLA 13) to
generalized r-bit test signals, which are compared with the reference signals corresponding to
them. Finally, if the generalized r-bit test signal is reliable, a pulse arrives at the second output
of PLA 13 and accordingly at the counting input of binary counter 17.
At the end of the k-th data output cycle from memory unit 2, the state of binary counter 17 is
determined by the number Ntestrelgenk (where Ntestrelgenk is the number of reliable
generalized r-bit test signals that can be obtained using the k-th RWP combination).
The information outputs of binary counter 17 are connected to the first input of comparator
22, at the second output of which a datum corresponding to Ntestrelgenu (u < k) arrives from
register 25 through gate 24, opening when a marker signal ("M") arrives at its control input.
If it turns out that Ntestrelgenk ≥ Ntestrelgenu, then a pulse delayed by 1/4 TT arrives from
the output of comparator 22 through delay element 23. When this pulse arrives at the control
input of register 25, the datum containing information about Ntestrelgenk is transferred to the
memory of register 25. At the same time (i.e., with a delay by 1/4 TT in the bank of delay
elements 21), the datum corresponding to the number assigned to the k-th RWP combination
arrives at the memory of register 26 from controller 3. Binary counter 17 is reset to the initial
state by marker pulse "M", delayed by 1/2 TT in delay element 28.
If Ntestrelgenk ≥ Ntestrelgenu, the pulse does not arrive at the output of comparator 22: the
datum corresponding to Ntestrelgenu remains in register 25 and the contents of register 26 also
remain unchanged.
At the end of all the output cycles for the r-digit test signals from memory unit 3 in mode 2,
the datum corresponding to Ntestrelgenj, the value of which is maximum, is found in register
25 while the datum corresponding to the j-th RWP combination is found in register 26.
Patent 2339164
[p. 10/19]
If after the v-th cycle, the number Ntestrelgenv is equal to the number of r-bit test signals
in the block of elementary data, then at the output of decoder 19, a signal is formed which
is delayed by 3/4 TT in delay element 20 and arrives at the second input of controller 3
through OR gate 11, stopping the operation of the device in the second mode before all
cycles have run (i.e., prematurely).
If the second mode did not stop prematurely, then after all cycles of the second mode
have run, the state of binary counter 15 is such that a signal stopping operation of the
device in the second mode arrives at the second input of controller 3, from the second
output of decoder 7 through delay element 10 (time delay 3/4 TT), through the second
input of OR gate 11.
From the output of OR gate 11, the signal also arrives at the input of trigger 12 and changes
its state in such a way that a signal arrives from its output which shifts PLA 13 and switch 14
to the third mode.
The device is operated in the third mode with the aim of obtaining generalized r-bit
information signals according to the optimal RWP combination, information about which is
contained in the memory of register 26 (flow chart of the algorithm for operation of the device
in the third mode is presented in Fig. 10).
Operation of the device in the third mode involves the following.
From the first output of controller 3, address data arrives at the address busses "A" of
memory unit 2, initiating sequential output of all the r-bit signals accumulated in it, which
(accompanied by address data) arrive at the first input of PLA 13. Data containing information
about the number assigned to the optimal RWP combination arrive simultaneously at the
second input of PLA 13. Their values during operation of the device in the third mode remain
unchanged, and correspond to the datum stored in the memory of register 26. The simultaneity
of their arrival is ensured by the method of shaping, involving strobing of the signals arriving
from the information outputs of register 26 at the inputs of gate 27, by the clock pulses "T"
arriving at the control input of gate 27.
PLA 13 is programmed in such a way that the generalized r-bit signals, accompanied by "T"
and "M" and formed according to the optimal RWP combination, arrive at its third output,
which is the output of the device.
At the end of the operation of the device in the third mode, from the third output of
controller 3 the "END MODE 3" signal arrives at the first input of trigger 6, changing its state.
From the output of trigger 6, the signal arrives at the READ/WRITE input of memory unit and
shifts memory unit 2 to WRITE mode. The "END MODE 3" signal also arrives at the second
input of trigger 12, and changes its state. The signal from the output of trigger 12 arriving at the
control input of switch 14 and the third input of PLA 13 shifts them to a state ready to operate
with the next data block in the first mode. Registers 25 and 26 are shifted to the initial state by
the "END MODE 3" signal. The "END MODE 3" signal also arrives at the second input of
switching unit 4, and also shifts the register of unit 4 to the initial state.
After some waiting, the device resumes operation in the first mode, but now with the r-bit
signals of the next data blocks for the diversity channels corresponding to the same
transmitted block.
Operation of switching unit 4.
The datum of the switching program code arrives at the information inputs of register 29,
which are the fourth input of switching unit 4, and is saved to the memory of this register when
the "START MODE 2" signal arrives at its control input (which is the third input of unit 4).
Register 29 is reset to the initial state when the "END MODE 3" signal arrives at its "RESET 0"
input (which is the second input of unit 4).
Patent 2339164
[p. 11/19]
Signals from the output of register 29 arrive at the input of decoder 30, and depending on
the switching program code, a signal appears at one of the outputs of decoder 30, arriving
at the control input of the corresponding gate from among 331, ....., 33q and opening it. The
zero (initial) state of register 29 means identical distributions of data over the input and
output bus lines of unit 4. Information and test r-bit signals arrive at the input of bus line
cross-connect unit 31, which is also the first input of unit 4. A certain variant of the crossconnection, accomplished a priori in unit 31, corresponds to each variant for the
distribution of input information and test r-bit signals over the output bus lines. The choice
of the required cross-connection variant is made using a gate from among 331, ....., 33q,
which can be opened in accordance with the switching program code. In combiner 32, a
function is applied to signals belonging to similar output bus lines of gates 331|,..., 33q that
is analogous to that realized in the OR gate.
Operation of shaper 5.
Data corresponding to the values Ntestrel1, Ntestrel2, ..., Ntestreln-1, Ntestreln arrive at the
information inputs of gates 341, ..., 34n, which open when the "START MODE 2" signal arrives
at their control inputs (which are connected to the control input of shaper 5), ensuring that these
data arrive at the inputs of cross-connect unit 35. In cross-connect unit 35, the outputs of each
pair of selected gates are a priori connected to the inputs of the corresponding comparators 361,
..., 36s. At the end of operation of the device in mode 1, depending on the values of Ntestrel1,
Ntestrel2, ..., Ntestreln-1, Ntestreln, signals appear at the outputs of certain comparators from
among 361, ..., 36s that are elements of the switching program code datum arriving at the output
of shaper 5.
Features of PLA 13 operation.
PLA 13 is essentially a finite automaton [K. A. Pulkov, ed., Principles of Cybernetics.
Theory of Cybernetic Systems (College Textbook) [in Russian], Vyssh. Shkola, Moscow
(1976), Ch. 21. 408 pp.], for which a certain combination of the finite set of its output signals
corresponds to each combination of the finite set of input signals. The functional relationship
between the input and output signals is specified a priori (when programming the PLA)
according to algorithms with flow charts presented in Figs. 9 and 10. Such a design makes it
possible to eliminate a series of calculations and to obtain a finished result in the form of the
output signals of the PLA, corresponding to its programmed "response" to the output signals.
In particular, each test r-bit signal has a certain address and a corresponding reference
(undistorted) signal, which makes it possible to a priori obtain the result of comparison of all
possible combinations of the received test r-bit signals and the reference signals corresponding
to them in the form of logic "0" and logic "1" and then to program the PLA so that in the case of
a reliable (undistorted) test r-bit signal, at a certain output of the PLA a pulse appeared (logic
"1") while in the case of an unreliable (distorted) test r-bit signal, no pulse appeared (logic "0").
In operation of the device in the first mode, test and information r-bit signals of n diversity
channels (their structure is presented in Fig. 7) arrive on the "D" bus line of the first input of
PLA 13. At the same time, along the "A" bus lines of the first input of PLA 13, address data
arrive, each of which corresponds to a certain test or information r-bit signal, depending on its
location (and on its number) in the block of elementary data. For the next operation, only test
words are selected according to the value of the address datum. Their position in the block of
elementary data is known a priori. PLA 13 is programmed in such a way that a "1" in the i-th
bit of the word, arriving at the first output of PLA 13, corresponds to a reliable test r-bit signal
of the i-th diversity channel, located among the input signals of other diversity channels, while
a "0" in the j-th bit of this word corresponds to an unreliable test r-bit signal in the j-th
diversity channel.
Patent 2339164
[p. 12/19]
The presence of a "1" in the i-th bit of the word arriving at the first output of PLA 13
means that a pulse arrives along the i-th bus line of the first output of PLA 13 at the
counting input of binary counter 16i (accordingly, no pulse arrives at the counting input of
binary counter 16j).
In operation of the device in the second mode, test r-bit signals of n diversity channels arrive
on the D bus line of the first input of PLA 13 (their structure is presented in Fig. 7),
accompanied by address data, arriving along the "A" bus lines of the first input of PLA 13.
Data on the number assigned to the RWP combinations arrive at the second input of PLA 13,
while a signal corresponding to operation of PLA 13 in the second mode is fed to its third
input. Data arriving simultaneously at the first, second, and third inputs of PLA 13 form
different code combinations, the number of which is finite. PLA 13 is programmed a priori in
such a way that a very definite signal at its second output ("0" or "1") corresponds to each input
combination. The essence of the algorithm realized in PLA 13 during its operation in the second
mode is that according to each possible combination of RWPs, a generalized test r-bit signal is
calculated a priori which is compared with the reference signal corresponding to it (known a
priori), and the result of the comparison is a signal "0" or "1" at the second output of PLA 13.
A match between the values for the test and reference r-bit signals corresponds to the value
"1", while a mismatch between them corresponds to the value "0". A pulse arrives at the
counting input of binary counter 17 in the "1" case, while no pulse arrives in the "0" case.
For operation in the third mode, information and test r-bit signals of n diversity channels
arrive on the D bus line of the first input of PLA 13 (Fig. 7), accompanied by address data
arriving along the "A" bus lines of the first input of PLA 13. Data on the number assigned to
the optimal combination of RWPs (their values do not change during operation of the device in
the third mode) arrive at the second input of PLA 13, while a signal corresponding to operation
of PLA 13 in the third mode is fed to its third input. Data arriving simultaneously at the first,
second, and third inputs of PLA 13 form different code combinations, the number of which is
finite. PLA 13 is programmed a priori in such a way that a very definite output combination
corresponds to each input combination, where the value of the output combination corresponds
to a generalized r-bit signal (test or information signal), arriving at the third output of PLA 13,
which is the output of the device. The essence of the algorithm realized in PLA 13 during its
operation in the third mode is that, according to the selected optimal combination of RWPs,
generalized r-bit signals (test or information signals) are formed, arriving at the output of the
device. And the operational logic of PLA 13 is such that it also forms synchronization signals
("T" and "M"), accompanying the output generalized r-bit signals. The structure of the output
signals of the device (when four-position signals are used) is presented as the representation in
Fig. 8.
Thus in operation of the device, the following method is realized for determining the
reliability weighting parameters and also their application for processing received multiposition signals.
1. Along n diversity channels, m-position signals are received, including information and
test signals, which after reception are transformed to pulsed r-bit-signals, comprising blocks
of elementary data in parallel binary code, accompanied by clock pulses and markers, where
m = 2r, m ≥ 2.
2. The set of RWP combinations {Wki}:{Wki}nopt, k = 1, ..., q , i = 1, ..., n are
precalculated for the pulsed r-bit test signals in each block of elementary data, where k is
the number assigned to the combination, i is the channel number.
The set of RWP combinations are obtained a priori as a result of solving the combinatorial
problem with the help of a personal computer. The initial data when solving the combinatorial
problem are: the number of diversity channels (n) and the number of positions (m) for the
signals used.
If the values of n and m are relatively low, then as a result of solving the combinatorial
problem a finite set of RWP combinations is obtained, the size of which is acceptable for
practical use in obtaining generalized data.
Patent 2339164
[p. 13/19]
For example, q = 166 for n = 5 and m = 4 (where q is the number of calculated RWP
combinations), i.e., a 5166 matrix (Table 1). The RWP combination establishes the
functional relationship between the r-bit signals of the diversity channels corresponding to
the same transmitted signal on the one hand, and the generalized r-bit signal on the other
hand. Each of the RWP combinations obtained by the proposed method establishes a new
functional relationship. This means that when additional RWP combinations are used
(besides what was obtained), the reliability of the generalized r-bit signals is not improved,
while if one combination were to be eliminated, the prerequisites are created for the
reliability to decrease.
3. The test r-bit signals for the blocks of elementary data and the reference signals
corresponding to them are compared, and the numbers i = 1, ..., n of diversity channels are
varied according to the value of Ntestreli, where Ntestreli, is the number of reliable test r-bit
signals in the block of elementary data in the data block of the i-th diversity channel, in order
of decrease in the number of reliable test r-bit signals Ntestreln ≥ Ntestreln-1 ≥ ...Ntestrel2 ≥
Ntestrel1, ordering their numbering relative to Ntestreli (the device for implementation of the
method in this case operates in the first mode).
4. For pulsed r-bit signals comprising blocks of elementary data, Wke is calculated: the
weighted-sum reliability estimate for the value e of the identified position of the m-position
signal, when using the k-th RWP combination, according to the formula
Wki is the reliability weighting parameter of the k-th combination for the ordered i-th
diversity channel,
i1, i2, ... are the ordered numbers assigned to the diversity channels for identical r-bit
signals,
e is the position in the m-position test signal.
For example, when using four-position signals, the possible values of e are equal to 1, 2, 3, 4,
while the reliability estimates corresponding to them are Wk1 , Wk2, Wk3, Wk4.
Let us explain the calculation of the estimates Wke using examples.
Example 1. If e1 = 1, e2 = 2, e3 = 1, e4 = 4, e5 = 1, see Table 2 (where ei is the value of the
elementary datum arriving from the 1st diversity channel), then:
Wk1 = Wk1 + Wk3 + Wk5,
Wk2 = Wk2 ,
Wk4 = Wk4 .
Then for the first RWP combination (k = 1, the values of the combinations are in Table 1):
W11 = 1 + 20 + 62 = 83, W12 = 10, W14 = 30.
Example 2. Same as in Example 1, except k = 2 (the values of the combinations are in
Table 1):
W11 = 11 + 30 + 92 = 133, W12 = 20, W14 = 40.
Example 3. If e1 = 2, e2 = 3, e3 = 2, e4 = 3, e5 = 1, see Table 2, then:
Wk1 = Wk5,
Wk2 = Wk1 + Wk3
Wk3 = Wk2 + Wk4.
Then for the first RWP combination (k = 1, the values of the combinations are in Table
1):
W21 = 62, W22 = 1 + 20 – 21, W23 = 10 + 30 = 40.
The device operates in the second mode when using test r-bit signals.
Patent 2339164
[p. 14/19]
The operation is analogous when working with elementary information data (in this
case, the device operates in the third mode).
5. Among the calculated weighted-sum reliability estimates Wke, e = 1, 2, ..., m,
corresponding to the same transmitted signal, the maximum estimate is determined and the
position egentestk corresponding to it, where egentestk is the position of the generalized (output)
r-bit signal when using the k-th RWP combination.
Explanatory notes.
Example 1 (continued). The maximum value of the reliability estimate is equal to 83,
while the estimate refers to a position value of "1". This means that egentest1 = 1 (k = 1).
Example 2 (continued). The maximum value of the reliability estimate is equal to 133,
egentest2 = 1 (k = 2).
Example 3 (continued). The maximum value of the reliability estimate is equal to 62,
egentest1 = 1 (k = 1).
Examples of the estimates Wk1, Wk2, Wk3, Wk4 for some combinations of e1, e2, e3, e4,
e5 and RWP combinations are calculated, their values and the position values corresponding
to them for generalized r-bit signals, egen, are presented in Table 3.
The device operates in the second mode when using test r-bit signals. The operation is
analogous when working with information r-bit signals (in this case, the device operates in the
third mode).
6. The position values for the generalized test r-bit signals egentestk are compared with
their reference values, and signals are generated which are indicators of the reliability of
the values of these positions (in this case, the device operates in the second mode).
7. Ntestrelgenk is calculated for test r-bit signals, where Ntestrelgenk is the number of
reliable generalized test r-bit signals in the block of elementary data, generated when
using the k-th RWP combination from the set of combinations {Wki}nopt (in this case, the
device operates in the second mode).
8. Among the calculated values of Ntestrelgenk , the highest value is selected and the
RWP combination corresponding to it is determined, {Whi}, k = h, i = 1, ..., n, from the set
of combinations {Wki}nopt, which are considered to ensure the highest number of reliable
generalized test r-bit signals.
9. The optimal RWP combination {Whi}, k = h, i = 1, ..., n is then used when obtaining
the generalized information r-bit signals (in this case, the device operates in the third
mode). In this case, the operations are carried out as in steps 4 and 5, similarly to what was
done when using test r-bit signals.
The results of a study of the claimed method are evidence that it is superior (with respect to
the reliability provided) to autoselection, majorization, and the design of the closest analog
[Russian Federation Patent 2052898], which to a significant extent is due to the successful
combination of a functional correspondence between the r-bit signals (generalized and
arriving from the diversity channels) and the noise conditions. The method provides faster
speed as a result of the decrease in the amount of data to be processed and the simplification
and improvement in the data processing conditions.
When the claimed method is used in processing received four-position signals containing
telemetric information, obtained in launches of aerospace technology products, the reliability
of the generalized telemetry measurements have proven to be better than the reliability
provided by the analogs considered.
The claimed method has commercial applications in receiving diversity digital signals by
telemetry. However, it can also be successfully used in communications systems for various
purposes when signal diversity is used.
Patent 2339164
[p. 15/19]
TABLE 1
Table 1
Reliability weighting parameters Wki for n = 5, m = 4
Table 2
Examples of calculations of the reliability estimates Wke, depending on the values of ei, i = 1, 2, ...,
n, for signals arriving from diversity channels for n = 5, m = 4
Table 3
Examples of obtaining generalized signals egentestk from ei, i = 1, 2, ..., n, for signals
arriving from diversity channels when n = 5, m = 4 for k = 1, 2, ..., 166
KEY for Table 3:
egentestk
Claim
Method for determining reliability weighting parameters for processing received multiposition signals, characterized in that m-position signals, including information and test
signals, are used along n diversity channels, where the signals are transformed to blocks of
elementary data, each of which represents pulsed r-bit signals in parallel binary code,
accompanied by clock pulses and separated by markers, where m = 2r, m ≥ 2, time delays of
the signals along the n diversity channels are compensated, to each pulsed r-bit signal is
assigned an address and they are stored, the pulsed r-bit test signals are compared with the
corresponding references, in each channel the number of matches for the r-bit test signals
Ntestreli, i = 1, 2, ..., n are determined, where Ntestreli is the number of matches in the i-th
channel, the blocks of elementary data for each channel are distributed in order of decrease in the
number of matches Ntestreln ≥ Ntestreln-1 ≥ ...Ntestreli...Ntestrel2 ≥ Ntestrel1, ordering their
numbering relative to Ntestreli and the order of the distribution of blocks of elementary data
is stored, the combinations {Wki} of the reliability weighting parameters (RWPs) are
precalculated for the pulsed r-bit test signals for each block of elementary data
{Wki}n-opt, k = 1, ..., q,
and Wk1 < Wk2 < ... Wk,i... < Wk,n-1, where k is the number assigned to the combination, i is
the channel number, and q is the number of combinations, the corresponding pulsed r-bit test
signals for each block of elementary data are compared for identity and the weighted-sum
reliability estimates {Wke} are calculated for each r-bit test signal in the block of elementary
data according to the formula
Patent 2339164
[p. 16/19]
e = 1, 2, ..., m,
where Wki is the reliability weighting parameter of the k-th combination for the ordered i-th
diversity channel,
i1, i2, ... are the ordered diversity channel numbers for identical pulsed r-bit test signals,
e is the position in the m-position test signal,
among the calculated weighted-sum reliability estimates Wke, e = 1, 2, ..., m, the maximum
weighted-sum reliability estimate is determined as well as the position egentestk (k = 1, 2, ..., q)
corresponding to it for the pulsed r-bit test signal, the weighted-sum reliability estimates are
calculated for the next r-bit test signals and the maximum weighted-sum reliability estimate is
determined as well as the position egentestk (k = 1, 2, ..., q) corresponding to it, the values of
the positions egentestk (k = 1, 2, ..., q) for the test signals are compared with their reference
values, the number of matches are determined, all the above-indicated operations for
determining the number of matches are repeated for each k-th combination and from them is
selected the combination k = h with maximum number of matches and the egentesth
corresponding to it, and the reliability weighting parameters corresponding to the h-th
combination are used for processing received m-position signals .
FIGURES
Patent 2339164
KEY:
[p. 17/19]
d
Fig. 1
c
c
d
c
"D"
RESET
"A"
"T", b
"M", a
RESET
"M", a
"M"
d
d
d
"T", b
c, "START MODE 2"
"START MODE 3"
d
Patent 2339164
[p. 18/19]
Fig. 1
Fig. 2
KEY for Fig. 1 [see previous page]
KEY for Fig. 2:
c, "START MODE 2"
Fig. 3
RESET "0"
d, END MODE 3
Fig. 4
KEY for Fig. 3:
KEY for Fig. 4:
c
Marker
four-position signal
c
c
c
Length of data block
Mode 1
Mode 2
Mode 3
Fig. 5
Wait
Fig. 6
KEY for Fig. 6:
1st bit
2nd bit
"T"
"M"
1st bit
2nd bit
"T"
"M"
1st bit
2nd bit
"T"
"M"
Patent 2339164
[p. 19/19]
Fig. 7
KEY for Fig. 7:
1st bit
2nd bit
1st bit
2nd bit
1st bit
2nd bit
"T"
"M"
Fig. 8
KEY for Fig. 8:
1st bit
2nd bit
"T"
"M"
Fig. 9
KEY for Fig. 9:
Start
Yes
Select {Wki}, i = 1, 2, ..., n
Select {etestti }, i = 1, 2, ..., n
t = Ntest
Select etesttj , i = j from
{etestti}, i = 1, 2, ..., n for
Wetesttj = Wetesttimax
Compare etesttj and etesttreference
Calculate Ntestrelgenk
Compare Ntest relgenk-1 and Ntestrelgenk
Ntestrelgenk-1 < Ntestrelgenk
Yes
Store {Wki}, i = 1, 2, ..., n
End
Fig. 10
KEY for Fig. 10:
Start
Yes
t = Ntot
Select {eti }, i = 1, 2, ..., n
Select etj , i = j from
{eti }, i = 1, 2, ..., n for
Wetj = Wetimax
End