ECE 597
Spring 2006
Electronic Slide Whistle MIDI Controller
Peter F. Klemperer
May 9, 2006
1
Abstract:
The purpose of this project is to create a MIDI controller which will allow a slide whistle
like musical instrument to interface with a MIDI synthesizer. The instrument is designed
in two parts, the mechanical instrument and the electronics to implement the MIDI
interface.
Introduction:
The purpose of this project is to create a MIDI controller which will allow a slide
whistle like musical instrument to interface with a MIDI synthesizer. The slide whistle is
probably best known for its use in slapstick comedy and cartoons. This instrument has,
however, been used in more serious musical compositions. According to Wikipedia,
several notable performers, including Louis Armstrong, Paul Trietsch, have performed or
recorded using this instrument. Furthermore, composers such as Maurice Ravel,
Cornelius Cardew, Alberto Ginastra and several other have composed classical works
employing the slide whistle. One significant motivation for the creation of the MIDI
slide whistle is to allow disabled musicians to perform. This new musical instrument will
expand the accessibility of MIDI synthesizers to a larger group of disabled musicians.
The project will be composed of two parts, the electronic slide whistle and the
MIDI controller interface. The electronic slide whistle will require two sensors, a breath
sensor and a slide position sensor. A Xilinx FPGA serves as the basis of the MIDI
controller to receive the instrument signals and convert them to MIDI format.
2
Design:
The electronic slide whistle midi controller’s design can be broken down into two main
assemblies. The physical slide whistle instrument body and the MIDI interface support
circuitry. These assemblies are marked and can be clearly identified in figure 1. This
document will first describe the physical instrument, then the analog electronics, and
finally the FPGA VHDL.
Instrument:
The instrument consists of two major subparts.
The slide determines the pitch of the sound output
and the breath sensor which determines the
loudness of the tone. These two components are
mounted in a PVC housing designed and
fabricated by the UIUC ECE Machine Shop.
Caliper
The caliper chosen is an Avenger products 6” digital caliper. This caliper is a low-cost
model stocked by the ECE storeroom. There is a two wire serial interface which can be
accessed through the interface port on the caliper body which was used in this product to
interface with the FPGA. This caliper offers 24 bit precision through the serial interface
3
but is limited in its position update rate to roughly 300 ms update period. I would
recommend this product for future projects requiring digital readout distance
measurement, but not for applications which require accurate measurement in time, like
this application. For future improvements on this project I would recommend using a
caliper with a higher update rate as mentioned on this website:
http://www.shumatech.com/support/chinese_scales.htm
Calipers of this type can be obtained from the following distributor as well as pre-built
serial adaptor cables:
http://www.littlemachineshop.com/
Another alternative would be a quadrature encoder based approach which I feel is most
appropriate as it can be used to provide near instantaneous measurement information.
One supplier of linear quadrature encoders can be found here:
http://www.usdigital.com/products/pes/
One final comment is that the sliding action is a large consideration for the slide whistles
suitability for use as an actual instrument. The digital caliper does not have very smooth
sliding action and made it difficult to reliably hit specific notes while playing.
Breath Sensor
The breath sensor used in this project is a Freescale Semiconductor MPXM2010GS 0-1
Psi gage pressure sensor. This pressure range is very appropriate for the human breath
input. The sensor also has some ability to indicate negative pressure if the circuit is
carefully designed. In future projects I would recommend this sensor for it’s suitability
4
as well as low cost. The mouthpiece design used in this project is a piece of 1 inch PVC
underground sprinkler flexible tubing to hard tubing adapter available at Do It Best
hardware store.
Circuit:
The circuitry can be divided into two major subparts: the analog circuitry and the FPGA
VHDL. The analog circuitry includes the analog to digital circuitry and buffers for the
breath sensor, the caliper line level adaptor circuit, and the MIDI output circuitry. The
FPGA can be broken into four parts: the caliper serial to parallel, the MIDI serial
interface, the breath sensor, and the pinout definition file (UCF).
Analog-to-Digital and Buffer
The analog to digital circuitry is the most complicated circuit in this project and is
illustrated in figure 5. The initial opamp is used to convert the differential 0-40 mV
output from the pressure sensor to the 0-5 V reference voltage required by the analog to
digital converter in the next stage. A LM324N opamp was chosen for this application
due to its ease of availability from the ECE electronics shop and its ability to operate in a
wide range of voltages. The analog to digital converter is an ADC0841 which is operated
in continuous operation mode. The schematic in figure 5 is taken directly from the
datasheet. One drawback of this configuration is that the start on power up button must
be pressed on initial startup of the device, this could be automated using the FPGA or
5
through some other circuit design. Finally this output was buffered before being input to
the FPGA to assure that it met LVTTL specifications using a standard hex buffer, just
about any choice will do and is probably unnecessary. An extremely steady supply
voltage for the sensor is required as the differential voltage output from the sensor will be
directly affected by the supply voltage fluctuations, and with only a few mV range, only a
few mV fluctuation on the supply is acceptable.
Caliper Line Level Circuitry
The digital readout caliper is operated by a 1.5 volt battery and the serial output uses 0V
and 1.5 V as the low and high logic levels respectively for the clock and data lines. A 1.5
V and ground voltage level reference is also provided in the output from the caliper. An
opamp circuit is used to raise the signal voltages to zero and five volt levels required for
the LVTTL interface standard to use with the FPGA. The circuit is illustrated in figure 4
and is directly connected to the pins of the FPGA.
MIDI Output Circuitry
The MIDI interface is a 5 mA current loop interface which uses 5-pin DIN standard
cables. The circuit I was used was lifted from the schematic described on:
http://www.cnmat.berkeley.edu/~norbert/midi/node6.html
This circuit uses a 7417N buffer to interface with the FPGA output to the pin 5 of the din
connector through a 220 ohm resistor. The third pin of the connector is connected to
6
ground and the fourth pin is connected to the five volt supply through another 220 ohm
resistor. This interface is very simple to implement and works well with the Yamaha
MIDI-to-USB adaptor.
FPGA
The FPGA circuitry consists of a Digilent D2 board containing an XC2S200 FPGA. This
board has several output ports which provide an unregulated nine volt supply. This
supply was tapped to a standard 7805 regulated supply to provide the five volt reference
supply for the analog circuitry. The Xilinx ISE 8.1 tool flow was used for VHDL
synthesis and bitfile download.
VHDL:
Breath Sensor
The breath sensor VHDL is found in figure 5 but is very simple. It reorders the bits for
correct data processing and sets a minimum threshold for output. This threshold had to
be set very high as the supply noise on the pressure sensor was carrying all the way
through to the FPGA and as a result, little tone volume modulation could be achieved. A
better implementation might attempt to remove the supply noise using DSP techniques
and I think this could be implemented relatively easily.
Caliper Interpolation
7
The caliper output is a clock and data line and the signal is illustrated in figure 3. The
VHDL describing the caliper input can be found in Figure 7. The clock line is monitored
for a rising edge and the data lines value is stored. Each set of information consists of 48
bits, 24 bits of relative scale measurement and 24 bits of measurement in two’s
compliment format with MSB first. The caliper output is limited to roughly three times
per second, which sounds rather rough when played as an instrument and not a smooth
continuous progression as one expects from a slide whistle. A simple linear interpolation
scheme was implemented to provide 32 samples of the pitch instead of just 3 per second.
This sounds much smoother but a higher update rate, probably close to the maximum
capabilities of the MIDI standard would be a better choice. The combination of a
quadrature encoder and some DSP will provide a much nicer solution.
MIDI Serial Interface
The MIDI interface VHDL is very simple with a single line serial. The 50 MHz clock is
down clocked by a factor of 1600 to provide the correct bit rate for the MIDI standard.
Then a sort of circular shift register is used to push the MIDI data out over the line.
Figure 6 contains the VHDL for this design. The MIDI sequence that is sent is:
Note off
Note On
Note Number
Velocity
8
Pitch Bend
The note number is determined from the first 12 bits of the caliper’s 24 bit output and the
pitch bend is determined from the remaining 12 bits. The velocity is received from the
breath sensor’s VHDL block. The note number of the previous note is stored so that it
can be shut off before the next note begins to provide a smooth transition. It is important
when using this type of scheme that the MIDI synthesizer has a “legato” mode which
helps create smooth note transitions or else using sample which have no attack so that the
transitions are masked. This MIDI signal is then picked up by the Yamaha MIDI-to-USB
adaptor. A few good free programs can be used to debug the MIDI interface in windows.
One program is called “MIDI Input Viewer” which is a bit buggy but provides a great
graphical view of the incoming MIDI stream. For a synthesizer I would recommend the
demonstration version of the program called “Pro-53” which can also be found online
and provides a pleasing slide whistle sound and a good “glide” mode.
FPGA Pinout Definitions
The FPGA pinout definitions used in this project can be found in figure 8. The UCF file
shows that I used LVTTL levels for input and output. The FPGA cannot source or sink
very much current and buffers should be used to protect the delicate circuitry. Xilinx
datasheets for the Spartan 2 should help in the selection of a voltage level standard if
LVTTL will not work in future applications.
9
Figure 1: Slide Whistle System Overview
10
Figure 2: Breath Sensor Diagram
11
Figure 3: Caliper Serial Output
Figure 4: Caliper Circuit
12
Figure 5: slidewhistle.vhd
----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
20:01:08 04/17/2006
-- Design Name:
-- Module Name:
slidewhistle - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity slidewhistle is
Port ( atod : in STD_LOGIC_VECTOR (7 downto 0);
caliper : in STD_LOGIC_VECTOR (1 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
midi : out STD_LOGIC;
rst : in STD_LOGIC;
brdled : out STD_LOGIC;
clk : in STD_LOGIC);
end slidewhistle;
architecture Behavioral of slidewhistle is
component midiComp Port (
rst : in std_logic;
clk : in std_logic;
note : in std_logic_vector(7 downto 0);
midi: out std_logic;
velocity : in std_logic_vector(6 downto 0);
pitch : in std_logic_vector(11 downto 0));
end component;
component bufgp Port (
I : in std_logic;
O : out std_logic );
end component;
component caliperComp
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
caliperclk : in STD_LOGIC;
caliperdata : in STD_LOGIC;
width : out STD_LOGIC_VECTOR (15 downto 0);
note : out STD_LOGIC_VECTOR (7 downto 0);
pitch : out STD_LOGIC_VECTOR(11 downto 0));
end component;
signal clkcount : std_logic_vector(23 downto 0);
signal rst_buf : std_logic;
signal pitch : std_logic_vector(11 downto 0);
13
signal
signal
signal
signal
begin
note : std_logic_vector(7 downto 0);
caliperWidth : std_logic_vector(15 downto 0);
velocity : std_logic_vector(6 downto 0);
atod_1, atod_2, atod_3, atod_0, atod_sum, atod_avg : std_logic_vector(7 downto 0);
midi0 : midiComp port map (
rst => rst_buf,
clk => clk,
note => note,
midi => midi,
velocity => velocity,
pitch => pitch);
caliper0 : caliperComp port map (
clk => clk,
rst => rst_buf,
caliperclk => not caliper(0),
caliperdata => not caliper(1),
width => caliperWidth,
note => note,
pitch => pitch);
RESETBUF : BUFGP port map( I=>rst, O=>rst_buf );
--led(1) <= caliper(1);
--led(0) <= caliper(0);
--led(5 downto 2) <= caliperWidth(15 downto 12);
--led(7 downto 2) <= not caliperWidth(5 downto 0);
--led(1 downto 0) <= not caliper(1 downto 0);
--led(0 to 7) <= caliperWidth(15 downto 8);
led(0) <= caliperWidth(10);
led(1) <= caliperWidth(9);
led(2) <= caliperWidth(8);
led(3) <= caliperWidth(7);
led(4) <= caliperWidth(6);
led(5) <= caliperWidth(5);
led(6) <= caliperWidth(4);
led(7) <= caliperWidth(3);
--led <= note;
--led <= X"F0";
--led(6 downto 0) <= not note(6 downto 0);
--led <= not atod;
process( clk, rst_buf )
begin
if rst_buf = '1' then
clkcount <= X"000000";
brdled <= '0';
else
if clk'event and clk = '0' then
-------------------
if( clkcount <= X"00000F" ) then
atod_3(0) <= not atod(7);
atod_3(1) <= not atod(6);
atod_3(2) <= not atod(5);
atod_3(3) <= not atod(4);
atod_3(4) <= not atod(3);
atod_3(5) <= not atod(2);
atod_3(6) <= not atod(1);
atod_3(7) <= not atod(0);
atod_2 <= atod_3;
atod_1 <= atod_2;
atod_0 <= atod_1;
atod_sum <= atod_3 + atod_2 + atod_1 + atod_0;
atod_avg <= "00" & atod_sum(7 downto 2);
clkcount <= X"000000";
else
clkcount <= clkcount + 1;
end if;
14
if( atod < "00110000" ) then
velocity <= not atod(6 downto 0);
else
velocity <= "0000000";
end if;
end if;
end if;
end process;
end Behavioral;
15
Figure 6: midi.vhd
----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
20:45:33 04/17/2006
-- Design Name:
-- Module Name:
midi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity midiComp is
Port ( clk : in
rst : in
STD_LOGIC;
STD_LOGIC;
note : in STD_LOGIC_VECTOR(7 downto 0);
pitch: in STD_LOGIC_VECTOR(11 downto 0);
velocity : in std_logic_vector(6 downto 0);
midi : out STD_LOGIC);
end midiComp;
architecture Behavioral of midiComp is
signal midipointer : natural;
signal midiclock
: std_logic_vector(11 downto 0);
signal midistream
: std_logic_vector(89 downto 0);
signal pitchbend
: std_logic_vector(15 downto 0);
signal velocity_on : std_logic_vector(6 downto 0);
signal note_on, note_off : std_logic_vector(7 downto 0);
begin
process( rst, clk )
begin
if rst = '1' then
midi <= '1';
midipointer <= 0;
midiclock <= X"000";
-note off
note vel
note #
note on
-midistream <= "1011001000" & "1" & note & "0" & "1100000000" & "1011001000" & "1"
& note & "0" & "1100100000";
-midistream <= "1100000000" & "1011001000" & "1" & note_off & "0" & "1100100000" &
"1011001000" & "1" & note & "0";
midistream <= "1" & pitchbend(15 downto 8) & "0" & "1" & pitchbend(7 downto 0) &
"0" & "1111000000" &
"1011001000" & "1" & note_on & "0" & "1100100000"
&
"1011001000" & "1" & note_off & "0" &
"1100000000";
else
if clk'event and clk = '0' then
16
-midistream <= "1100000000" & "1011001000" & "1" & note_old & "0" &
"1100100000" & "1011001000" & "1" & note & "0";
-midistream <= "1011001000" & "1" & note_on & "0" & "1100100000" &
"1011001000" & "1" & note_off & "0" & "1100000000";
midistream <= "10" & "10" & pitchbend(15 downto 11) & "0" &
"10" & pitchbend(10 downto 4) & "0" & "1111000000"
&
-midistream <= "10" & "1000000" & "0" & "10" & "0000001" & "0" & "1111000000" &
"10" & velocity_on & "0" & "1" & note_on & "0" &
"1100100000" &
"1011001000" & "1" & note_off & "0" &
"1100000000";
if midipointer < 90 then
midi <= midistream(midipointer);
else
midi <= '1';
end if;
if midiclock = X"000" then
if midipointer >= 2000 then
midipointer <= 0;
pitchbend <= pitch & "0000";
note_off <= note_on;
note_on <= note;
velocity_on <= velocity;
else
midipointer <= midipointer + 1;
end if;
end if;
if midiclock > 1650 then
midiclock <= X"000";
else
midiclock <= midiclock + 1;
end if;
end if;
end if;
end process;
end Behavioral;
17
Figure 7: caliper.vhd
----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
10:11:30 04/18/2006
-- Design Name:
-- Module Name:
caliper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity caliperComp is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
caliperclk : in STD_LOGIC;
caliperdata : in STD_LOGIC;
width : out STD_LOGIC_VECTOR (15 downto 0);
note : out STD_LOGIC_VECTOR (7 downto 0);
pitch : out STD_LOGIC_VECTOR( 11 downto 0));
end caliperComp;
architecture Behavioral of caliperComp is
signal caliperclk_deb : std_logic_vector(127 downto 0);
signal caliperclk_debounced : std_logic;
signal caliperclk_old : std_logic;
signal data_reg : std_logic_vector(49 downto 0);
signal data_reg_hold : std_logic_vector(23 downto 0);
signal data_reg_hold_old, data_reg_hold_new, data_reg_hold_new_temp, data_reg_hold_temp,
data_reg_hold_temp2 : std_logic_vector(47 downto 0);
signal data_reg_pointer : natural;
signal pitch_scaler_old : std_logic;
signal data_reg_scaler : std_logic_vector(31 downto 0);
begin
width(15 downto 0) <= data_reg_hold(23 downto 8);
--width(0) <= caliperclk_debounced;
process( data_reg_hold, rst )
begin
if rst = '1' then
note <= X"2B";
else
-if data_reg_hold(15 downto 0) > X"FFFF" then
-note <= X"33";
-else
-note <= X"3C";
-end if;
18
if data_reg_hold(23 downto 12) < "0000000" then
note <= X"33";
pitch <= "000000000000";
else
note <= X"33" + data_reg_hold(20 downto 13);
pitch <= data_reg_hold(12 downto 1);
--pitch <= "000000000000";
end if;
end if;
end process;
process(rst, clk)
begin
if rst = '1' then
data_reg <= X"000000000000" & "00";
data_reg_hold <= (others=>'0');
data_reg_pointer <= 0;
caliperclk_deb(7 downto 0) <= (others=>caliperclk);
caliperclk_old <= caliperclk;
else
if clk'event and clk = '1' then
caliperclk_deb(127 downto 0) <= caliperclk_deb(126 downto 0) &
caliperclk;
caliperclk_old
<=
caliperclk_debounced;
pitch_scaler_old <= data_reg_scaler(20);
if( data_reg_scaler = X"00000000" ) then
data_reg_hold_temp
<= X"000000" & (data_reg_hold_new(23
DOWNTO 0) - data_reg_hold_old(23 DOWNTO 0));
-data_reg_hold_new_temp
<= data_reg_hold_old;
DATA_REG_HOLD
<= DATA_REG_HOLD_OLD(23
DOWNTO 0);
-data_reg_hold
<= data_reg_hold_temp(47
downto 24) + data_reg_hold_new_temp(23 downto 0);
elsif( data_reg_scaler = X"001156EB" ) then -- 1
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"002FAF08" ) then -- 2
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"003404C1" ) then -- 3
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00455BAC" ) then -- 4
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"0056B297" ) then -- 5
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00680982" ) then -- 6
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"0079606D" ) then -- 7
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"008AB758" ) then -- 8
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"009C0E43" ) then -- 9
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00AD652E" ) then -- 10
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00BEBC19" ) then -- 11
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00D01304" ) then -- 12
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
19
elsif( data_reg_scaler = X"00E169EF" ) then -- 13
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"00F2C0DA" ) then -- 14
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
elsif( data_reg_scaler = X"010417C5" ) then -- 15
DATA_REG_HOLD
<= DATA_REG_HOLD +
DATA_REG_HOLD_TEMP(23 DOWNTO 4);
end if;
if( data_reg_scaler = X"017D7840" ) then
data_reg_scaler
<= X"00000000";
data_reg_hold_new
<= data_reg_hold_temp2;
data_reg_hold_old
<= data_reg_hold_new;
else
data_reg_scaler
<= data_reg_scaler + 1;
end if;
if caliperclk_deb = X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" then
caliperclk_debounced <= '1';
elsif caliperclk_deb = X"0000000000000000" then
caliperclk_debounced <= '0';
else
caliperclk_debounced <= caliperclk_debounced;
end if;
if caliperclk_debounced /= caliperclk_old and caliperclk_debounced = '1'
then
--
data_reg_hold(15 downto 0) <= data_reg_hold(15 downto 0) + 1;
data_reg(data_reg_pointer) <= caliperdata;
if data_reg_pointer >= 48 then
data_reg_hold_temp2(23 downto 0) <= not data_reg(48 downto
25);
--
data_reg_hold(15 downto 0) <= not data_reg_hold(15 downto
0);
data_reg_pointer <= 0;
else
data_reg_pointer <= data_reg_pointer + 1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
20
Figure 8: slidewhistle.ucf
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "atod<0>" LOC = "P102" | IOSTANDARD = LVTTL ;
NET "atod<1>" LOC = "P110" | IOSTANDARD = LVTTL ;
NET "atod<2>" LOC = "P112" | IOSTANDARD = LVTTL ;
NET "atod<3>" LOC = "P113" | IOSTANDARD = LVTTL ;
NET "atod<4>" LOC = "P115" | IOSTANDARD = LVTTL ;
NET "atod<5>" LOC = "P120" | IOSTANDARD = LVTTL ;
NET "atod<6>" LOC = "P122" | IOSTANDARD = LVTTL ;
NET "atod<7>" LOC = "P126" | IOSTANDARD = LVTTL ;
NET "brdled" LOC = "P71" ;
NET "caliper<0>" LOC = "P101" | IOSTANDARD = LVTTL ;
NET "caliper<1>" LOC = "P99" | IOSTANDARD = LVTTL ;
NET "clk" LOC = "P80" ;
NET "led<0>" LOC = "P73" | IOSTANDARD = LVTTL ;
NET "led<1>" LOC = "P75" | IOSTANDARD = LVTTL ;
NET "led<2>" LOC = "P82" | IOSTANDARD = LVTTL ;
NET "led<3>" LOC = "P86" | IOSTANDARD = LVTTL ;
NET "led<4>" LOC = "P87" | IOSTANDARD = LVTTL ;
NET "led<5>" LOC = "P89" | IOSTANDARD = LVTTL ;
NET "led<6>" LOC = "P94" | IOSTANDARD = LVTTL ;
NET "led<7>" LOC = "P96" | IOSTANDARD = LVTTL ;
NET "midi" LOC = "P74" | IOSTANDARD = LVTTL ;
NET "rst" LOC = "P77" ;
#PACE: Start of PACE Area Constraints
#PACE:
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
Start of
PROHIBIT
PROHIBIT
PROHIBIT
PROHIBIT
PROHIBIT
PROHIBIT
PROHIBIT
PROHIBIT
PACE Prohibit Constraints
= P125;
= P114;
= P111;
= P109;
= P84;
= P95;
= P98;
= P100;
#PACE: End of Constraints generated by PACE
21