University Question

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UNIT-I
BASIC STRUCTURE OF COMPUTERS
PART-A
1. Why data bus is bidirectional and address bus is unidirectional in most
microprocessors?
(MAY/JUNE 2007)
2. What is a bus? What are the different buses in a CPU?
( NOV/DEC 2006)
3. What are tri-state gate?
(APRIL/MAY 2008)
4. List out the 4 types of operation that an instruction must do.
( NOV/DEC 2006)
5. Define Superscalar execution.
( NOV/DEC 2006)
6. What do you understand by hit-ratio?
( NOV/DEC 2006)
7. Define 3-address instruction with an example.
(MAY/JUNE 2006)
8. Define 2-address instruction with an example.
(MAY/JUNE 2006)
9. Define 1-address instruction with an example.
(MAY/JUNE 2006)
10. Define 0-address instruction with an example.
(MAY/JUNE 2006)
11. What is the information conveyed by addressing modes?
(NOV/DEC 2007)
12. Which data structures can be supported using (a). Indirect addressing mode
(b). Indexed addressing mode?
13. Define locality of reference? What are its types?
(MAY/JUNE 2006)
( NOV/DEC 2006)
14. Define Spatial expansion.
(APRIL/MAY 2008)
15. Define Temporal expansion.
(APRIL/MAY 2008)
16. Draw the full adder circuit using two half adders?
(NOV/DEC 2007)
17. What are the various ways of representing signed integers in the system?
(NOV/DEC 2007)
18. Define underflow and overflow.
(APRIL/MAY 2008)
19. What is the purpose of guard bits used in floating point operations?
(MAY/JUNE 2006)
20. Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What
is the effective address of the memory operand in each of the following instructions?
(a) Load 20(R1), R5
(b) Add - (R2), R5
(APRIL/MAY 2008)
21. What is the use of condition code register?
(APRIL/MAY 2008)
22. What do you mean by End—around carry correction?
(APRIL/MAY 2008)
PART-B
1. Draw the single bus and three bus organization of the data path inside a processor.
(NOV/DEC 2007)
2. What do you know about bit, bytes, nibbles and word? What are big-endian and littleendian assignments of addresses?
3. Write notes on Instruction formats.
(NOV/DEC 2007)
(NOV/DEC 2007) & ( NOV/DEC 2006)
4. Explain about Instruction & Instruction Sequencing?
( NOV/DEC 2006)
5. (a) Explain in detail the different Instruction types and Instruction Sequencing.
Or
(b) Explain the different types of Addressing modes with suitable examples.
(APRIL/MAY 2008)
6. (a) Illustrate Booth Algorithm with an example.
Or
(b) Design a 4-bit Carry-Look ahead Adder and explain its operation with an example.
(APRIL/MAY 2008) & (NOV/DEC 2007)
7. Explain various instruction formats in detail.
(APRIL/MAY 2008) & (MAY/JUNE 2006)
8. Explain the instruction cycle highlighting the sub-cycles and sequence of steps to be
followed.
(NOV/DEC 2007)
9. Explain about Addressing modes?
(NOV/DEC 2007) & ( NOV/DEC 2006) & (MAY/JUNE 2007)
10. Registers R1 and R2 of a computer contains the decimal values 1200 and 2400
respectively. What is the effective address of the memory operand in each of the
following instructions?
i.
Load 20(R1), R5
ii.
Add –(R2) , R5
iii.
Move #3000, R5
iv.
Sub (R1)+, R5
(MAY/JUNE 2006)
10. Explain how the processor is interfaced with the memory with a neat block
diagram and explain how they communicate.
(NOV/DEC 2007)
11. What are the disadvantages in using a ripple carry adder? ( NOV/DEC 2006)
12. Design a binary multiplier using sequential adder. Explain its operation.
(NOV/DEC 2007)
13. Draw the diagram of a carry look a head adder and explain the carry look ahead
principle.
( NOV/DEC 2006)
14. Design a 4-bit binary adder/ subtractor and explain its functions.
(APRIL/MAY 2008)
15. Give the algorithm for multiplication of signed 2’s complement numbers and
illustrate with an example.
(APRIL/MAY 2008)
16. Design an array multiplier that multiplies two 4-bit numbers and explain its
operation.
(APRIL/MAY 2008)
17. Write the algorithm for division of floating point numbers and illustrate with an
example.
(APRIL/MAY 2008)
18. Write about the CSA method of fast multiplication. Prove how it is faster with an
example.
(NOV/DEC 2007) & (MAY/JUNE 2006)
19. Draw the circuit for integer division and explain.
(NOV/DEC 2007)
20. Explain the working of a floating point adder/ subtractor. With a detailed flow
chart explain how floating point additional/ subtraction is performed.
(MAY/JUNE 2006) & ( NOV/DEC 2006)
21. Give the IEEE standard double precision floating point format.
( NOV/DEC 2006)
22.Explain the representation of floating point numbers in detail. (MAY/JUNE 2007)
UNIT –II
BASIC PROCESSING UNIT
PART-A
1. What factors influences the bus design decisions?
(APRIL/MAY 2008)
2. What are the advantages and disadvantages of hard wired and micro programmed
control?
(NOV/DEC 2007)
3. Write the sequence of control steps required for three bus structure for the
following instruction: Add R4, R5 and R6.
(APRIL/MAY 2008)
4. Define Bus Arbitration.
(APRIL/MAY 2008)
5. Why is the Wait—for—Memory-Function-Completed step needed when reading
from or writing to the main memory?
(APRIL/MAY 2008)
6. State the difference between hardwired control and micro programmed control
unit.
(MAY/JUNE 2007)
PART-B
1. Give the sequence of control signals to be generated to fetch an instruction from
memory in a single-bus organization.
2. Explain about multiple-bus organization in detail.
(MAY/JUNE 2006)
(MAY/JUNE 2007)
3. Explain various design methods of Hardwired control in detail.( NOV/DEC 2006)
4. Explain the organization of Micro programmed control unit in detail.
(NOV/DEC 2007) & (MAY/JUNE 2006) & ( NOV/DEC 2006)
5. List the differences between hardwired control and micro programmed control?
(APRIL/MAY 2008)
6. With a suitable diagram describe the sequence of micro operations involved in
fetching and executing a typical instruction.
(APRIL/MAY 2008)
7. Explain Microprogrammed Control Unit. What are the advantages and
disadvantages of it?
(APRIL/MAY 2008)
UNIT-III
PIPELINING
PART-A
1) What is pipelining and what are the advantages of pipelining?
(APRIL/MAY 2008)
2) What is pipeline speedup?
( MAY/JUNE 2007)
3) What is data hazard in pipelining? What are the solutions?(NOV/DEC 2007)
4) How do control instructions like branch, cause problems in a pipelined processor?
(MAY/JUNE 2006)
5)
Define Locality of Reference.
(APRIL/ MAY 2008)
PART-B
1. Design a 4-stage instruction pipeline and show how its performance is improved
over sequential execution.
(NOV/DEC 2007) & ( NOV/DEC 2006)
2. Explain the function of a six segment pipelines and draw a space diagram for a six
segment pipeline showing the time it takes to process eight tasks.
(MAY/JUNE 2007)
3. Explain the performance of the instruction pipeline can be improved.
(MAY/JUNE 2007)
4. Explain about Data Hazards with its representation.
(APRIL/MAY 2008)
5. Explain the execution of an instruction with diagram.
(MAY/JUNE 2007)
6. Highlight the solutions of instruction Hazards.
(NOV/DEC 2007)
7. What are branch hazards? Describe the methods for dealing with the branch
hazards.
(APRIL/MAY 2008)
8. Explain how pipelining helps to speed-up the processor. Discuss the hazards that
have to be taken care of in a pipelined processor.
(MAY/JUNE 2006)
UNIT-IV
MEMORY SYSTEM
PART-A
1. Give the features of a ROM cell
(APRIL/MAY 2008)
2. An eight-way-associative cache consists of a total of 256 blocks. The main
memory contains 8192 blocks, each consisting of 128 words.
a. How many bits are there in the memory address?
b. How many bits are there in the TAG, SET and WORD fields?
(MAY/JUNE 2006)
3. List the differences between static RAM and dynamic RAM.
(APRIL/MAY 2008)
4. How many 128** Ram chips are needed to provide a memory capacity of 2048
bytes?
(MAY/JUNE 2007)
5. What is Translation Look aside Buffer?
(MAY/JUNE 2006)
PART-B
1. Describe the organization of a typical RAM chip.
(MAY/JUNE 2007)
2. Explain about Static & Dynamic memory systems. (NOV/DEC 2007)
3. Write note on:
i.
ROM technologies.
ii.
Memory Interleaving
iii.
Set associative mapping of cache.
iv.
RAID Disk arrays.
(NOV/DEC 2007)
4. Explain about Cache memory in detail.
( NOV/DEC 2006)
5. What is mapping? Explain its types in detail.
(MAY/JUNE 2006)
6. Explain various mechanisms of mapping main memory address into cache
memory addresses.
(APRIL/MAY 2008)
7. A digital computer has a memory unit 64 K * 16 and cache memory of 1K words.
Caching uses directed mapping with a block size of 4 words. How many bits are
there in the TAG, index, block and word filed of the address format? How many
blocks can the cache accumulate.
8. Explain the performance factors in memory.
(MAY/JUNE 2007)
(MAY/JUNE 2006)
9. A byte- addressable computer has a small data cache capable of holding eight 32bit words. Each cache block contains one 32-bit word. When a given program is
executed, the processor reads data from the following sequence of Hex addresses.
200, 204, 208, 20C, 2F4, 2F0, 200, 204, 218, 21C, 24C, 2F4. The pattern is
repeated 4 times. Assuming that the cache is initially empty, show the content of
the cache at the end of each pass. And compute the hit-rate for a direct mapped
cache.
(MAY/JUNE 2006)
10. Explain the concept of memory hierarchy.(NOV/DEC 2007)&( NOV/DEC 2006)
11. Explain how the virtual address is converted into real address in a paged virtual
memory system.
(APRIL/MAY 2008)
12. Discuss the address translation mechanism and the different page replacement
policies used in a virtual memory system.
(MAY/JUNE 2006)
13. Describe the functional characteristics that are common to the devices used to
build main and secondary computer memories.
(APRIL/MAY 2008)
14. Describe the working principle of a typical magnetic disk. (APRIL/MAY 2008)
15. Discuss the concept of memory interleaving and give its advantages.
( NOV/DEC 2006)
16. Define Cache Mapping Functions. Explain the methods.
17. How a virtual address gets translated into a physical address? Explain in detail
with a neat diagram. Explain the use of TLB.
(APRIL/MAY 2008) & ( NOV/DEC 2006) & (MAY/JUNE 2007)
18. What is virtual memory? How is it implemented? (NOV/DEC 2007)
UNIT-V
I/O ORGANIZATION
PART-A
1. What is a bus? What are the different buses in a CPU? ( NOV/DEC 2006)
2. Why are interrupt masks provided in any processor?
(MAY/JUNE 2006)
3. What is priority interrupt?
(APRIL/MAY 2008)
4. What are advantages of using interrupt initiated data transfer over transfer under
program control without interrupt?
(MAY/JUNE 2007)
5. What is the difference between subroutine and interrupt services routine?
(NOV/DEC 2007)
6. What is Direct Memory Access (DMA)? And state its advantages.
( NOV/DEC 2006)
7. What will be the width of address and data buses for a 512K * 8 memory chip?
(NOV/DEC 2007)
8. Why do we need DMA?
(NOV/DEC 2007)
9. Why does DMA have priority over the CPU when both request a memory
transfer?
(MAY/JUNE 2007)
10. How does bus arbitration typically work?
(MAY/JUNE 2006)
11. What is the necessity of an interface?
(NOV/DEC 2006)
12. List the factor that determines the storage device performances.
(MAY/JUNE 2007)
PART-B
1. Design parallel priority interrupt hardware for a system with eight interrupt
source.
(MAY/JUNE 2007)
2. Explain how DMA transfer is accomplished with a neat diagram.
( NOV/DEC 2006)
3. Draw the typical block diagram of a DMA controller and explain how it is used
for direct data transfer between memory and peripherals.
(APRIL/MAY 2008) & (MAY/JUNE 2007)
4. Explain how data may be transferred from a hard disk to memory using DMA
including arbitration for the bus,. Assume a synchronous bus, and draw a timing
diagram showing the data transfer.
(MAY/JUNE 2006)
5. Explain the use of vectored interrupts in processors. Why is priority handling
desired in interrupt controllers? How do the different priority schemes work?
(MAY/JUNE 2006)
6. Write short notes on:
a. DMA.
b. Bus Arbitration
c. Printer-processor Communication.
d. USB.
(NOV/DEC 2007)
7. Discuss the data transfer mechanism of the PCI bus. (MAY/JUNE 2006)
8. Explain the organization of a magnetic disk in detail. (MAY/JUNE 2007)
9. How do you connect multiple I/O devices to a processor using interrupts? Explain
with suitable diagrams.
(NOV/DEC 2007)
10. (i)Explain the use of DMA Controllers in a computer system with a neat diagram.
(ii)Explain Handshake protocol. Depict clearly how it controls data transfer
during an input operation.
(APRIL/MAY 2008)
11. Describe the working principles of USB.
(APRIL/MAY 2008)&(MAY/JUNE 2006)
12. Briefly compare the characteristics of SCSI with PCI.
(APRIL/MAY 2008) & ( NOV/DEC 2006) & (MAY/JUNE 2007)
13. Describe the functions of SCSI with a meat diagram. (MAY/JUNE 2007)
14. Explain the advantages of USR over older I/O bus architecture.
( NOV/DEC 2006)
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