Tutorial notes
Yuan Zhang
Simulation Tool – Hspice
To start
Login in one of the following workstations:
eesu1 - eesu10 (Ultra 10 workstations) , eesu27 – eesu34.ece.ust.hk (Blade 1500 workstations)
1. open Secure shell Client.
2. Modify .cshrc_user file in your home directory using pico or vi editor.
######################################################
#
File : .cshrc.user
######################################################
source /usr/eelocal/meta/2002.2/.cshrc
source /usr/eelocal/synopsys/sx/.cshrc
The first and second lines are for sourcing hspice and waveview analyzer respectively.
3. Type source .cshrc_user to apply the changes or you have to logout and re-login again to valid
the above setup.
4. Start X-win. Find the ip address of your computer.
5. Under the Unix shell, set the DISPLAY environment variable.
eesuxx:xxxx:1>setenv DISPLAY 143.89.68.76:0.0
change the ip address accordingly.
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Tutorial notes
Yuan Zhang
Hspice Simulator
1. Netlist File
a. Model file.
Download one model file from
http://www.mosis.org/Technical/Testdata/menu-testdata.html.
Open the model file and search for the line:
*DATE: XX XX/XX
Remove anything above this line and then save the file with the file extension of ‘.mod’,
e.g. cmos018.mod
* DATE: Oct 15/07
* LOT: T77A
WAF: 2007
* Temperature_parameters=Default
.MODEL CMOSN NMOS (
LEVEL = 49
+VERSION = 3.1
TNOM
= 27
TOX
= 4.1E-9
+XJ
= 1E-7
NCH
= 2.3549E17
VTH0
= 0.3698438
+K1
= 0.5791729
K2
= 2.347381E-3
K3
= 1E-3
+DVT0W = 0
DVT1W = 0
DVT2W = 0
b. Write an Input netlist file based on your schematic. The statements in Hspice are case
insensitive. Here is an example.
Vdd
M3
M4
out
3
Vin+
VS
0
Vin+
Vin-
M1
M2
Vin-
Vdd
+ E1 E2 +
-
VS
0
Ibias
AC
2
1
Vs
DC
Vcm
M5
M6
***********Title***********
* Elec 504 (Fall 2008) Example
* Differential pair with active load
***** Initialization *****
.options post probe acout=0
.include 'cmos018.mod'
$ include the model file
The model file name must be the
same as that of the model file that
you want to use.
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***** Circuit description *****
vdd vdd 0 1.8
Ibias vdd 1 200u
as=ad=W x Ls are the drain and
source areas.
ps=pd=2*W + 2*Ls are the drain
and source perimeters
m1 3 vin+ 2 0 cmosn w=w1
l=l1
+ as='w1*ls' ad='w1*ls' ps='2*w1+2*ls' pd='2*w1+2*ls'
m2 out vin- 2 0 cmosn w=w2
l=l2
+ as='w2*ls' ad='w2*ls' ps='2*w2+2*ls' pd='2*w2+2*ls'
m3 3 3 vdd vdd cmosp w=w3
l=l3
+ as='w3*ls' ad='w3*ls' ps='2*w3+2*ls' pd='2*w3+2*ls'
m4 out 3 vdd vdd cmosp w=w4
l=l4
+ as='w4*ls' ad='w4*ls' ps='2*w4+2*ls' pd='2*w4+2*ls'
m5 1 1 0 0 cmosn w=w5
l=l5
+ as='w5*ls' ad='w5*ls' ps='2*w5+2*ls' pd='2*w5+2*ls'
m6 2 1 0 0 cmosn w=w6
l=l6
+ as='w6*ls' ad='w6*ls' ps='2*w6+2*ls' pd='2*w6+2*ls'
cl
out 0
1p
e+
evcm
vs
vin+ 102
vin- 102
102 0
100 0
100 0 0.5
100 0 -0.5
dc=0.9
dc=0 ac=1
For 0.18um
Ls=0.48um.
For 0.13um
Ls=0.55um
CMOS
process,
CMOS
process,
L
Ls
W
***** Parameter definition *****
.para
w1=2.6u l1=0.18u w2=2.6u l2=0.18u
.para
w3=12.8u l3=0.18u w4=12.8u l4=0.18u
.para
w5=5.2u l5=0.18u w6=5.2u l6=0.18u
.para
ls=0.48u
***** Analysis *****
* Operation point
.op
* DC analysis
.dc vs -1
1 0.01
.probe dc v(out)
* AC analysis
.ac dec 100 10k 1g
.probe ac vdb(out) vp(out)
* Transfer function analysis
.tf v(out)
vs
* Pole zero analysis
.pz v(out)
vs
.end
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Tutorial notes
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2. Start simulation.
a. Put the model file and the netlist file in the same directory. After putting the model file
in the directory, remember to check whether the model file ends with the extension of
‘.mod’. If not, rename it with the extension of ‘.mod’. Run Hspice using your netlist file as
the input and redirect Hspice’s output to an output file.
eesuxx:xxxx:> hspice example.sp >example.lis
Simulation is done when you see the following information. Correct your netlist if there are
errors.
>info:
real
user
sys
***** hspice job concluded
0.7
0.3
0.0
b. Check the output file for simulation results.
****
operation point
subckt
element 0:m1
0:m2
0:m3
0:m4
0:m5
0:m6
model
0:cmosn
0:cmosn
0:cmosp
0:cmosp
0:cmosn
0:cmosn
region
Saturati Saturati Saturati Saturati Saturati Saturati
id
79.4043u 79.4043u -79.4043u -79.4043u 200.0000u 158.8086u…
…
****
small-signal transfer characteristics
v(out)/vs
input resistance at
output resistance at v(out)
******
vs
= 21.9514
= 1.000e+20
= 27.3874k
pole/zero analysis
poles (rad/sec)
poles ( hertz)
**********************************************************************
real
imag
real
imag
-35.3479x
0.
-5.6258x
0.
-16.0150g
0.
-2.5489g
0.
-55.8418g
0.
-8.8875g
0.
-150.0923g
0.
-23.8879g
0.
zeros (rad/sec)
zeros ( hertz)
**********************************************************************
real
imag
real
imag
-39.8618g
0.
-6.3442g
0.
-56.3093g
0.
-8.9619g
0.
-150.4046g
0.
-23.9376g
0.
257.5914g
0.
40.9970g
0.
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Tutorial notes
Yuan Zhang
3. Use WaveView Analyzer to plot the simulation results.
Type
eesuxx:xxxx:>sx –w
or
eesuxx:xxxx:>wv
to run WaveView Analyzer
Click the menu File→Import Waveform File to import the waveform files. Multiple files can be
imported simultaneously by pressing the ‘Ctrl’ button while clicking the files to be imported. In
the example below, the ‘example.ac0’ and ‘example.sw0’ are the ac and dc sweep waveform files
respectively.
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Tutorial notes
Yuan Zhang
After the waveform files are imported, the windows will become:
The waveforms can be loaded in two ways.
The first method is to use the mouse to drag the ‘toplevel’ highlighted below from the Output
View and then drop it to the waveview window on the right. With this method, all the signals
(vdb(out) and vp(out)) within this hierarchy level are loaded to the same graph together.
The second method is to double-click on the signal (e.g. vdb(out)) to display it in an individual
graph in the waveview.
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Tutorial notes
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Double-click on another signal (e.g. vp(out)) to display it in another graph in the waveview.
Change the X axis to logarithmic scale if necessary by clicking the menu Axes→X-Axis Type→
Log10. The graphs will now become:
To add a new waveview, click the menu WaveView→New. A new waveview tab called waveview2
is now shown next to waveview1. By clicking the corresponding tab, you can switch to the
waveview that you want to display.
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Tutorial notes
Yuan Zhang
Then, other waveforms can be displayed in this new waveview by the above two methods.
Click on the ‘add cursor’ button at the left 4th position of the bar on top of the waveview to get
the coordinate data of any point you’re interested in. For example, you can get the DC gain, unit
gain frequency, phase margin etc. on the plot.
4. Iterate if the simulation results don’t meet the specifications.
Hspice manual: /usr/eelocal/meta/doc2003.12/hspice_sim_analysis.pdf
Spice Explorer and WaveView Analyzer manual:
/usr/eelocal/synopsys/sx-vc2009.03/c2009.03/sx_c2009_03/doc/manuals/swxv_user.pdf
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Tutorial notes
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Hspice Examples in Homework
Device Characteristics
Use the model file
Before start simulations, please look into the model file. There, you may find a lot of information
about the process you’re using. Here lists some important parameters.
MOSFET model: BSIM3 level 49
Name
TOX
VTH0
NSUB
K1
U0
UA
Unit
m
V
cm-3
V1/2
cm2/V/sec
m/V
Description
Gate Oxide thickness
Threshold voltage of the long channel device @Vbs=0 and small Vds
Substrate doping concentration
First-order body effect coefficient
Low field mobility at T=TREF=TNOM
First-order mobility degradation coefficient
You can find more detailed descriptions of the model on BSIM3’s homepage at
http://www-device.eecs.berkeley.edu/~bsim3/
Some useful quantities:
Symbol
ε0
εox
εsi
Description
Permittivity of free space
Permittivity of oxide
Permittivity of silicon
Value
8.854×10-12 F/m
3.9ε0
11.9ε0
Some useful equations:
C ox 
 ox
t ox
,
2q si N sub

Cox
Hspice simulations
To test the device, build a Hspice circuit shown below.
D
G
VGS
B
S
VBS
VDS
Chose W/L = 9 μ/0.18 μ for the transistor. In Hspice netlist file, there should be something like
vds
vgs
vbs
m1
d
g
b
d
0
0
0
g
0.5
0.52
0
0 b
cmosn
w=9u
l=0.18u
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Tutorial notes
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To get the threshold voltage, you need to fix VBS, VDS, then do a DC analysis on VGS.
.op
.dc vgs 0
1.8
.probe i(m1)
0.01
Using WaveView Analyzer, you can plot the curve of ID vs. VGS.
From the plot, you can estimate VT, μCox etc. Check the output file for more detailed information.
To simulate the channel modulation effect, fix VGS and VBS, do a DC analysis on VDS. You would get
a plot like the following one. λ can be calculated from the plot.
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Tutorial notes
Yuan Zhang
To obtain the IV characteristic curve,
.op
.dc vds 0
1.8
.probe i(m1)
0.01 vgs
0
0.8
0.01
Use .op statements to get operation point information of your circuit. In the output file you can
find gm , Cgs,Cgd etc. fT can be calculated then.
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Tutorial notes
Yuan Zhang
Two Stage OPAMP Design
Design
1.8V
To design a CMOS amplifier, the first thing you should do is deriving all the equations you need.
For a classic two stage OPAMP shown above, here list some design equations
For example:
 The compensation capacitor and the load capacitor are equal, i.e. CC=CL.
 Typically, the input devices should be biased such that
VDS,sat=VGS - VT=0.2V
 The second stage is biased at higher current that the input stage.
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Tutorial notes
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From the equations and specifications, we can now derive the all the parameters we need.
After some mathematic, we may get the requirements or values for some parameters. For
example,
gm1≥754 μA/V
gm5≥1.508 mA/V
Choose one process. Using the data you got from single transistor simulation, you can get W/L12.
And finally you can determine the aspect ratios of all MOSFETs.
Simulation Using Hspice
To simulate the gain, unit gain frequency, phase margin, CMRR, you need to add some input
sources to your netlist.
e+
evcm
vs
vin+ 102
vin- 102
102 0
100 0
100 0 0.5
100 0 -0.5
dc=0.9
dc=0 ac=1
* AC analysis
.ac dec 100 10k 1g
.probe ac vdb(out) vp(out)
Run an AC analysis on Vs, you’ll get a small signal response plot.
On that plot, it’s rather straightforward to get low-frequency gain, unit gain frequency, phase
margin etc.
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Tutorial notes
Yuan Zhang
To simulate CMRR, you need to change the AC source in your circuit. Put the following statements
just before the .end statement. Now the AC source is applied as a common mode signal.
.alter
vcm
vs
.end
102
100
0
0
dc=0.9
dc=0
ac=1
ac=0
After simulation, you get two curves, the differential mode gain and the common mode gain.
Then PSRR=(Adm-Acm) dB.
To simulate Slew Rate, configure your amplifier as a unity gain buffer and apply a square wave as
input. Both positive and negative Slew Rate can be obtained from slope of the output.
Vout
Vin+
CL
* Slew rate analysis
vpulse vin+ 0 pwl(0 0.5 1n 1 500n 1 500.1n 0.5)
.trans
0.1n 1u
.probe v(out)
v(vin+)
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Tutorial notes
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Slope=negative
slew rate
Slope=positive
slew rate
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Tutorial notes
Yuan Zhang
Summary of Useful Commands (Hspice)
1. Devices
BJT
Qxxx nc nb ne <ns> model_name <area_value>
MOS
Mxxx nd ng ns <nb> model_name <W=?> <L=?> <AD=?>
+<AS=?> <PD=?> <PS=?>
Resistor
Rxxx n1 n2 <model_name> resistance
Capacitor
Cxxx n1 n2 <model_name> capacitance
Inductor
Lxxx n1 n2 <model_name> inductance
2. Independent Sources
Voltage
source:
Current
sources:
Vxxx n+ n- <<DC=> dcval> <tranfun>
+<AC=acmag,<acphase>>
Iyyy n+ n- <<DC=> dcval> <tranfun>
+<AC=acmag,<acphase>>
Note: Independent sources can have ac and dc components simultaneously.
3. Transient Functions
Pulse
pulse(v1 v2 td tr tf pw per)
Sin
sin(vo va freq td θ φ)
Exp
exp(v1 v2 td1 τ1 td2 τ2 …)
Piecewise
linear
pwl(t1 v1 t2 v2 t3 v3 …)
4. Dependent Sources
VCCS
Gxxx n+ n- in+ in- transconductance
CCCS
Fxxx n+ n- vn1 gain
VCVS
Exxx n+ n- in+ in- gain
CCVS
Hxxx n+ n- vn1 transresistance
5. Analysis
Operating Point
Calculation
.op
Transient
.tran voltage/current_source <start=>start_time
<stop=>stop_time <step=>step_time
DC analysis
.dc voltage/current_source <start=>start_value
<stop=>stop_value <step=>step_value
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Tutorial notes
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Transfer function
analysis
.tf output_variable input_source
AC analysis
.ac <<type=>decade/linear> no_of_pt_per_decade
start_freq stop_freq
Notes:
a. .dc is used to compute the operating points of a circuit when the DC value(s) of the
voltage/current source(s) is swept. This helps to eliminate the tedious work of changing the DC
value(s) of the voltage/current source(s) and reading the operating points manually.
b. .tf is the small-signal DC small-signal transfer function analysis. Small-signal gain, input
and output resistance can be obtained in the output file by using this analysis.
6. Output
.probe <type=ac/dc/tran> output(s)…
Note: The number of outputs can be more than one.
Format of Outputs
Voltage of a node
vx(Node_name)
Differential voltage
v(n1,n2)
Current of a component
ix(comp_name)
Drain current of MOS
i(Mxxx)
For more information, please refer to the hspice and awaves manual
Hspice manual: /usr/eelocal/meta/doc2003.12 /hspice_sim_analysis.pdf
Spice Explorer and WaveView Analyzer manual:
/usr/eelocal/synopsys/sx-vc2009.03/c2009.03/sx_c2009_03/doc/manuals/swxv_user.pdf
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