The 2005 International Workshop on
System-on-Chip
July 20 - July 24, 2005
Banff, Alberta - Canada
Call For Papers
In Cooperation with
IEEE Circuits and Systems
Society's Technical
Committee on VLSI
The objective of this workshop is to provide a forum for discussion of new developments, recent
progress, and innovations in the design and implementation of System on Chip. It addresses all
aspects of design and design methods of those systems. Emphasis is on current and future challenges
in research and development in both academia and industry. A proceeding of the workshop will be
published. Original and unpublished papers are solicited in the following areas, but not limited to:
and
IEEE Circuits and Systems
Society's Technical
Committee on
Communication
Technical Co-sponsor
The IEEE CAS
Conference General Chair
Graham Jullien
Dept. of ECE
University of Calgary
1. IP Core, Circuit and System Designs
1.1. Analog and Mixed-Signal IC Design
1.2. Digital IC Design
1.3. Digital Signal Processing and Image
Processing IC Design
1.4. Telecommunication Circuits and Applications
1.5. Special Architectures
1.6. Hardware Reconfiguration (FPGA-based
circuits, systems & applications)
1.7. Micromechanical Systems
1.8. Systems On Chip (embedded systems, IPs,)
2. CAD & CAT Methods and Tools
2.1. Modeling and Simulation
2.2. Deep Submicron Design & Modeling Issues
2.3. Verification
Technical Co-chairs
Wael Badawy
Dept. of ECE
University of Calgary
badawy@enel.ucalgary.ca
2.4. Low-Power Issues
2.5. Logic and High-level Synthesis
2.6. Prototyping and Validation
2.7. Testability and Test
3. Applications:
3.1 Speech/Music/Audio
3.2 Image and Machine Vision
3.3 Video/HDTV
3.4 Sonar and Radar
3.5 Networking/Communications
3.6 Coding/Compression
3.7 Wireless
3.8 Multimedia
3.9 Sensors
3.10 Medical
Special Sessions: Panels, embedded tutorials and hot-topic sessions will discuss new trends, can be
visionary and/or controversial. A one-page abstract must be submitted.
SOC Paper Student Contest: The best student paper will receive a special award.
SOC vs. SIP Panel: System on Chip or System in Package?
Kris Iniewski
ECE Department
University of Alberta
iniewski@ece.ualberta.ca
Important Dates
Tutorial/Special sessions
proposals
January 31, 2005
Paper Submission
February 1, 2005
Notification of Acceptance
March 15, 2005
Camera-Ready Paper
Analog Synthesis Panel: Is analog synthesis going to replace analog and RF designers?
SOC Test Panel: We can design SOC but how are we going to test it?
Start-up Panel: Is this still worthy to start your own company?
The Banff Forum on Circuits and Systems
The Banff forum on Circuits and Systems will be held in conjunction with the IWSOC2005. The
forum addresses the state of the arts development in the area of circuits and systems.
Paper Submission: Visit the conference website for information on submission www.socrt.org
Social Activates: In addition to the technical program, a very entertaining social program is planned. It will
introduce the conference attendees and their guests to Banff's
outdoor show on earth' with millions of visitors from around the
city of Calgary is transformed for ten days into a western town
enjoy the atmosphere and friendly, relaxed attitude of
www.worldweb.com/parkscanada-banff
most popular tourist attraction, 'the greatest
world each year: The Calgary Stampede. The
celebrating the cowboy culture. Visitors will
the locals. For more information, visit
April 15, 2005
More Information
http://www.socrt.org
Banff is the town in the heart of Banff National Park in Alberta's Rocky Mountains. The picturesque mountain
town is located 1½ hours from Calgary and just a short distance from the mountain areas of Lake Louise and
Kananaskis Country. Banff has something for everyone, from luxury escorted motor coach tours to adventure
tours featuring skiing, snowboarding, rock climbing, white-water rafting - the list is endless.
Invited Papers (see bios below):
Artur Balasinski, Cypress Semiconductor, “DFM for SOC”
John Long, Delft University, “Technologies for Wearable Communicators”
Johan van der Tang, ItoM Inc./Eindhoven University of Technology, "HW/SW co-design for SoC on
mobile platforms"
Christian Cojocaru, Skyworks Systems, “Low Power Bluetooth”
Sreedhar Natarajan, Emerging Memories Technology, “Semiconductor memories for future SOC”
Bozena Kaminska, SFU, "Wireless biomedical sensors and networks"
Sorin Voinigescu, University of Toronto, "Si-based SOC Design Beyond 50-GHz"
James Kuo, SFU/NTU, “Low-Voltage Bootstrapping Techniques for CMOS VLSI Digital Circuits and
Systems”
Paul Hasler, “Programmable and Reconfigurable Analog Signal Processing in a Digital World”
Ramesh Senthinathan, ATI Technologies , “High-speed links for SOCs used in hand held, TV and other
consumer devices”
Daniel Foty, Gilgamesh Associates, and Gennady Gildenblat, Pennsylvania State University,
“Fundamental Aspects of CMOS Technology: Basics, Implications, and a Roadmap to the Future”
Vladimir Stojanovic, MIT, “A view on the current and future design of high-speed links”
Mohab Anis, University of Waterloo, "Leakage Power: The Biggest Stumbling Block to Moore's Law Challenges and Solutions"
Sudha Sudharshanan, Queens University, “Architecture and design automation tools for application
specific SoCs”
Stephen Bates, Kris Iniewski, University of Alberta, "10 Gb/s over Copper Wires and Backplanes"
Tutorials (see bios in a separate file):
Tutorial #1:
Marek Mierzwinski, Tiburon Design Automation, Santa Rosa, CA, “An Introduction to Verilog-A for
Compact Device Models”
Tutorial #2:
Paul Hasler, Associate Professor, Georgia Institute of Technology , “Floating-Gate Devices, Circuits, and
Systems”
Tutorial #3:
Vladimir Stojanovic, MIT, “A systems approach to building modern high-speed links”
Tutorial #4:
Kris Iniewski, University of Alberta, and Calvin Plett, Carleton University, “Moderate Inversion:
Physics, Modeling and Circuits Implications”
“System on Chip (SOC) or System in Package (SIP)?”
Evening Panel Discussion #1:
System on Chip (SOC) has received intense attention in the last 5 years, but enthusiasm behind “let us integrate
everything” seem to be fading away due to inherent SOC complexities and prohibitive costs. System in package (SIP),
that existed years ago as Multi Chip Module (MCM) technology, has risen from the ashes to challenge SOC. Many SIP
issues remain: how to test for a good die?, how to interconnect various ICs?, how to partition the system? Top
international experts from industry and academia will debate this hot topic and try to address the integration issues.
"Is analog synthesis going to replace analog and RF designers?"
Evening Panel Discussion #2:
Historically digital synthesis relieved digital designers from designing their circuits at the transistor levels. Today, most
chip designers are fluent in VHDL/Verilog, but only marginally aware of silicon related issues. With recent progress in
analog synthesis a similar fate might hit analog designers. Is the history going to repeat itself? Top international experts
from industry and academia will debate this hot topic and try to address the chip design automation issues.
“We can design SOC but how are we going to test it?”
Evening Panel Discussion #3:
While SOC design is challenging many in the semiconductor industry think that SOC testing is even more challenging.
Some traditional approaches to silicon testing are facing big hurdles. Built-in Self Test (BIST) adds complexity and
silicon area. Iddq becomes problematic due to increased leakage currents. Tester costs are going through the roof. Top
international experts from industry and academia will debate this hot topic and address challenges of SOC testing.
“Is it worthy to start your own company?”
Evening Panel Discussion #4:
Starting your own company remains a dream for many engineers and entrepreneurs in North America. However,
increasing complexities and escalating chip design costs make it difficult to be successful. System on Chip (SOC)
industry offers opportunity in fabless and IP core design activities, but the number of companies that hit it big time is
limited to a few. Past, present and future CEOs will debate this interesting topic and address the business start-up issues.
Panels Organizer & Moderator: Kris Iniewski, Professor, University of Alberta, www.ece.ualberta.ca/~iniewski
Panel Participants & their positioning statements (see bios in a separate file):
Panel #1:
“System on Chip (SOC) or System in Package (SIP)?”
Paul Kempf
Chief Marketing and Technology Officer, Jazz Semiconductor, Newport Beach, CA
www.jazzsemi.com
The concept of system on a chip sounds exciting and represents an achievement, the ultimate goal of reducing multiple
components down to one. While this is a nice theory, it may not be the best solution. The idea that a system is optimized
by using the technology that achieves the best performance at the right price point may in fact be a two or even three chip
solution. The first step is a subsystem –on – a – chip, using the best-suited process technology for the analog/RF portion
and the best suited technology for the logic intensive digital portion of the chip.
Resve Saleh
Professor, University of British Columbia, Vancouver, BC
http://www.ece.ubc.ca/~res/
Many people feel that SoC is about integrating everything onto one chip. The concept of combining digital, memory,
mixed-signal, RF, etc. has been around since the mid-seventies. There is nothing new in that idea. However, the difficulty
of integrating heterogeneous circuit design styles and processes onto one substrate still remains. Therefore, SiP seems to
be the only viable solution at this point.
On the other hand, one should not confuse this with the concept of SoC. The SoC methodology was developed as a
response to the productivity gap, not the integration gap. It is based on the notion of reusable IP and its use in rapidly
constructing large complex designs. It extended the notion of reusability to the next level by defining application-specific
SoC Platforms that are a combination of a number of reusable IP blocks, standard buses, standard I/O and embedded
software, along with the CAD tools and flows to generate derivative designs. This is the essence of SoC, not the
integration of heterogeneous technologies on one chip (although it would be great if we could do both!).
In my opinion, SoC and SiP are complementary approaches addressing two different problems: one addresses
productivity of design engineers and the other addresses packaging of heterogenous design technologies. Yes, they do
overlap at times but they should really co-exist. An SoC will comprise one or more of the chips in the SiP. In fact, SoC
and SiP are synergistic in nature. Rather than arguing about which is better, why not leverage both capabilities to their
fullest extent!
David LeBlanc
VP Manufacturing, Potentia Semiconductor, Ottawa, ON
www.potentiasemi.com
Artur Balasinski
Principal Engineer, Cypress Semiconductor, San Jose, CA
www.cypress.com
I am willing to risk a bet that SOC is the ultimate solution. This is because of the natural engineering trend to integrate
manufacturing process, functionality, and applications. Likewise, I can risk a bet that, in a perfect world, there would be
no SIPs. But the world is not perfect and there are economical and functional reasons to choose SIPs to gain time to
market, prove new applications, or simplify product development. One needs to carefully put all the arguments on the
table. I think it is safe to say that SOCs start with SIPs. This triggers a question – what is the price of converting a SIP
into a SOC? Is the customer willing to pay that price? Is this a long-term cost reduction? Would the quality improve?
Simple spreadsheet calculations can readily prove or disprove the concept. The bigger question is – should one develop
standards for SIPs knowing that to some, they may appear to be merely failed SOCs?
Sreedhar Natarajan
President, Emerging Memory Technologies, Ottawa, ON
www.emergingmemory.com
Semiconductor industry is running into crossroads with technology scaling and innovative solutions are being devised
almost every week. Most of these technologies are SOC based embedded applications, but these technologies are being
limited by performance, power, interconnects etc. As an alternative to SOC, SIP is being progressed substantially in the
last few years and initial implementations of SIP are cost effective. SIP offers flexibility to de-reuse and minimized cost
compared to SOC.
Steven Slupsky
CEO, Scanimetrics, Edmonton, AB
www.scanimetrics.com
As the complexity and functionality of microchips increase, the required die area to perform the necessary functions is
also increasing, despite the fact that process feature sizes are shrinking according to Moore's Law. System-on-chip (SoC)
designs are posing more and more stringent requirements on semiconductor foundries to deal with issues of decreasing
yields due to increased die size. In addition, designers are required to add built-in-self-test (BIST) and design-for-test
(DFT) circuitry in order to test complex SoC designs, necessitating even more die area. The solution to these problems
lies in transitioning from SoC designs to system-in-package (SiP) designs. The key to widespread adoption of SiP in
complex system designs is the reliability, cost and performance of the interconnect technology used between the die.
Standard wire bonding is not suitable for multi-chip applications since it limits the number of die which can be used, the
relative size of each die, the interconnectivity between die, and operating speeds. Scanimetrics offers a wireless die
interconnect technology which address all these issues and promotes the adoption of SiP designs.
Paul Rousseau
Manager, TSMC, San Jose, CA
www.tsmc.com
SOC? It isn’t going to happen for one simple reason, cost. Every generation, customers go through the exercise of
evaluating SOC vs package integration. The latter almost always wins on cost. Of course, there are always exceptions
when SOC is must have for performance or functionality. Increasingly, the strategy is "smart" and targeted integration vs
total integration. This requires a careful analysis of the system architecture from the very beginning, how to partition all
the various blocs to best take advantage of existing technologies.
Panel #2:
"Is analog synthesis going to replace analog and RF designers?"
Ramesh Senthinathan
Director, IO, Analog and Technology Development.
ATI Technologies
www.ati.com
Marek Mierzwinski
President
Tiburon Design Automation
www.tiburon-da.com
Sorin Voinigescu
Associate Professor, University of Toronto
http://www.eecg.toronto.edu/~sorinv/
High-frequency measurements over many foundries and technology nodes down to the 90-nm node indicate very
predictable scaling of the high-frequency and noise performance of MOSFETs. Accurate design of RF and millimeter
wave CMOS circuits should not be an active device issue. Yet RF designers continue to lament the poor quality of
MOSFET models. Interestingly, the models are actually as bad or worse for digital applications -since devices with sub
0.5m gate widths are used - yet the industry has so far been willing to waste power and speed to gain design efficiency.
At the same time, interconnect characteristics are highly predictable and show less process variation than active devices.
As further scaling of digital circuits now faces the interconnect and power dissipation brick wall, the time has likely come
to fix both analog and digital design bottlenecks and open up the way for design automation of circuits operating beyond
10 GHz.
Panel #3:
“We can design SOC but how are we going to test it?”
Bozena Kaminska
Professor
SFU
Changing Economics of SoC Testing: Who Owns the Market?
System-on-a-chip (SOC) designs are gaining popularity, yet the complexity of these designs can slow down product
development and increase cost rather than speed things up. The new economy, the raising role of SoCs and their
escalating costs are forcing the electronic industry to re-examine the existing approach of design and test. For innovative
products the integrated SOC development environment promises to provide the greatest productivity increases, and
therefore the fastest time-to-market while keeping costs under control. Integrated development environment means not
only thinking how to approach physical design, but for industry, including customers and vendors, a fundamental shift is
required in making all critical decisions during system specification and high level design. What the integrated SOC
development environment should look like? What are its essential components? The list of decisions is ranging from
platform choice, to software-hardware partitioning to IP selection to packaging etc. The list is long but higher lever each
decision will be made better outcome will be generated and better trade-off can be reached. Here, our main focus is on
testability. Testability meaning low level SCAN insertion issues, overall SOC test methodology and ATE selection.
Today, there is a believe that design-for-test (DFT) technology and tools will help in solving increasingly high
complexity and cost of SOC testing. DFT including build-in self-test (BIST) gains acceptance and change the
development environment. With a decision on a DFT strategy for SOC the required set of software tools and ATE are
completely different. The software support for DFT becomes comprehensive. The requirements for ATE change and can
vary in level of cost, complexity and software integration. Several ATE vendors are researching and introducing a new
class of structural testers, often called DFT testers. EDA companies are facing the same dilemma from software point of
view.
Andre Ivanov
Professor, UBC
www.ece.ubc.ca/~ivanov
Panel #4:
“Is it worthy to start your own company?”
Resve Saleh
Professor, University of British Columbia
http://www.ece.ubc.ca/~res/
I think that the key question is what type of company should you start? Today, there are many options such as hardware
(chip), EDA, embedded software and IP/Platform design. The risks are very high for a pure hardware company due to the
upfront costs of setting up a design flow, hiring the right people, building relationships with the foundries, and then
testing the chip. The capital requirements alone may be a deterrent to pursue this path. My view is that the chances of
success are quite low. An EDA company has a much lower risk and capital requirements, but would probably end up
being acquired by one of the big companies – not altogether a bad thing. Assuming that you have a good product idea, the
chances of success in one form or another is high. The IP business on the other hand is full of failed attempts because the
requirements for high-quality IP have not been met by smaller companies. The bigger customers are not willing to risk
their designs on some flaky IP blocks from fledgling startups. The ARM, MIPS and Rambus efforts are exceptions but
they have taken many years to gain the credibility to gain their respective market share. Large corporations have a better
chance to make headway in this arena. It would be difficult for a small company to ship a working SoC platform to
customers. Finally, there may be room for those interested in the reusable embedded software market. Perhaps there is a
business model here that would fit the increasing number of embedded applications and the bottleneck that embedded
software presents. Also, hardware/software co-design and co-verification may provide important opportunities for wouldbe entrepreneurs.
Andrzej Strojwas
CTO, PDF Solutions, San Jose
www.pdf.com