3/6/2016
2008 International Symposium on Physical Design
Embassy Suite Portland Downtown, Portland, Oregon
April 13-16, 2008
www.ispd.cc
Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS
Additional support from IEEE/CEDA, Cadence, eASIC, IBM, Magma, Mentor, Pyxis, SRC, Sun and Synopsys
PROGRAM
The International Symposium on Physical Design
provides a high-quality forum for the exchange of ideas
on the physical layout design of VLSI systems. The scope
of this symposium includes all aspects of physical design,
from high-level interactions with logic synthesis, down to
back-end performance analysis and verification.
Regular paper presentations run 25 minutes. Invited talks
are 30 minutes.
SUNDAY, APRIL 13
5:30 – 7:00 pm Evening Reception
MONDAY, APRIL 14
Metal-Density Driven Placement for CMP Variation and
Routability
Tung-Chieh Chen, Minsik Cho, David Pan and Yao-Wen
Chang
Highly Efficient Gradient Computation for Density Constrained
Analytical Placement Problems
Jason Cong and Guojie Luo
Abacus: Fast Legalization of Standard Cell Circuits with
Minimal Movement
Peter Spindler, Ulf Schlichtmann and Frank Johannes
3-D Floorplanning Using Labeled Tree and Dual Sequences
Renshen Wang, Chung-Kuan Cheng, Fan Chung
Graham, Ron Graham, Evangeline Young and Yi Zhu
8:30 – 9:30 am Welcome and Keynote Address
Host: David Pan/University of Texas at Austin
3:10 – 3:40 pm Afternoon break
(Keynote Talk) Design or Manufacturing: Which will be the best
driver for the future of the semiconductor roadmap?
Antun Domic from Synopsys
3:40 – 5:40 am Session 3: Statistical and Physical
Design for Manufacturability—Act II
Chair: Hidetoshi Onodera (Kyoto University)
9:30 – 10:00 am Morning break
(Invited talk) Variations, Margins, and Statistics
Patrick McGuinness from Freescale
10:00 - 11:40 am Session 1: Physical Optimization
Techniques with Buffering and Gate Sizing
Chair: Phiroze Parakh (Mentor Graphics)
RUMBLE: An Incremental Timing-driven Physical Synthesis
Optimization Algorithm
David Papa, Tao Luo, Michael Moffitt, Cliff Sze, Zhuo
Li, Gi-Joon Nam, Charles Alpert and Igor Markov
Robust Gate Sizing via Mean-Excess Delay minimization
Jason Cong, John Lee and Lieven Vandenberghe
Multi-Scenario Buffer Insertion in Multi-core Processor Designs
Yifang Liu, Jiang Hu and Weiping Shi
Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree
Construction
Bruce Tseng and Hung-Ming Chen
(Invited talk) Implications of Device Timing Variability on Full
Chip Timing
Ed Grochowski from Intel
(Invited talks) How To Get Real MAD
Andrew Kahng from UCSD
(Invited talks) A Robust Approach to Lithography Friendly
Design Implementation
Phiroze Parakh from Mentor Graphics
6:30 – 9:30 pm: Dinner Banquet
TUESDAY, APRIL 15
12:00 – 1:30 pm Lunch
8:30 – 10:10 am Session 4: Interconnect Synthesis
and Structured ASIC
Chair: Igor Markov (University of Michigan)
1:30 – 3:10 pm Session 2: Advances in Placement
Chair: Bill Halpin (Synplicity)
(Invited talk) Fast Interconnect Synthesis with Layer Assignment
Charles Alpert from IBM
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(Invited talk) RF Interconnects for Communications On-Chip
Frank Chang and Jason Cong from UCLA
ISPD’08 Global Routing Contest Results
Cliff Sze, IBM
(Invited Talk) Placement Challenges for Structured ASICs
Herman Schmit from eASIC
6:30 – 9:30 pm: Dinner Banquet
10:10 – 10:40 pm Morning break
10:40 – 12:00 pm: Session 5: Logic Optimizations
for Physical Synthesis
Chair: Andrew Kennings (U of Waterloo)
A Framework for Layout-level Logic Restructuring
Hosung Kim and John Lillis
Optimizing Non-Monotonic Interconnect Using Functional
Simulation and Logic Restructuring
Stephen Plaza, Igor Markov and Valeria Bertacco
Reap What You Sow: Spare Cells for Post-Silicon Metal Fix
Kai-Hui Chang, Igor Markov and Valeria Bertacco
12:00 – 1:30 pm Lunch
1:30 – 3:10 pm Session 6: Advances in Routing
Chair: Yao-Wen Chang (National Taiwan U)
Optimal Post-Routing Redundant Via Insertion
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang and
Kai-Yuan (Kevin) Chao
Efficient Multilayer Routing Based on Obstacle-Avoiding Preferred
Direction Steiner Tree
Chih-Hung Liu, Yao-Hsin Chou, Shih-Yi Yuan and SyYen Kuo
An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding
Rectilinear Steiner Tree Construction
Jieyi Long, Hai Zhuo and Seda Ogrenci Memik
Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless
Track Assignment for a Gridless Routing System with Fast
Pseudo-Tile Extraction
Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin and Wen-Nai
Cheng
3:10-3:40 pm Afternoon break
3:40-5:10 pm Session 7: Modern Global Routing
Issues and ISPD’08 Global Routing Contest
Chair: Gi-Joon Nam (IBM)
(Invited Talk) Issues in Global Routing
Bill Swartz from InternetCAD
The Coming of Age of (Academic) Global Routing
Michael Moffitt, IBM
WEDNESDAY, APRIL 16
8:30 – 10:10 am Session 8: Electrical Issues and
Clock Network Design in Physical Synthesis
Chair: Kai-Yuan (Kevin) Chao (Intel)
Statistical Timing Analysis Considering Spatially and Temporally
Correlated Dynamic Power Supply Noise
Takash Enami, Shinyu Ninomiya and Masanori
Hashimoto
Stress Aware Layout Optimization
Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw
and Kanak Agarwal
Discrete Buffer and Wire Sizing for Linked-based Non-tree Clock
Networks
Rupak Samanta, Jiang Hu and Peng Li
Activity and Register Placement Aware Gated Clock Network
Design
Weixiang Shen, Yici Cai, Xianlong Hong and Jiang Hu
10:10am – 10:40am Morning Break
10:40—12:00 pm Session 9: Physical Design for BioMicrofluidics
Chair: Prashant Saxena (Synopsys)
(Invited Talk) Automated Design of Digital Microfluidic Lab-onChip under Pin-Count Constraints
Krishnendu Chakrabarty, Duke University
(Invited Talk) Physical Design Issues in Biofluidic Microchips
Tamal Mukherjee from Carnegie Mellon University
A High-Performance Droplet Router for Digital Microfluidic
Biochips
Minsik Cho and David Z. Pan
12:00 – 1:00 pm Closing Remarks & Lunch
SYMPOSIUM REGISTRATION
Please register on-line at http://www.ispd.cc by March
12th, 2008 for the early registration discount rates.
Registration Rates
Early
Late
ACM/IEEE Member
$380
$455
Non-Member
$455
$530
Student
$170
$220
3/6/2016
HOTEL ACCOMODATIONS AND TRAVEL
ISPD will be held at the Embassy Suites Portland
Downtown Hotel, in Portland, Oregon. The hotel is
located in the downtown area near the Oregon
Convention Center.
Room Rate: $159/single, $169/double
Reserve By: March 12, 2008
Registration code: ACN (either on the web or calling)
Reservations may be made via calling 1-800-EMBASSY
or online via www.embassysuites.com. Be sure to
mention the group code when calling. If you make
reservations online, please enter ACN in the
Group/Convention Code section.
Airport Shuttle: contact the hotel for a reservation.
Reserve early to give yourself the best chance of getting a
room.
Embassy Suites Portland Downtown
Symposium Organization
General Chair
Past Chair
Steering Committee
David Z. Pan / University of Texas at Austin
Patrick H. Madden / SUNY Binghamton
Patrick H. Madden / SUNY Binghamton (Chair), Patrick Groeneveld / Magma,
Lou Scheffer / Cadence, Dennis Sylvester / U. Michigan, Paul Villarrubia / IBM
Technical Program Chair
Gi-Joon Nam / IBM Research
Technical Program Committee
Ameya Agnihotri / Magma
Kai-Yuan (Kevin) Chao / Intel
Bill Halpin / Synplicity
Rob Mains / Sun
Gi-Joon Nam / IBM
Yegna Parasuram / Sierra
Prashant Saxena / Synopsys
Ulrich Brenner / UBonn
Chris Chu / Iowa State U
Andrew Kennings / UWaterloo
Patrick McGuinness / Freescale
David Newmark / AMD
Rob Rutenbar / CMU
Toshiyuki Shibuya / Fujitsu
Yao-Wen Chang/ NTU
Lars Hagen / Cadence
Jens Lienig / TU Dresden
Shigetoshi Nakatake / U Kitakyushu
Hidetoshi Onodera / Kyoto U
Sachin Sapatnekar / UMinnesota
Ankur Srivastava / U Maryland
Publication Chair
Publicity Chair/Webmaster
Prashant Saxena / Synopsys
Yao-Wen Chang / National Taiwan University