A Novel Hybrid Nano Scale MOSFET
Structure for Low Leak Application
Abstract- In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate
leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap
region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap
region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leakage
behaviour of HMOS has been investigated with the help of compact analytical model and Sentaurus
Simulation. The results so obtained show good agreement between model and simulation data. It is found that
HMOS structure has reduced the gate leakage current to great extent as compared to conventional overlapped
MOSFET structure. Further, the proposed structure had demonstrated improved on current, off current,
subthreshold slope and DIBL characteristic.
Keywords- Hybrid MOSFET(HMOS), gate tunneling current, analytical model, spacer dielectrics, DIBL,
subthreshold slope.
1. INTRODUCTION
The successful scaling of MOSFETs toward shorter channel lengths requires thinner gate oxides and higher
doping levels in order to achieve high drive currents and minimized short-channel effects [1-2]. In this
situation, the gate leakage current due to tunnelling through gate oxide becomes very high. Gate leakage is
predicted to increase at a rate of more than 500X per technology generation, while sub-threshold leakage
1
increases by around 5X for each technology generation [3]. Thus, to reduce the gate leakage current in present
era of integrated circuits, new device structures are needed as a method to contain/reduce the gate leakage
current especially for low power battery-operated portable applications [4].
In the past, various techniques have been proposed to control the gate leakage currents. The work in [5]
presents an approach to reduce Isub, but not Igate. The impact of Igate on delay is discussed in [6], but its impact
on leakage power is not addressed. In [7], the authors presented circuit-level techniques for gate leakage
minimization. In each of these reports, extensive SPICE simulations were performed to obtain estimates of
gate leakage. In [8], authors addressed various leakage mechanisms including gate leakage and presented
circuit level technique to reduce the leakage. However, this can be extremely time-consuming, especially for
large circuits. In [9], the authors examine the interaction between Igate and Isub, and their state dependencies.
This work applies pin reordering to minimize Igate. In [10], Lee et al., developed a method for analyzing gate
oxide leakage current in logic gates and suggested pin reordering to reduce it. Sultania et al., in [11],
developed an algorithm to optimize the total leakage power by assigning dual Tox values to transistors. In [12],
Sirisantana and Roy use multiple channel lengths and multiple gate oxide thickness for reduction of leakage.
Mohanty et. al. [13] have presented analytical models and a data path scheduling algorithm for reduction of
gate leakage current. In [14], conventional offset gated MOSFET structure has been widely used to reduce
subthreshold leakage but gate leakage reduction has not been addressed in the literature so far. Thus, the
general problems of gate leakage reduction techniques are the need for additional devices (e.g. sleep
transistors) and the reduction of only one component of leakage. Moreover, transistor level approaches are not
applicable for standard cell designs and require long calculation time. Further, gate level DVT-/DTOCMOS
methods do not offer the best possible solution as the number of gate types limits the improvement.
2
To solve this problem, we propose hybrid MOSFET (HMOS) structure for the first time to reduce the
gate leakage current significantly because gate leakage current through the source/drain overlap region has
been identified as the principal source of power dissipation in VLSI chips especially in sub-1V range [15].
The use of High-k as gate dielectric, further, reduces the gate leakage current by increasing the physical
thickness of the gate dielectric through which carrier tunnel. Also, by adopting high-k dielectric spacers, we
can induce low resistance inversion layer as a S/D extension region in the non-overlap region. An effective
and compact model has been developed for analyzing the gate tunneling current of HMOS by considering the
NSE (nano scale effect) effect that are difficult to ignore at nano scale regime. The NSE effect include (i) the
non-uniform dopant profile in poly-gate in vertical direction resulted due to low energy ion implantation, (ii)
additional depletion layer at the gate edges due to gate length scaling down and (iii) gate oxide barrier
lowering due to image charges across the Si/SiO2 interface. We, also, adopted advanced physical models in
the simulation (Sentaurus simulator) [16] to see other device characteristics such as DIBL (drain induced
barrier lowering), SS (subthreshold slope), on current and off current.
The rest of the paper is organized as follows. Section 2 establishes the gate current model for novel
HMOS. The device design and structure of novel HMOS is presented in Section 3. Section 4. presents the
Sentaurus simulation set up for analysis. The results and discussion are presented in Section 5. Finally,
conclusions and future directions are summarized in Section 6.
2. THEORETICAL GATE CURRENT MODEL
In this, we have considered inelastic trap assisted tunneling as a two step process for simplicity. Firstly,
electrons tunnel into deep lying trap state, become released from the trap state and subsequently tunnel to gate
under the influence of the applied electric field. Because of non overlap region between gate-to-source and
gate-to-drain, the edge direct tunneling current is absent and hence total gate leakage current (Ig) is given by
3
I g  I gc  J ITAT _ ch  Lg
(1)
Where Igc is the gate tunneling current through channel region and
J ITAT _ ch
is the inelastic trap-assisted
tunneling current density through channel region and is given by a detailed balance of Jin and Jout . The Jin and
Jout are tunneling-in current density from inversion layer to the traps and tunneling-out current density from
the traps to the gate respectively. Now, assuming that x is the distance from the Si–SiO2 interface, Ntrap(x, E)
is the sheet trap density in cm2 at a distance x and having the energy level with respect to the conduction band
edge of gate dielectric, Ot(x, E) is the electron occupancy of the traps at a distance of x and the energy of E, σt
is the capture cross section of the traps and Ag is the gate tunneling area.
J in 
 

 
q
 t Ntrap x, qEgi x  b _ eff .  1  Ot x, qEgi1x  b _ eff J1 b _ eff , x, Egi1
Ag
J out 

 
 
q
 t Ntrap x, qEgi1x  b _ eff .  Ot x, qEgi1x  b _ eff J 2 t , t gi  x, Egi2
Ag

(2)

(3)
t  b _ eff  qE gi1 x  E LOSS
where Φt is the barrier height of the gate insulator trap states, Egi is the electric field in the gate insulator, Egi1
is the electric field over a distance x of the trap relative to the interface in the gate insulator and Egi2 is the
electric field over a distance tgi-x relative to the interface in the gate insulator, ELoss is the energy loss
accompanied with the injection of electrons into the neutral trap sites and σt is assumed to be constant
irrespective of the position and energy level of the traps. J1 and J2 are the uniform current densities and are
calculated by modifying the formulation of direct tunneling in Lee and Hu model [17]. b is the interface
barrier height of composite gate dielectric i.e combination of interfacial oxide and high-k gate dielectric. It is
taken as the average of barrier height of interfacial oxide and high-k gate layer. So
b 
b _ ox  b _ hk 
(4)
2
4
b _ hk
where
is the barrier height of high-k gate layer and b _ ox is the barrier height of oxide layer. b _ eff is
the effective barrier height, given as below,
b _ eff  b  
 
The
qEgi

4 eff

(5)
qVgi
4 eff Tgi
 2q3 N DTC (ch)b _ eff

3

16 2 eff





1
4
(6)
is the reduction in the barrier height at the high-k/SiO2/Si interface from Φb so that barrier height
becomes b _ eff . This reduction in barrier height is due to image charges across the interface. This barrier
reduction is of great interest since it modulates the gate tunneling current. NDTC(Ch) is the effective density of
carrier in channel and  eff is the equivalent dielectric constant of composite gate dielectric. We have found the
equivalent dielectric constant of the composite gate dielectric in terms of the oxide thickness by considering
the MOSFET as parallel plate capacitor with two dissimilar dielectrics.
 eff
 t
t gi  t ox 
  ox 

 hk t gi 
  ox t gi
1
(7)
where  eff ,  ox and  hk are the dielectric constants of the equivalent dielectric, interfacial oxide, and the
high-k gate dielectric respectively, tgi is the total thickness of the gate dielectric, and tox is the thickness of
interfacial oxide.
Consequently, inelastic trap assisted tunneling current can be expressed as
J ITAT 



q
 t N trap x, qE gi x  b _ eff .PITAT x, E , E gi
Ag

(8)
where PITAT can be expressed as
PITAT 

 
J 1 b _ eff , x, E gi1 .J 2 t , t gi  x, E gi2




J 1 b _ eff , x, E gi1  J 2 t , t gi  x, E gi2

(9)
5
Using Gauss’s law and considering MOS capacitor equivalent circuit, the local electrical fields Egi1 and Egi2
of both the tunneling regions finally become
E gi1  E gi 
t gi  x qN trap
.
t gi
 eff
E gi2  E gi 
(10)
x qN trap
.
 eff
t gi
(11)
The modified uniform current density J1 and J2 are expressed as




C(ch) t , t gi  x, Egi2
J1 b _ eff , x, Egi1  At

b _ eff
J 2 b _ eff , x, Egi1  At
where

At 




t
  exp  8


3

2meff b _2 eff

.
 b _ eff , x, Egi1 
3hq
Egi1



(12)
3

2meff  2
t
.
 t , t gi  x, Egi2 

3hq
Egi2

(13)



q3
8 b _ eff  eff
c(ch ) b _ eff , x, E gi1

.  exp  8
C(ch ) b _ eff , x, Egi1

 ( ch ) 



 20  x E gi1(ch )  b _ eff _


 1



b _ eff

 b _ eff 


 exp 
.  E gi1 .N DTC (ch )



x
E
gi1( ch ,ov) 
.1 



b _ eff






c(ch ) t , t gi  x, E gi2
 

 (ch ) 
 

 20  (t gi  x) E gi 2(ch )  t


 1
  



t
 t 


 exp 
  E gi 2 .N DTC (ch )
  (t gi  x) E gi 2(ch,ov) 

.1 

t







qx
 (b _ eff , x, E gi1 )  1  1 
E
 b _ eff gi1






3

2
6
 (t , t gi
N DTC (ch )
Where


 q t gi  x
 x, E gi2 )  1  1 
E gi2
t


 eff
 t gi


  eff

 t gi
meff




3
2



 Vg  VFB
naccvt . ln 1  exp  
naccvt






 Vg  Vth
ninvvt . ln 1  exp  
ninvvt



  forV


  forV


g
g
0
0
is the equivalent effective mass of the composite dielectric Taking the resistances in series of the
two layers of the gate dielectric, we have
R gi  Rox  Rhk
(14)
Considering the relaxation time  ox   hk   eff   , we obtain the equivalent effective mass of composite gate
dielectric using Eq. (14) as

m t
mhk t gi  t ox
meff   ox ox 
t gi
 t gi



In the above equations,
 (ch ) is
(15)
the fitting parameter for channel region tunneling ,
parameters, VFB represents the flat band voltage,
depending upon MOSFET biasing condition,
N DTC (ch)
C F ch,ov is
ninv and nacc
are the swing
denotes the density of carrier in channel region
correction factor and
V ge
is the effective gate voltage
excluding poly gate non-uniformity and gate length effect and is equal to V g  V poly . The default values of
and
nacc
are
S
vt
(S is the sub threshold swing and
vt is
ninv
the thermal voltage) and 1 respectively. mox is the
effective mass of electrons in the interfacial oxide layer and mhk is the same in the high-k gate dielectric
layer. The voltage across the gate insulator for different region of operation is as follows.

V  V
 forV 0
Vgi  Vgge ss VFBFB  forVgg 0
(16)
7
where s is the surface band bending of the substrate for channel depending upon the biasing condition of the
MOSFET device including the poly non-uniformity, gate length effects and image force barrier lowering. The
accurate surface potentials expressions in case of channel in weak inversion/depletion, strong inversion and in
accumulation can be taken from [18].The effective gate voltage including the effect of nonuniform dopant
distribution in the gate is derived as follows.
Vge  (VFB  so  V p1  V p 2 ) 
q
2
si N polyTgi
2
 ox
  1  2


2
gi (Vg
 VFB  so )
q si N polyTgi2

 1


(17)
The so , by taking the quantization effect into account, is given [19] as follows
 so  2 s  sQM  VBS
(18)
where sQM can be taken from [18]. This equation (17) includes the non uniformity in the gate dopant profile
through a term
V p1 and
fringing field effect i.e. gate length effect through a term
V p 2 .The
potential drop
V p1
due to non uniform dopant profile in poly Si gate, caused by low energy implantation, is given by
 kT   N poly _ top 
 ln
V p1  
 q   N poly _ bottom 
The
N poly _ top
and
potential drop
V p 2 
N poly _ bottom
V p 2
(19)
are the doping concentration at the top and bottom of the polysilicon gate. The
due to gate length effect, caused by very short gate lengths is given as below
 
Q 2qAN d V

cm
Cd
Lg Cd
(20)

  TF  Tgi  
 
 3  cos  
 
 eff 
  TF

Cd  
ln 



  TF  Tgi  
 1   
 
 

  TF
(21)
8
where A denote the triangular area of the additional charge, Lg is the gate length, Cd is the depletion
capacitance in the sidewalls [20], eff is the effective permittivity of the composite gate insulator, TF is the
thickness of the field oxide, Tgi is the thickness of the gate insulator and δ is fitting parameter equal to 0.95
normally.
3. DEVICE DESIGN
The cross-section of HMOS for the analysis of the gate tunneling current characteristics, is shown in Fig. 1.
HfO2
Spacer
Interfacial
Oxide
Lg
Poly
G
High-k Gate
Dielectric
Non Overlap
Region
Lno
S
D
Halo
Implantation
p-Si
Fig. 1. Schematic cross-section of proposed Hybrid N-MOSFET
The MOSFET has n+ poly-Si gate of physical gate length (Lg) of 35 nm, gate dielectric of 1.0 nm EOT
(equivalent oxide thickness) - 0.3 nm interfacial oxide and 0.7 nm EOT of high-k gate dielectric. The buffer
oxide of 1.0 nm under high-k spacer has been taken to minimize the stress between spacer and substrate. Here
Lno represents the non-overlap length between gate to source/drain. The source/drain extension region are
created with the help of fringing gate electric field by inducing an inversion layer in the non overlap region.
So, HfO2 high-k dielectric is used as spacer because it develops high vertical electric field under non-overlap
region to induce inversion layer. The halo doping around the S/D also reduces short-channel effects, such as
the punch-through current, DIBL, and threshold voltage roll-off, for different non-overlap lengths.
9
4. SIMULATION SET UP
Fig. 2 shows the Santaurus simulator schematic of HMOS. The doping of the silicon S/D region is assumed to
be very high, 1x1020 cm-3, which is close to the solid solubility limit and introduces negligible silicon
resistance. The dimension of the silicon S/D region is taken as 40 nm long and 20 nm high. This gives a large
contact area resulting in a small contact resistance.
Poly Silicon
Gate
D
S
Fig. 2. Sentaurus schematic cross-section of HMOS.
The doping concentration in silicon channel region is assumed to be graded due to diffusion of dopant ions
from heavily doped S/D region with a peak value of 1x1018 cm-3 and 1x1017 cm-3 near the channel. The polysilicon doping has been taken to be 1x1022 cm-3 at the top and 1x1020 cm-3 at bottom of the polysilicon gate i.e.
interface of oxide and silicon. The MOSFET was designed to have Vth of 0.25 V. We determined Vth by using
a linear extrapolation of the linear portion of the IDS-VGS curve at low drain voltages. The operating voltage
for the devices is 1.0 V. The simulation study has been conducted in two dimensions, hence all the results are
in the units of per unit channel width.
10
The simulation of the device is performed by using Santaurus design suite [19], with drift-diffusion,
density gradient quantum correction and advanced physical model being turned on.
Fig. 3 shows the simulated vertical electric field along the channel direction for different spacer in the
non-overlap region for non-overlap length of 5 nm. The vertical electric field is plotted for three different
spacer such as HfO2 (k=22), Si3N4 (k=7.5) and SiO2 (k=3.9). It is clear from the Fig. 3 that magnitude of
vertical electric field increases with the increase in dielectric constant of the spacer. The vertical electric filed
is responsible to induce an inversion layer in the non-overlap region. Result shows that approximately three
times higher vertical electric field is obtained under non-overlap region by HfO2 high-k spacer compared to
the oxide spacer. This implies that the on-state current of the high-k spacer non-overlapped gate to S/D
MOSFET can be significantly larger than that of the oxide spacer MOSFET. This guides the use of
compatible high-k spacer (i.e. compatibleHfO2) to induce the sufficient inversion layer in non-overlap region.
It also shows that vertical electric field magnitude decreases significantly with the distance of non overlap
region from the gate edge thereby limiting the non-overlap length (Lno).
Lg= 35nm
Lno= 5nm
Vgs=1.0 V
Vds=.05 V
Gate
Source
Lno
Lno
Drain
Fig. 3.Vertical electric field along channel for different spacer in the non overlap region.
11
Lg= 35nm
Vgs=1.0 V
Lno= 5nm
Vds=.05 V
Gate
Source
Lno
Lno
Drain
Fig. 4.Vertical electric field along channel with HfO2 spacer in the non overlap region for different gate
dielectrics i.e.SiO2, Si3N4 and HfO2
Fig 4. plots the variation of vertical electric along the channel direction with HfO2 spacer in the non
overlap region for different gate dielectrics i.e.SiO2, Si3N4 and HfO2. It is clear from figure that
the
magnitude of vertical electric field is almost constant with change of gate dielectric. The fringing electric field
is a strong function of dielectric constant of spacer material instead of dielectric constant of gate dielectric
material.
It is observed from the Fig 5. that electron concentration below the spacer also remains constant with
the change of dielectric constant of gate dielectric. This is due to that fact that vertical fringing field remains
constant with the change of dielectric constant of dielectric. However, it is obvious that the vertical fringing
electric field produced by HfO2 high-k spacer is capable of inducing electron concentration of the order of
1x10-18 cm-3 which, in turn, can behave as extended S/D region. Thus, a reasonable amount of electron
concentration was induced for HfO2 spacer.
12
Vgs=1.0 V
Vds=.05 V
Source
Lg= 35nm
Lno= 5nm
Gate
Lno
Lno
Drain
Fig. 5.Electron concentration along channel with HfO2 spacer in the non overlap region for different
gate dielectrics i.e.SiO2, Si3N4 and HfO2
5. RESULT AND DISCUSSION
Computation have been carried out for a n-channel nanoscale hybrid MOSFET (HMOS) to estimate the gate
tunneling current. The interfacial oxide thickness and EOT for high-k gate dielectric have been taken to be 0.3
nm and 0.7 nm respectively with a combined EOT of 1.0 nm. This model is computationally efficient and easy
to realize.
The comparision between the simulated data and the model data for gate tunneling current is presented in
Fig. 6.The figure shows the gate tunneling current versus gate bias for HMOS with HfO2 spacer above the
non-overlap region at an equivalent oxide thickness (EOT) of 1 nm and non-overlap length of 5nm. It is
shown in Fig. 6 that analytical result calculated by our model has better agreement with the simulated results
certifying the high accuracy of the propsed analytical modelling. The simulation for HMOS with HfO2 as
high-k gate dielectric has been carried out with t HfO2 = 3.95 nm,
[21], mhk = 0.18mo [21],  t
=
tint erfacial _ oxide =
0.3 nm.  b _ hk (HfO2) =1.5 ev
9.3×10-16 cm2 [22], Ntrap = 7.67×1012 cm-2 [22]. The trap position ( xt ) is
13
extracted to be 0.35 t HfO2 in the inelastic tunneling model by comparing the magnitude of JITAT with that of
direct tunneling current of MOS capacitors with gate oxides of 3.95 nm. The fitting parameters Eloss and  ch 
have been taken to 0.36 eV, 0.62 respectively to fit the model with the simulated value.
Sentaurus Simulator Data
Model Data
Gtae Tunneling Current (A/um)
1E-18
EOT=1.0 nm
1E-23
Lg= 35 nm
Lno= 5 nm
1E-28
1E-33
0.0
0.2
0.4
0.6
0.8
1.0
Gate Bias (V)
Fig 6. Comparison of analytical model data with Sentaurus simulated data HMOS with equivalent
oxide thickness (EOT) of 1.0 nm, physical gate length of Lg= 35nm and S/D to gate non overlap length
of Lno=5 nm.
Gate Tunneling Current (A/um)
1E-8
1E-13
Conventional MOSFET
HMOS with SiO2 as gate dilectric
HMOS with Si3N4/interfacial oxide stack as gate dilectric
HMOS with HfO2/interfacial oxide stack as gate dilectric (HMOS)
1E-18
1E-23
1E-28
0.0
0.2
0.4
0.6
0.8
1.0
Gate Bias (V)
Fig 7. Gate tunneling current vs gate bias for HMOS with different gate dielectrics e.g. SiO2, Si3N4
and HfO2
14
Fig. 7 shows the variation of the gate tunneling current with gate bias for different gate dielectrics of
HMOS. It is observed that gate leakage current decreases significantly for HMOS compared to overlapped
conventional structure. This is because gate to S/D overlap region is absent in our designed HMOS, so gate
tunneling (leakage) current is reduced to greater extent. The reduction is significant with the increase of
dielectric constant of gate dielectric of HMOS. This is because vertical electric field responsible for carrier
tunneling decreases as the
physical thickness of gate insulator increases with increase in dielectric
constant(k). The simulation for HMOS with Si3N4 high-k gate dielectric has been carried out with
nm,
tint erfacial _ oxide =
t Si3 N 4 =
0.3 nm.  b _ hk (Si3N4)=2.0 ev [21], mhk = 0.20 mo[21],  t =3×10-13 cm2 [23],
1.35
Ntrap
=3x1011cm-2 [24]. The trap position ( xt ) is extracted to be 0.29 t Si3N 4 in the inelastic tunneling model by
comparing the magnitude of JITAT with that of direct tunneling current of MOS capacitors with gate oxides of
1.35 nm. The fitting parameters Eloss and  ch  has been taken to 0.23 eV, and 0.71 respectively to fit the
model with the simulated value.
Fig. 8 plots the gate tunneling current with gate bias for HfO2 based high-k HMOS and overlapped HfO2
based high-k conventional MOSFET at an EOT of 1.0 nm. It is observed that gate leakage current decreases
significantly for HfO2 based high-k HMOS as compared to overlapped HfO2 based high-k conventional
MOSFET especially at low gate bias range. At low gate bias, channel is about to form so that gate leakage
current is mainly due to carrier tunneling through gate to S/D overlap region. The gate to S/D overlap region
is absent in our designed HfO2 based high-k HMOS, so gate tunneling (leakage) current is reduced to greater
extent. However, at higher gate bias range the gate tunneling (leakage) current is mainly due to the carrier
tunneling through the channel region to the gate. Due to this reason, gate tunneling current is almost same for
both structure.
15
1E-14
Gate Tunneling Current (A/um)
Conventional MOSFET with HfO 2/Interfacial oxide stack as gate dielectric
NHMOS with HfO2/Interfacial oxide stack as gate dielectric(HMOS)
EOT=1.0 nm
1E-20
1E-26
1E-32
0.0
0.2
0.4
0.6
0.8
1.0
Gate Bias (V)
Fig 8. Gate tunneling current vs gate bias for HfO2 based high-k HMOS and overlapped HfO2 based
high-k conventional MOSFET at an EOT of 1.0 nm.
Fig. 9. shows the variation of DIBL and SS for HMOS with different gate dielectrics e.g. SiO2, Si3N4 and
HfO2 at an EOT of 1.0 nm. It is observed in Fig 9. that DIBL is maximum (72.55mV/V) for overlapped gate
to S/D MOSFET structure (conventional MOSFET). It is due to the fact that the effect of fringing field on
channel is maximum. Due to this decrease in gate control, the drain electrode is tightly coupled to the channel
and the lateral electric field from the drain reaches a larger distance into the channel. Consequently, this
electrically closer proximity of drain to source gives rise to higher drain-induced barrier lowering (DIBL) in
overlapped gate to S/D MOSFET structure. In non-overlapped gate to S/D MOSFET structure (NMOS),
DIBL improves because lateral electric field from the drain reaches a smaller distance into the channel. This is
due to increase in metallurgical gate length as compared to conventional MOSFET structure in the same
physical gate length. For HMOS, with Si3N4 (HMOS_1) and HfO2(HMOS_2) gate dielectric, DIBL degrades
due to increased coupling of lateral electric field from the drain into the channel because of slightly enhanced
fringing field. It is also shown in Fig. 9 that subthreshold characteristic improves for non overlapped gate to
16
S/D MOSFET structure(NMOS) compared to overlapped gate to S/D conventional MOSFET structure. But,
for HMOS with Si3N4 (HMOS_1) and HfO2 (HMOS_2) gate dielectric, SS degrades due to increased the
depletion capacitance in the subthreshold equation.
110
100
90
120
OMS --> Overlapped MOS
NMOS --> Non-overlapped MOS with SiO2 as gate dielectric
HMOS_1 --> HMOS with Si3N4 as high-k dielectric
HMOS_2 --> HMOS with HfO2 as high-k dielectric
110
80
EOT = 1.0nm
70
100
DIBL
SS
60
50
40
90
30
20
10
Subthreshold Slope,SS (mV/dec)
Drain Induced Barrier Lowering, DIBL (mV/V)
120
80
Conventional MOSFET
0
OMS
NMOS
HMOS_1
HMOS_2
Fig . 9. DIBL, SS for HMOS with different gate dielectrics e.g. SiO2, Si3N4 and HfO2 at an EOT of 1.0
nm.
OMS--> Overlapped MOS
NMOS--> Non-overlapped MOS with SiO2 as gate dilectric
HMOS_1--> HMOS with Si3N4 as High-k gate dielectric
HMOS_2--> HMOS with HfO2 as High-k gate dielectric
1E-6
0.01
Ion
Ioff
1E-7
1E-8
Off Current,Ioff(A/um)
On Current, Ion (A/um)
0.1
1E-3
Coventional MOSFET
1E-9
OMS
NMOS
HMOS_1
HMOS_2
Fig . 10. On and off current HMOS with different gate dielectrics e.g. SiO2, Si3N4 and HfO2 at an EOT
of 1.0 nm.
17
Fig.10. represents the on and off current behavior of HMOS with different gate dielectrics e.g SiO2,
Si3N4 and HfO2. It is observed in figure that on current slightly degrades and off current slightly improves
with increase in dielectric constant of gate dielectric due to increase in threshold voltage (Vth). The Ion/Ioff ratio
greater than 3x104 is achievable for NMOS follow by HMOS_1, HMOS_2 and conventional MOSFET.
The result indicates that non overlapped gate to S/D NMOSFET (NMOS) is better in term of SCE
whereas HMOS_2 is better in term of gate leakage reduction.
It is clear from Fig. 10 that current drivability(Ion), DIBL and SS degrade with the introduction of nonoverlapped gate to S/D MOSFET structure (NMOS and HMOS) as compared to conventional overlapped
MOSFET structure. So, to improve the dive current, DIBL and SS, we propose a dual dielectric spacer HMOS
(modified HMOS i.e. MHMOS) as shown in Fig 11. where spacer consist of 10 nm oxide spacer and 10 nm
high-k HfO2 spacer.
SiO2
Spacer
HfO2
Spacer
Interfacial
Oxide
High-k Gate
Dielectric
Lg
Poly
G
Non Overlap
Region
Lno
S
D
Halo
Implantation
p-Si
Fig. 11 Schematic cross-section of Hybrid N- MOSFET structure with dual spacer (Modified HMOS)
Fig.12 shows the impact of modified HMOS on off and on current. It is observed in figure that on current
improves with the introduction of dual spacer. The improvement is because of the slight decrease in threshold
voltage due to slight reduction in gate fringing field. The slight decrease in threshold voltage (Vth), in turn,
18
slightly degrades the off current for both modified HMOS ( MHOS_1 i.e. modified HMOS with Si3N4 as gate
dielectric and MHMOS_2 modified HMOS with HfO2 as gate dielectric)
4.50E-008
4.00E-008
3.50E-008
0.0008
3.00E-008
0.0007
2.50E-008
Off Current (A/um)
On Current (A/um)
0.0009
HMOS_1 --> HMOS with Si3N4 as gate dielectric
MHMOS_1 --> Modified HMOS with Si3N4 as gate dielectric
HMOS_2 --> HMOS with HfO2 as gate dielectric
MHMOS_1 --> Modified HMOS with HfO2 as gate dielectric
0.0006
2.00E-008
1.50E-008
0.0005
HMOS_1
MHMOS_1
HMOS_2
MHMOS_2
Fig . 12. Impact of modified HMOS on Off and On current with EOT of 1.0 nm
45
100
HMOS_1--> HMOS with Si3N4 as gate dielectric
MHMOS_1--> Modified HMOS with Si3N4 as gate dielectric
HMOS_2--> HMOS with HfO2 as gate dielectric
MHMOS_2--> Modified HMOS with HfO2 as gate dielectric
95
90
40
85
35
80
30
75
25
Subthreshold Slope, SS (mV/dec)
Drain Induced Barrier Lowering, DIBL (mV/V)
50
70
HMOS_1
MHMOS_1
HMOS_2
MHMOS_2
Fig . 13. Impact of modified HMOS on DIBL and SS with EOT of 1.0 nm
19
The impact of modified HMOS on DIBL and SS is plotted in Fig.13. It is observed in figure that DIBL
and SS improves for both modified HMOS i.e. MHOS_1 (modified HMOS with Si3N4 as gate dielectric) and
MHMOS_2 (modified HMOS with HfO2 as gate dielectric) due to slightly reduced coupling of lateral electric
field from the drain into the channel.
It has also been found that there is negligible effect on gate leakage current because of dual spacer in
modified HMOS. Thus, results indicate that ModifiedHMOS_2 show better SCE in addition to significant
reduced gate leakage current.
6. CONCLUSION
In summary, gate leakage aspect of 35 nm HMOS has been analysed with simplified and compact analytical
gate current model including nano scale effect (NSE). A significant gate leakage reduction is demonstrated
by HMOS using HfO2 as gate dielectric. Excellent short channel effects (SCE) are, also, demonstrated for 35
nm HMOS. Further, short channel effects (SCE) are improved by the use of modified HMOS. These results
suggest that modified HMOS is a promising candidate for the future low leak VLSI application.
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