Design of Capacitive Displacement
Sensors for Nanoalingment
A Thesis Presented
by
Jose Luis Medina
To
The Department of Electrical and
Computer Engineering
in partial fulfillment of the requirements
for the degree of
Master of Science
in the field of
Electrical and Computer Engineering
Northeastern University
Boston, Massachusetts
December 17, 2007
ABSTRACT
Nanotechnology is a very promising technology that could potentially have a great
impact in fields such as medicine, electronics, material science, and energy storage.
Improvements in microscopy, as the invention of the Scanning Tunneling Microscope in
1981 and the Atomic Force Microscope in 1986, enabled the observation of molecules at
nanoscale and helped obtain a better understanding of the extraordinary dominant effects
at nanoscale, and later enabled the manipulation of single atoms or molecules.
Furthermore, the discovery of carbon nanotubes brought a novel material with excellent
properties at nanoscale. Fabrication of nanodevices is already a reality. However, in order
for this technology to become cost-effective and available for society, scalable fabrication
processes that would enable massive production of nanodevices must be developed.
Towards this goal, the ‘Center for High Rate Nanomanufacturing’ is developing a
scalable nanomanufacturing process flow based on transferring nanoelements from a
template to a substrate.
For one of the step of this process flow, a alignment of template and substrate at
nanoscale is required. This work aims at designing a capacitive displacement sensor for
alignment of two chips or wafers. First, the alignment process is analyzed and different
sensing techniques studied in relation to this specific project. After that, modeling and
analysis of the sensor is carried out, followed by the design of the sensor, including its
readout circuit.
ii
ACKNOWLEDGMENTS
From my experience studying and researching in several institutions in three different
countries, I know usually advisors care more about the final goals of the project than
about the students who are doing that research. I would specially like to thank professor
McGruer for, not only giving me the opportunity to work with him on this project, but
also for his interest in my academic and personal development, in addition to my research.
I appreciate his guidance through my studies at Northeastern and beginning of my career.
I also want to thank professors George Adams, Demetrios Papageorgiou, Ahmed
Busnaina, Sun, and Sinan Muftu for their help and guidance during my thesis.
In the Northeastern Microfabrication Lab, I want to thank the students Prashanth
Makaram, Andy Pamp, Peter Ryan, Juan Aceros, and Siva Somu for helping with the
tools and equipment in the lab. I also want to thank Jen Dawson, for copyediting my
thesis, and for so much more.
iii
TABLE OF CONTENTS
Abstract
Acknowledgments
ii
iii
1. Introduction
1.1 Nanotechnology and Nanomanufacturing
1.2 Alignment and Nanopositioning
1.3 Displacement Sensors
1.4 Sensor requirements
1.5 Comparison sensors literature and nanoaligner sensor
1
1
2
3
5
2. Sensor design
2.1 Arrangement for connections-free substrate
2.2 Arrangement for large gap variations
2.2.1 Fractal arrangement
2.2.2 Switchable variable width
2.2.3 Central fractal
2.3 Fabrication
8
10
10
12
14
15
3. Modeling
3.1 Capacitance and FEM field solvers
3.2 Modeling scenarios
3.3 Equivalent capacitance circuit
3.4 FEM simulations
3.4.1 Algorithm
3.4.2 Fringing field effect
3.4.3 Influence of plate conductivity
3.5 Convergence
17
22
24
27
27
28
32
45
4. Capacitance-to-voltage converter
4.1 Introduction
4.2 Converters
4.3 Oscillators
4.4 Capacitive Bridge
4.5 Transimpedance amplifier
4.5.1 Gain and noise
4.5.2 Stability
4.5.3 Demodulator
4.6 Switched-Capacitor Converter
4.6.1 Switched-Capacitor Amplifier
4.6.2 Parasitic Capacitance
4.6.3 Correlated Double Sampling
49
50
51
52
52
52
55
59
60
60
63
64
iv
4.6.4 Bandwidth
4.6.5 Noise Analysis
4.6.6 Simulations
4.7 Sigma-Delta modulator
68
70
73
76
5. Experimental verification
5.1 Scaled model
5.2 Setup
5.3 Readout circuit
5.4 Designs tested
5.4.1 Large features test board
5.4.2 Central fractal test board
81
84
85
86
87
90
6. Conclusions and future work
6.1 Experimental results
6.2 Recommendations for design
6.3 Future work
93
95
97
Appendices
A. Calculation of equivalent output capacitance
B. APDL macro for capacitance extraction simplified model table 3.2
C. APDL macro model for large gap and displacement range table
D. MATLAB filter for ANSYS capacitance results
E. APDL macro to calculate capacitance versus number of nodes per
electrode’s horizontal surface
F. Input equivalent capacitance for connected plates.
G. Hspice code readout circuit Figure 4.24 and RC LPF
v
101
vi
1. Introduction
1.1 Nanotechnology and Nanomanufacturing
Nanotechnology can be defined as the engineering of functional systems at nanometer
scale, i.e. at the molecular scale. Currently there is technology available that enables
manipulation single molecules and building of nanodevices [1.5]. However, in order for
nanotechnology to become commercially available for the general public, instead or
manipulating single molecules at a time, billions of molecules have to be manipulated at
a time. A scalable nanomanufacturing process that would enable the fabrication of
nanodevices at high rates is one of the main keys towards the commercialization of
nanotechnology.
1.2 Alignment and Nanopositioning
Towards the successful commercialization of nanotechnology, the ‘Center for High Rate
Nanomanufacturing’ (CHN) aims to develop a process flow that would enable scalable
fabrication of nanodevices. A novel process studied at this center involves the transfer of
nanotubes and or nanoparticles from a template to a substrate. In order for the transfer to
be successful, an extraordinarily accurate alignment between substrate plate and template
plate must be achieved. This alignment would have two phases. A first phase would align
the plates up to a few nanometers by means of a displacement sensor. A nanopositioner,
like the one in Figure 1.1, would be used to move the plates, while a displacement sensor
1
would sense the relative position and close the feedback loop. The nanopositioner would
move one of the plates, while the other one would remain static.
Figure 1.1: Model of nanopositioner used for high rate nanomanufacturing [1.6].
Then, the second phase of the alignment would take over, where molecular forces of
chemical and physical nature would further align the plates. Once alignment is achieved,
the nanotubes or nanoparticles would be transferred from template to substrate.
1.3 Displacement Sensors
Displacement sensors are widely used in industry. Most displacement sensors are based
on transducers that convert displacement to another signal such as temperature, light, or
electrical resistance. The main transducer principles are given in the following table.
Criteria
Probe-based
Optical
Capacitive
Thermal
Accuracy
++
++
+/++
+/++
Range
-/+
++
+/++
+/++
Speed
+
+
+
Fabrication
-++
++
Electronics integration
+
++
++
Parasitic forces
-/+
++
--/+
Power consumption
+/++
-/+
++
+
Table 1.1: Main displacement sensor transducers that enable integration within a MEMS device, with
accuracy in the nm-range, and range over 100 μm [1.1].
Optical transducers achieve high accuracy, but are complex to fabricate and integrate.
Capacitive transducers are easier and inexpensive to fabricate, can easily be integrated in
2
any system, and do not need complicated electronics. On the other hand, capacitive
transducers are highly affected by any surrounding capacitances different from the
capacitance to be measured. Thermal transducers are simple and inexpensive as well,
although the measurement is slower.
1.4 Sensor requirements
To align two chips or wafers, a displacement sensor can be integrated in the chips to align,
so that the relative position of both chips can be sensed.
A displacement sensor for plate alignment must meet several characteristics from
fabrication and economics point of view. First, its fabrication should be compatible with
the nanomanufacturing process flow, and enable integration. Second, it must be flexible
and compatible with general nanopositioner equipment. Third, it should be as
inexpensive and robust as possible. A probe-based converter may not be compatible with
the alignment process and nanopositioner. An optical transducer would require a complex
circuitry to obtain an electrical signal for the feedback. A thermal actuator may be too
slow, which would require a more complex controller for the feedback and may result in
instability. A capacitive transducer is easy to integrate in the feedback loop with rather
simple circuitry, and inexpensive to fabricate. Furthermore, built-in capacitive sensors
can easily be fabricated on top of the same plates to align, which results in easier
integration in the alignment process and compatibility with the nanopositioner. For all
these reasons, capacitive transducers are used for this project’s purposes.
As illustrated in the following figure, a group of metal strips can be fabricated on the
chips to align, in a way that the capacitance between the strips in the substrate and the
3
strips in the template would depend on the relative position of the plates. Four
independent sensors are incorporated on both plates, two sensors oriented in one direction
and the other two perpendicular. In principle, these four sensors should be able to
determine the relative position of both plates in six degrees of freedom.
Figure 1.2: substrate and template plates (grey) with built-in electrodes (yellow) for capacitive sensing.
Figure 1.3 shows the strips on substrate and template.
Figure 1.3: Detail of substrate and template strips. The figure on the left shows the
pads for external connections.
The main drawback of this approach is the parasitic capacitances in the sensor, which
deteriorates the sensor performance. Care should be taken in the design of the electronic
readout circuit to minimize the influence of parasitic capacitances.
4
1.5 Comparison sensors literature and nanoaligner sensor
There is extensive research literature in the field of micromachined capacitive sensors for
applications such as Bioengineering [1.2], positioners [1.3], temperature and humidity
sensor [1.7], and automotive [1.4]. Most of these sensors are based on two parallel
electrodes, where the overlapping area of the electrodes changes with the lateral
displacement of the plates, while the gap remains constant.
Figure 1.4: Schematic model of a capacitive position sensor [1.2].
Humidity and temperature capacitive sensors have fixed electrodes, so the structure
usually used for these sensors is quite different from the structure needed for alignment
with a nanoaligner [1.7]. Something common in all displacement sensors reviewed during
the literature research done is that in all sensors only one dimension varies, while the
other dimension is meant to stay as constant as possible. Indeed, in most displacement
sensors, the gap between the electrodes is kept constant, while the overlap electrode area
changes with displacement. The sensor in Figure 1.4 follows such approach. Typically
capacitive sensors are based on the capacitance from the strips on one plate to the strips
on the other plate.
5
~
Figure 1.5: typical scheme used in capacitive displacement sensors. The top strips and the bottom strips are
attached to two different plates. An excitation is applied to the strips on one plate, while the strips on the
other plate are connected to a readout circuit. The gap remains constant, while the plates move laterally in
parallel to each other. The sensor detects the relative plate displacement.
Unlike these sensors, a sensor aimed at alignment with a nanopositioner like the one
shown in Figure 1.1 would have two novel main requirements. First, in order for the
nanopositioner to move one of the plates, this plate must be free of connections.
Therefore all the connections to a readout circuit have to be done to the static plate. This
means that a scheme such as the one in Figure 1.5 cannot be used, since this scheme
requires connections to both top and bottom plates.
Second, capacitive sensors are usually designed to work under either a constant gap or an
overlapping area constant. In this way the electrode geometry can be optimized for given
range. However, in this project it will be assumed that the nanopositioner starts the
alignment at a long gap. Once the best possible alignment is achieved at that gap, the gap
is decreased, so the sensitivity of capacitance to displacement increases, and a new finer
realignment can be achieved. This process is repeated several times until the minimum
gap before contact is reached. As a first assumption, the gap at the beginning of
alignment process would be 0.5 mm, while the last smallest gap could be as short as 50
nm. A widely variable gap introduces an important issue to overcome in the sensor
6
design. Parallel plate capacitors such as the ones shown in Figure 1.5 become insensitive
to lateral displacement if the ratio of strip width to gap is large. A large number of strips
with small width would give high sensitivity for small gaps, but it would be almost
insensible to lateral displacement for long gaps. However, a smaller number of strips with
larger width would result in greater sensitivity for large gaps, but less sensitivity for small
gaps. Potential solutions and trade-offs to this issue, such as fractal geometries with sets
of electrodes with different width, will be addressed during the sensor design.
References:
[1.1] A. A. Kuijpers, ‘Micromachined Capacitive Ling-Range Displacement Sensor for
Nano-positioning of Microactuator Systems’, PhD thesis, Universiteit Twente.
[1.2] A. Pedrocchi, S. Hoen, G. Ferrignl, A. Pedotti, ‘Perspectives on MEMS in
Bioengineering: A Novel Capacitive Position Microsensor’, IEEE Vol. 47, No. 1, January
2000
[1.3] H. U. Meyer, ‘An Integrated Capacitive Position Sensor’, IEEE Vol. 45, No. 2,
April 1996
[1.4] G. Brasseur, B. Brandstatter, H. Zangl, ‘State of the Art of Robust Capacitive
Sensors’, IEEE 2003.
[1.5] A. Busnaina, ‘Nanomanufacturing Handbook’, Northeastern University, Boston,
CRC Press
[1.6] A. Busnaina, ’High-rate Directed Assembly of Nanoelements’. NSF presentation
[1.7] A. Tetelin, C. Pellet, ‘Modeling and Optimization of a Fast Response Capacitive
Humidity Sensor’, IEEE Sensors Journal, Vol. 6, No. 3, June 2006.
7
2. Sensor design
2.1 Arrangement for connections-free substrate
As explained before, the scheme of Figure 1.4 would be incompatible with the alignment
process, since the nanopositioner needs the moving plate to be free of connections.
Instead, a scheme such as the one shown in Figure 2.1 could be used.
Figure 2.1: scheme of capacitive sensor with connections (the black arrow on the left and the voltage
source on the right) on only one side and equivalent capacitances. The capacitance symbols represent the
main capacitances between electrodes.
In the scheme of Figure 2.1 the two bottom electrodes 1 and 2 would be attached to plate
4, while top electrode 3 would be attached to plate 5. As in Figure 1.5, several groups of
strips could be placed in parallel to increase the capacitance. The resulting capacitance
that the detection circuit would sense when connected to electrodes 1 and 2 neglecting
capacitances to plates 4 and 5 would be
Ctotal  C12 
C13C 23
C13  C 23
(2.1)
A scheme similar to the one in Figure 2.1 is used for differential capacitive sensors [2.1].
This is shown in the following figure.
8
Figure 2.2: differential capacitor. The figures show the bottom plate, the bottom electrodes and the top
electrodes. In the figure on the left, three electrode groups are set in parallel to increment the capacitance.
The figure on the right shows a simplified model of the capacitances [2.1].
The differential sensor of Figure 2.2 uses excitation applied at electrode 3 (the top
electrode), while electrodes 1 and 2 are connected to a differential amplifier. Figure 2.3
shows a differential readout circuit and the electrical signal through its stages when there
is a displacement [2.2].
Figure 2.3: differential capacitor sensor and readout circuit [2.2]. The circuit is based on a differential
transimpedance amplifier as explained in section 4.5.
The circuit of Figure 2.3 models the sensor capacitance C1 and C2 of Figure 2.2 as an
initial capacitance Cx0 plus an increment due to a lateral displacement. This increment is
the same in absolute value for both capacitances C1 and C2, but of opposite signs. The
output voltages are processed by the circuit independently and subtracted at a final stage.
9
Therefore the sensitivity of capacitance to displacement compared to single capacitive
sensors is twice as much. This scheme is useful for alignment if a connection to the plate
moved by the nanopositioner is possible. Otherwise, the scheme of Figure 2.1 should be
considered.
2.2 Arrangement for large gap variations
Capacitive sensors composed of parallel strips or plates as in Figure 1.4 are designed to
have a gap around 10 times smaller than the strip width. As will be shown in section 3.4.2,
larger gaps than one third of the width would give poor sensitivity of capacitance to
lateral displacement. Therefore, hypothetically, a parallel plate capacitor for lateral
displacement sensing would need to be optimized for a specific gap or a short range
around it. In the following sections several approaches are proposed to overcome this
issue. These approaches will be analyzed by means of a FEM simulator in Chapter 3.
2.2.1 Fractal arrangement
Fractals can be defined as geometrical objects that are self-similar under a change of
scale, for example, magnification [2.3]. In principle, the strips of a capacitor could be
arranged in fractal geometry, in a way that the different levels of the fractals would be
used for different gaps.
The simplest and first discovered fractal is the Cantor set [2.4]. This fractal is constructed
be deleting the open middle thirds of a set of line segments. The first step starts by
deleting the open middle third from the interval [0, 1], leaving two line segments:
[0, 1/3] , [2/3, 1]. Next, the open middle third of each of these remaining segments is
10
deleted. This process is continued ad infinitum. Figure 2.4 shows the first six steps of the
process [2.4].
Figure 2.4: From the top to the bottom, first six steps of Cantor set [2.4].
A capacitor arranged in such way would be expected to give peaks with displacement that
would be divided in several new peaks for shorter gaps. These new peaks would be again
divided in new peaks for even shorter gaps, and so on. Instead of dividing a line into
three segments, for the sensor design the line is divided in five segments, where the
second and fourth segment would be removed. The following figures show the process.
For small gaps, a couple of strips is used to sense lateral displacement.
Figure 2.5: first fractal level
When the gap increases, the association of the first level unit with the strips around it
takes over, sensing as it was one unit.
Figure 2.6: second fractal level
In a similar way, for longer gaps, three second level units form a larger unit, which gives
the third level.
11
Figure 2.7: third fractal level
And finally, for larger gaps, the fourth level takes over
Figure 2.8: fourth fractal level
For a three electrodes scheme as in Figure 2.1, hypothetically the fractal arrangement
could be implemented as well:
Figure 2.9: first fractal level
Figure 2.10: second fractal level
Figure 2.11: third fractal level
Figure 2.12: fourth fractal level
12
2.2.2 Switchable variable width
By connecting and disconnecting different strips, the sensor configuration can be changed
and adapted to the most convenient arrangement for a specific gap. With the threeelectrode configuration of Figure 2.1, for small gaps the electrodes can be arranged as in
Figure 2.13.
Figure 2.13: first level arrangement for short gaps. The colors represent the three groups of electrodes that
are connected.
For larger gaps, two consecutive plates can be grouped as one plate, obtaining a larger
plate, as shown in Figure 2.14.
Figure 2.14: second level arrangement for short gaps.
And further on, more consecutive plates can be grouped for larger gaps as in Figure 2.15
and Figure 2.16
13
Figure 2.15: third level arrangement for short gaps.
Figure 2.16: fourth level arrangement for short gaps.
The sensor configuration could be changed by means of switches that would connect the
different parts.
2.2.3 Central fractal
The central fractal geometry is meant to obtain high resolution for short gaps while still
using electrodes with large width. Starting with three groups, instead of continuing the
fractal in the three groups, only the central part is replaced by three identical parts. The
process can be repeated ad infinitum with the new three central parts.
The geometry starts with three identical parts as shown in Figure 2.17.
Figure 2.17: capacitor geometry arranged in three identical groups
Then the central part is replaced by three more parts as in Figure 2.18.
Figure 2.18: capacitor geometry of Figure 2.17 replacing the central group by three identical groups
14
And further on, the central part is replaced by three more parts as in Figure 2.19.
Figure 2.19: capacitor geometry of Figure 2.18 replacing the central group by three identical groups
To decrease the change in capacitance with the gap, the lateral groups could be
disconnected and left floating once the alignment at that level has been achieved and the
gap is reduced. This would probably increase the sensitivity of the sensor as well, since
the capacitance from the larger groups may overlap the changes in the smaller groups for
short gaps.
2.3 Fabrication
The fabrication of the capacitor sensor is rather simple, with a three steps process. First,
to isolate the chip substrate from the capacitor electrodes, a layer of oxide is grown.
Figure 2.20: first step fabrication process. Substrate (grey), silicon dioxide (brown)
Second, metal is deposited to form the electrodes. A thin layer of zinc is deposited,
followed by a layer of gold.
Figure 2.21: second step fabrication process. Deposition of Zn (green), and gold (yellow)
15
The third step is pattern of the metal. Photoresist is spunned on top, and exposed by
optical lithography.
Figure 2.22: clear mask for metal pattern. The green line delimits the section showed in following figures
Figure 2.23: chip section after exposure. From the bottom to the top: substrate (grey), oxide (brown), Zn
(green), gold (yellow), photoresist (blue).
Once the photoresist is exposed, the metal is etched, and the photoresist removed.
Figure 2.24: chip section
16
Reference:
[2.1] Z. Liu, Q. Huang, W. Li, ‘A differential Capacitive Mini-Displacement Sensor’,
Key Lab. Of MEMS of the Minist. Of Educ., Southeast Univ., Nanjing, China. Sensors,
2004. Proceedings of IEEE.
[2.2] J. C. Lotters, W. Olthuis, P. H Veltink, ‘A sensitive differential capacitance to
voltage converter for sensor applications’. IEEE Vol. 48, No. 1, February 1999
[2.3] McGraw-Hill Encyclopedia of Science and Technology. Copyright © 2005 by The
McGraw-Hill Companies, Inc.
[2.4] http://en.wikipedia.org/wiki/Cantor%27s_fractal_set
17
3. Modeling
3.1 Capacitance and FEM field solver
When a battery is connected to two isolated conductors, the battery extracts negative
charges, i.e. electrons, from one conductor to the other, until a determined difference of
potential is achieved. This is shown in Figure 3.1.
Conductor a
e-
+
+
+
+
+
+
+
+
Q
+
+
+ +
+
++++++++++++++++++++++++++++

E
Vs
e-
-
- - - - - - - - - - - - - - - - - - -Q
Conductor b
Figure 3.1: two conductors being charged by a battery
Capacitance is defined as the ratio of the charge stored to the voltage applied.
C
Q
Vs
(3.1)
The capacitance of a system only depends upon the geometry of its elements and the
material properties of the surrounding medium. The capacitance of simplified models,
such as uniformly charged parallel plate capacitor, can be obtained analytically by
resolving Maxwell’s equations. Although analytical solutions to more complex
geometries are sometimes available in transmission line and microstrips theory literature
[3.1]-[3.4], numerical methods are needed to obtain accurate solutions for systems
composed by more than two electrodes.
18
Finite Element simulations calculate ground capacitance, which relates the charge on
each conductor with the conductor’s voltage drop to ground [3.5]. The following figure
illustrates a system with four conductors, where the fourth one is ground.
Figure 3.2: Multielectrode system with three conductors and ground
The ground capacitances are given by Eqns. 3.2-3.4
Q1=Cg11U1+Cg12U2+Cg13U3
(3.2)
Q2=Cg21U1+Cg22U2+Cg23U3
(3.3)
Q3=Cg31U1+Cg32U2+Cg33U3
(3.4)
Where Ui is the potential of conductor i, Qi is the charge of conductor i, and Cgij is the
ground capacitance of electrode i to electrode j. A matrix of ground capacitance is
defined from the coefficients of Eqns. 3.2-3.4
C g11 C g12

C g  C g 21 C g 22
C g 31 C g 32

C g13 

C g 23 
C g 33 
(3.5)
For a linear system Cgij=Cgji, and therefore Cg becomes symmetric. Because ground
capacitance does not relate the capacitance between conductors, circuit simulators such as
Spice use lumped element capacitance models. A lumped model is defined as a model in
which the dependant variables of interest are function of time only, as opposed to
19
distributed models, whose variables are function of time and more spatial variables [3.6].
The lumped circuit model of the system of Figure 3.2 is shown in Figure 3.3.
Figure 3.3: Lumped capacitor equivalence of four conductor system
The lumped matrix capacitance is extracted from the ground capacitance equations.
Q1=(Cg11+Cg12+Cg13)(U1-0)+(-C12)(U1-U2)+ (-C13)(U1-U3)=Cl11U1+Cl12(U1-U2) +Cl13(U1-U3)
Q2=(-C21)(U2-U1)+ (Cg21+Cg22+Cg23)(U2-0)+ (-C23)(U2-U3)=Cl21(U2-U1)+Cl22U2 +Cl23(U2-U3)
Q3= (-C31)(U3-U1)+ (-C32)(U3-U2)+ (Cg31+Cg32+Cg33)(U3-0)=Cl31(U3-U1)+Cl32(U3-U2)+Cl33U3
(3.6), (3.7), (3.8)
The lumped matrix capacitance is therefore obtained from the ground capacitance with
the following relation.
C g11  C g12  C g13

 C g12
 C g13


Cl  
 C g12
C g12  C g 22  C g 23
 C g 23




C

C
C

C

C
g 13
g 23
g 13
g 23
g 33 

(3.9)
To illustrate an example of matrix capacitance, the results from a capacitance extraction
simulation of a five electrode system with ANSYS are shown below
20
________________ CMATRIX SOLUTION SUMMARY ___________________
*** Ground Capacitance Matrix ***
Self Capacitance of conductor 1. =
Self Capacitance of conductor 2. =
Self Capacitance of conductor 3. =
Self Capacitance of conductor 4. =
Self Capacitance of conductor 5. =
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Ground capacitance matrix is stored in
*** Lumped Capacitance Matrix ***
Self Capacitance of conductor 1. =
Self Capacitance of conductor 2. =
Self Capacitance of conductor 3. =
Self Capacitance of conductor 4. =
Self Capacitance of conductor 5. =
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Mutual Capacitance between conductors
Lumped capacitance matrix is stored in
0.30142E-03
0.30118E-03
0.54565E-03
0.35634E-02
0.35719E-02
1. and 2. =
-0.45432E-06
1. and 3. =
-0.19700E-03
1. and 4. =
-0.24790E-04
1. and 5. =
-0.79176E-04
2. and 3. =
-0.19686E-03
2. and 4. =
-0.24780E-04
2. and 5. =
-0.79081E-04
3. and 4. =
-0.12600E-03
3. and 5. =
-0.25787E-04
4. and 5. =
-0.33717E-02
3d array parameter cmatrix ( 5., 5.,1)
0.22795E-16
0.33339E-16
0.39858E-16
0.16123E-04
0.16122E-04
1. and 2. =
0.45432E-06
1. and 3. =
0.19700E-03
1. and 4. =
0.24790E-04
1. and 5. =
0.79176E-04
2. and 3. =
0.19686E-03
2. and 4. =
0.24780E-04
2. and 5. =
0.79081E-04
3. and 4. =
0.12600E-03
3. and 5. =
0.25787E-04
4. and 5. =
0.33717E-02
3d array parameter cmatrix ( 5., 5.,2)
Capacitance values are per unit length
Capacitance matricies are stored in file cmatrix .txt
_____________________________________________________________
Figure 3.4: capacitance extraction simulation output with ANSYS. The solution given by ANSYS includes
both the ground capacitance matrix from the simulations and the lumped capacitance matrix for a lumped
circuit model.
In order to obtain the matrix capacitance of a system, the following equation, known as
Gauss’s law, can be used.

Qi   o r  E (r )dAi
(3.10)
Ai
 

where Qi is the charge of electrode -i, E (r ) is the electric field at point r , εo and εr the
vacuum permittivity and medium relative permittivity, and Ai is the area of integration
around electrode -i. Due to numerical reasons, a more efficient way to calculate
capacitance is by using the principle of energy conservation [3.7].
21
W


   2
1
1    
 o   r (r ) E (r ) dV   E (r ) D(r )dV
2 V
2V
(3.11)
Instead of using Eqn. (3.1), the following relation of energy and capacitance is used.
W 
1
CU 2
2
(3.12)
Eqn. (3.12) is used to set up a system of equations that relates voltage differences to
energy stored.
C  W 
U1,12 2 U1,132 U1,14 2 U1, 232 U1, 24 2 U1,34 2   12   1 

2
2
2
2
2
2   C13 
W2 
U 2,12 U 2,13 U 2,14 U 2, 23 U 2, 24 U 2,34  C  W 
1
14
3
.
.
.
.     
W4
 C23
2
.     
 .
   
U 2 U 2 U 2 U 2 U 2 U 2  C24  W5 
6 ,13
6 ,14
6 , 23
6 , 24
6 , 34 
 6,12
C34  W6 
(3.13)
Eqn (3.13) represents a system of 4 electrodes, which has 6 unknown capacitances. Even
though different electrode potentials would give a completely different electric field
distributions, the capacitance must remain the same because it is exclusively a geometric
and material factor. Using this principle, any electrode potential Uk,ij can be used as
boundary condition. Once the electric field is obtained for a particular boundary
condition, the energy is calculated with the numerical equivalent of Eqn. 3.11
Wk 
1 l n
2
2
2
2
2
2
E xk ,l  E yk ,l  E zk ,l  Dxk ,l  D yk ,l  Dzk ,l  velem,l

2 l 1
(3.14)
The process is repeated until the number of required independent equations is obtained.
Once mutual capacitances are calculated, self capacitances can easily be calculated with
the following expression
Cii  
22
n
C
j 1, j i
ij
(3.15)
It can easily be verified that the ground matrix capacitance given in the example above
matches Eqn. (3.15).
3.2 Modeling scenarios
In electrostatic, magnetic, and thermal domain, a system model can be classified as open
scenario or closed scenario [3.5]. A closed scenario is a model whose field is restricted to
a determined area by its boundary conditions.
Figure 3.4: Three conductor system modeled as closed scenario
On the other hand, an open scenario assumes that the field is not restricted and extends
indefinitely. An open scenario can be seen as a closed scenario with boundary conditions
at the infinity. There are three main approaches to model the far-field. The simplest one is
to assume a natural boundary condition that the field has to match. This is illustrated in
Figure 3.5.
Figure 3.5: Three conductor system. Natural boundary condition to model far-field
A more accurate approach to model far-fields is by defining Far-field elements around
the area to model, as illustrated in Figure 3.6
23
Figure 3.6: Three conductor system. Far-field elements (infinite elements) to model far-field
The most accurate approach, although restricted to 3D models, is to define a Trefftz
domain. This method models the far-field with hybrid infinite elements and Trefftz nodes.
This is illustrated in Figure 3.6.
Figure 3.6: Three conductor system. Trefftz method to model far-field
If the plates to align were conductive and could be connected to ground, a closed model
scenario could be used to simulate the system. However, for the most general case, no
connection to either plate is assumed. Therefore an open model scenario must be used.
Due to the large number of strips that compose the sensor, and the longitudinal
geometrical symmetry, 2D simulations are accurate and far more computationally
efficient. Thereby, infinite elements were used as modeling scenario for the project’s
sensor.
3.3 Equivalent circuit
In Figure 2.1 the capacitances between electrodes 1, 2, and 3 are illustrated. For the most
general case, however, the plates which will be aligned are conductors as well. This
24
means that the system is composed of 5 electrodes instead of 3, with mutual capacitances
from every electrode to every electrode.
Figure 3.7: Sensor capacitance model
The scheme of Figure 3.7 can be simplified to a circuit with lumped capacitances. This
circuit is shown in Figure 3.8.
Figure 3.8: Sensor equivalent circuit
The equivalent circuit of Figure 3.8 can be simplified to an equivalent input impedance
from nodes 1-2. To do so, a test voltage is applied between nodes 1 and 2. By applying
the loop-current method, the test current is obtained in function with the equivalent
impedance. In order to resolve a circuit with b branches and n nodes, b-n+1 equations are
sufficient to obtain the current through every branch [3.8]. The following figure shows
the six branches whose equations are to be obtained, and the current references.
25
Figure 3.9: Circuit graph with selected tree and branch current references
The selected branches are a, b, c, d, e, and f. The current in the remainder branches g, h, j,
and k can be obtained as a function of the selected branches.
ig=ia+ib+if
(3.16)
ih=ig -id -ie=ia+ib+if -id - ie
(3.17)
ij=if+ik-id=ib+ic+if -id -ie
(3.18)
ik=ib+ic –ie
(3.19)
Assuming an impedance Zij at every branch, and applying a test voltage in branch g, the
following circuit is obtained
Figure 3.10: Circuit to obtain equivalent impedance
To resolve the circuit, the current equations of the six fundamental branches are obtained
as in Table 3.1.
26
Loop
Branches
Equation
a
a, h, g
0=Z23 ia + Z13 ih - Vt
b
b, k, j, h, g
0=Z24 ib + Z45 ik – Z35 ij + Z13 ih -Vt
c
c, k, j
0=Z34 ic + Z45 ik – Z35 ij
d
d, h, j
0=Z15 id – Z13 ih + Z35 ij
e
e, h, j, k
0=Z14 ie – Z13 ih + Z35 ij –Z45 ik
f
f, j, h, g
0=Z25 if – Z35 ij + Z13 ih - Vt
Table 3.1: Fundamental branches, loops’ branches, and loop equations
Substituting the currents ig, ih, ij, and ik from Eqns. (3.16)-(3.19) into the equations in
Table 3.1, a system of six equations with six unknown currents is obtained. Calculated
the fundamental branch currents, the test current it is obtained with Eqn. (3.16). The
equivalent impedance is then calculated as,
Z equiv 
it
 Z12 .
Vt
(3.20)
To resolve the system of equations for generic capacitance Cij , the equations from Table
3.1 were implemented in MATLAB. The code and results are given in appendix A.
A first interesting result that can be extracted from the output capacitance expression is
the weight of every capacitance over the total output capacitance. This can be obtained as
the partial derivative of the output capacitance
Cout Cout (Cij  Cij )  Cout (Cij )

Cij
Cij  Cij
(3.21)
Table 3.2 shows the derivative of the output capacitance respect to each lumped
capacitance. The lumped capacitance values were extracted from one of the simulation of
Section 3.4.
27
Cij
Set up point [pF/μm]
dC/dCij
C12
3.8079e-5
1
C13
1.108e-5
0.2148
C14
7.677e-4
0.2488
C15
5.518e-4
0.2453
C23
7.263e-6
-0.2596
C24
7.692e-4
0.2444
C25
5.540e-4
0.2393
C34
9.059e-4
-0.0078
C35
1.265e-4
-0.0056
C45
0.2314
-3.01e-5
Table 3.2: Derivative of output capacitance respect to each lumped capacitance.
Results from one of the simulation of section 3.4. The capacitance between the two plates (C 45),
and from electrode 3 to both plates have almost no influence in the output capacitance
3.4 Simulations
3.4.1 Algorithm
A finite element simulation software (ANSYS), was used to model and simulate the
sensor. As illustrated in Figure 3.4, ANSYS calculates the matrix capacitance for a given
model. A model is defined basically by its geometry, material properties, element
properties, electrode’s nodes, and mesh. To obtain the sensor response to lateral
displacement, a series of simulations was performed, in which the plates' relative position
was varied. This resulted in vectors of capacitance and displacement, which can be
plotted as capacitance versus displacement. Once the lumped matrix capacitance is
obtained, the equivalent capacitance is calculated as explained in Section 3.1. This gives
the input equivalent capacitance that a readout circuit connected to the sensor would ‘see’.
Since a large number of simulations had to be carried out for every geometry to obtain
curves capacitance-displacement, macros in APDL language were written. The macro
28
codes for the simulations are given in different Appendices. The diagram in Figure 3.11
shows the algorithm on which the macros were based.
k=1
Plate displacement
δ=[δ1, …, δN]
k=k+1
δk
k = 1?
no
Remove model
yes
Define geometry
material properties
and element type
Define number of
nodes
Mesh
Set up external flag
and electrodes
solve
Store results Cijk
k=N?
no
yes
Cij=[Cij1,…,CijN]
Figure 3.11: Flow diagram of FEM simulations with ANSYS
29
3.4.2 Fringing field effect
The variation or sensitivity of capacitance per unit length to displacement with the
infinite parallel plate model can be calculated as the derivative of capacitance with
respect to lateral displacement. By using the well-known capacitance of infinite parallel
plates, the sensitivity is
dC d   ( w  x) 

  n
  n
dx dx 
g
g

(3.21)
where g is the gap, ε the air permittivity, w the electrode width, and n the number of
parallel capacitors. In actuality, the capacitance displacement sensitivity is lower than in
Eqn. 3.21 due to fringing field capacitance. Eqn. 3.21 does not take into account the
fringing field capacitance, which is much less sensitive to lateral displacement than the
ideal ‘overlap’ capacitance of Eqn. 3.21.
C real  Cideal  C fringing  
nwL
 C fringing
g
(3.22)
Figure 3.12 shows the variation of dimensionless capacitance to lateral displacement for
different gaps for a simple parallel plate geometry.
2 electrodes 1 um width capacitor
dimensionless capacitance
1
0.9
0.8
0.7
gap 0.1 um
gap 0.2 um
gap 0.3 um
gap 0.5um
gap 1 um
gap 2 um
gap 5 um
gap 10 um
gap 100 um
0.6
0.5
0.4
0.3
0.2
0.1
0.5
1
1.5
2
2.5
3
3.5
4
4.5
displacement [um]
Fig 3.12: Dimensionless capacitance ( C(x)/C(x=0)) versus displacement for different gaps. The system
modeled was two parallel plates of 1μm width and negligible thickness.
30
Figure 3.12 shows how capacitance becomes less sensitive to displacement for larger
gaps. Eqn. 3.21 does not hold for large gaps, in which case the fringing field capacitance
is no longer negligible. The percentage of fringing field capacitance to total capacitance
is shown in Figure 3.13 for different gaps.
Fig 3.13: Ratio of fringing field capacitance (Cnumerical-Canalytical) to total capacitance (Cnumerical).
Analytical capacitance is calculated with the ideal parallel plate capacitance equation. Numerical
capacitance is calculated with a FEM simulator and includes both the ideal term and fringing term
of Eqn. 3.22. The system modeled was two parallel plates of 1μm width and negligible thickness.
Although Figure 3.13 shows fringing field for the case of two electrodes capacitor of
Figure 1.4, the results can be extrapolated to the 3 electrode capacitor of Figure 2.1.
When capacitance is dominated by fringing field capacitance, the capacitance sensitivity
to lateral displacement becomes negligible because the fringing effect sensitivity to
lateral displacement is very low. This can be extracted from Figure 3.13 and Figure 3.12.
For 100 μm gap, Figure 3.13 shows that capacitance is mostly made of fringing field
effect. For the same gap, Figure 3.12 shows that this capacitance, which is basically
fringing field, has very little variation with lateral displacement.
According to Figure 3.13, if fringing fields want to be kept under 30% of the total field
when the plates are aligned, the ratio of gap to width should be in the order of 1/3. In this
way, a minimum capacitor displacement sensitivity is guaranteed.
31
3.4.3 Influence of plates conductivity
The influence of the plates’ conductivity was analyzed by using different models that
include the plates as conductors or dielectrics.
-Simplified model, 5 electrodes
To reduce the number of nodes and make the simulations more time efficient, simplified
models with just a small fraction of the plates and reduced number of strips were used.
Figures 3.14-3.16 show the FEM model.
Figure 3.14: FEM model of capacitive sensor
The outer ring with square elements encloses the infinite elements modeling the far-field.
The triangular elements model the surrounding medium, which is air. And the two white
squares are sections of bottom and top plate. Between the two plates, the thin area models
the sensor’s electrodes, air and oxide. Figures 3.15-3.16 focus on this area.
Figure 3.15: Space between plates from Figure 3.14
32
Figure 3.16: Zoom in figure 3.14 showing electrodes, gap air, oxide layers, and plates
Figure 3.16 shows a part of the two plates, the three electrodes that compose the basic
sensor unit, two meshed layers of oxide separating the electrodes and the plates, and the
meshed space between the plates. A description of the model’s geometry is summarized
in Table 3.3.
gap
electrode thickness
width bottom electrodes
width top electrode
thickness oxide layer
thickness Si substrate plates
width plate
spacing between two bottom electrodes
spacing bottom electrode different groups
electrode length
plate lenght
Number of groups
Electrodes per group
Total number of electrodes
0.1 μm
0.1 μm
1 μm
2 μm
0.5 μm
381 μm
500 μm
1 μm
3 μm
500 μm
15 mm
3
3 (2 bottom, 1 top)
9
Table 3.3: model geometry
By changing the relative position of bottom and top plate, the change of capacitance
matrix versus displacement is obtained. Figures 3.17-3.21 show the results obtained. The
code is given in Appendix B.
33
-3
3.5
capacitance simulations g=0.1 um
x 10
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
3
capacitance [pF/um]
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.17: Lumped mutual capacitances per unit length. The electrodes are numbered as in
Figure 2.1 and 3.7
As expected, the largest capacitance is C45, which is the capacitance between the two
plates. Figure 3.18 focuses on the other capacitances.
-4
capacitance simulations g=0.1 um
x 10
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
capacitance [pF/um]
3
2
1
0
-3
-2
-1
0
1
displacement [um]
2
3
Figure 3.18: Lumped mutual capacitances per unit length.
Figure 3.16 shows that the capacitances C13 and C23 change drastically with displacement.
Capacitance C12 can be neglected compared to C13 and C23, in agreement to an
assumption commonly used in differential capacitance sensors [2.1]. However, the rest of
capacitances are in the same order of C13 and C23 and must be taken into account.
Figures 3.19-3.25 show the total capacitance in picoFarads.
34
total capacitance one group g=0.1 um
60
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
capacitance [pF]
50
40
30
20
10
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.19: Lumped mutual capacitances.
total capacitance one group g=0.1 um
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
0.16
0.14
capacitance [pF]
0.12
0.1
0.08
0.06
0.04
0.02
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.20: Lumped mutual capacitances.
Plugging the values from the capacitance matrix in the expression of equivalent input
capacitance deduced in Appendix B, input capacitance versus displacement curves are
obtained. Figures 3.21-3.22 show these results.
35
total capacitance one group g=0.1um
c12
c13
c23
cout
0.16
0.14
capacitance [pF]
0.12
0.1
0.08
0.06
0.04
0.02
0
-3
-2
-1
0
1
displacement [um]
2
3
Figure 3.21: C12, C13, and C23 from the lumped matrix capacitance, and equivalent input capacitance (Cout).
total capacitance one group g=0.1um
c12
c13
c23
cout
0.075
0.07
capacitance [pF]
0.065
0.06
0.055
0.05
0.045
0.04
0.035
-3
-2
-1
0
1
displacement [um]
2
3
Figure 3.22: C13 and C23 from the lumped matrix capacitance, and equivalent input capacitance (Cout).
Scaling up the results obtained with the simplified model, results for a model in scale can
be obtained. Figures 3.23-3.25 show the result of the simplified model scaled-up by
assuming 15 mm x 15 mm plates, and 27 groups of strips, across the 500 μm sensor
width.
36
total capacitance 27 groups g=0.1 um
1400
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
1200
capacitance [pF]
1000
800
600
400
200
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.23: Lumped mutual capacitances.
total capacitance 27 groups g=0.1 um
4.5
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
4
capacitance [pF]
3.5
3
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
Figure 3.24: Lumped mutual capacitances.
total capacitance 27 groups g=0.1um
4.5
c12
c13
c23
cout
4
capacitance [pF]
3.5
3
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.25: C13 and C23 from the lumped matrix capacitance, and equivalent input capacitance (Cout).
37
-Model for large gap and displacement range, 5 electrodes
For larger gaps and displacement ranges, a more precise model was developed. This
model is summarized in Table 3.4.
gap
electrode thickness
width bottom electrodes
width top electrode
thickness oxide layer
thickness Si substrate plates
width plate
spacing between two bottom electrodes
spacing bottom electrode different level 1
spacing bottom electrode different level 2
spacing bottom electrode different level 3
electrode length
plate lenght
Number of electrodes group level 1
Number of groups level 1
Number of groups level 2
Number of groups level 3
Total number of electrodes
20 μm
0.1 μm
1 μm
2 μm
0.5 μm
381 μm
500 μm
1 μm
2 μm
13 μm
65 μm
500 μm
15 mm
3
3
3
3
81
Table 3.4: characteristics model for large gap and deflections
The APDL macro is given in Appendix C. Figures 3.26-3.27 show the meshed model.
Figure 3.26: FEM model of sensor from table 3.4. Detail gap and 9 group of electrodes
38
Figure 3.27: FEM model of sensor from table 3.4. Detail of gap and 3 groups of electrodes
The curves equivalent input capacitance versus displacement are shown in Figure 3.283.29.
-4
1.64
x 10
output capacitance, 3x3x3x3 model, g=20 um
1.63
capacitance [pF/um]
1.62
1.61
1.6
1.59
1.58
1.57
1.56
-100
-80
-60
-40
-20
0
20
displacement [um]
40
60
80
100
Figure 3.28: Input equivalent capacitance per unit length versus displacement
Due to the large number of electrodes, the number of nodes per electrode had to be kept
low to avoid an excessive number of elements in the model. Because of the lower number
of nodes per electrode, the results for different displacements showed less consistency
than in other simulations. Figure 3.29 filters the results to minimize the error.
39
-4
filtered output capacitance, 3x3x3x3 model, g=20 um
x 10
1.62
capacitance [pF/um]
1.61
1.6
1.59
1.58
1.57
-80
-60
-40
-20
0
20
displacement [um]
40
60
80
100
Figure 3.29: Input equivalent capacitance per unit length versus displacement. Results from ANSYS
filtered with MATLAB (MATLAB code given in Appendix D)
-Model for connected plates, 4 electrodes
During the alignment, the nanopositioner may connect electrically both plates. For this
case, a model was developed to obtain the input equivalent capacitance. In this case,
instead of 5 electrodes, there would be 4 electrodes. The equivalent input impedance in
function with the lumped capacitances was obtained as well. Its deduction is given in
Appendix F.
The model has the characteristics given in Table 3.4. The results from the FEM simulator
are shown in Figure 3.30-3.31.
-4
3.5
x 10
substrates wired,three groups, per unit lenght g=0.1 um
c12
c13
c14
c23
c24
c34
3
capacitance [pF/um]
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
Figure 3.30: Lumped capacitance matrix
40
4
-4
3.5
x 10
substrate wired, three groups, per unit lenght, g=0.1um
c12
c13
c23
cout
3
capacitance [pF/um]
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.31: C12, C13, and C23 from lumped capacitance matrix and input equivalent capacitance (cout)
-Model for glass top electrode
Another model was developed to analyze the influence of non-conductive plates. In this
case, the plate on top was modeled as Silicon dioxide. Figures 3.32-3.33 show the model
meshed.
Figure 3.32: Glass top plate meshed model. It can be seen in the figure that the space for the top
plate has been meshed
41
Figure 3.33: Glass top plate meshed model. The detail of the gap shows, from the bottom to the top, air not
meshsed, a layer of silicon dioxed, the electrodes, air between the electrodes, a top electrode, and a large
surface meshed which is the top plate
The results from the model with the characteristics of Table 3.4 are shown in Figure 3.343.35.
Figure 3.34: Lumped capacitance matrix model glass top plate
-4
1.5
three groups, top substrate glass, g=0.1um
x 10
1.4
capacitance [pF/um]
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.35: Input equivalent capacitance model glass top plate
42
-Model for glass top electrode
In Figures 3.36-3.38, simulations for a model with glass bottom plate are shown.
Figure 3.36: Meshed model with glass bottom plate. Meshed model with glass bottom plate.
Detail of gap on the left
-4
3.5
three groups, bottom substrate glass, g=0.1um
x 10
c12
c13
c14
c23
c24
c34
3
capacitance [pF/um]
2.5
2
1.5
1
0.5
0
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.37: Lumped capacitance matrix model glass bottom plate
43
-4
1.4
three groups, bottom substrate glass, g=0.1um
x 10
1.3
capacitance [pF/um]
1.2
1.1
1
0.9
0.8
0.7
0.6
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.38: Input equivalent capacitance model glass bottom plate
-Four models compared
To analyze the influence of the plates in the equivalent input capacitance, the following
figure compares the results from the four models above.
simulations 4 simplified models
2.2
top subs glass
subs wired
bottom subs glass
5 electrodes
2
capacitance [pF]
1.8
1.6
1.4
1.2
1
0.8
-4
-3
-2
-1
0
1
displacement [um]
2
3
4
Figure 3.39: Equivalent input capacitance from models with different plate characteristics.
Although whether the plates are conductive or dielectric has an influence on the
equivalent input capacitance, the sensor would work for all the cases studied.
44
3.5 Convergence
To obtain the optimal mesh in terms of accuracy and computation time, the algorithm
convergence was analyzed. Because the greatest field gradient is at the space between
electrodes 1, 2, and 3 (see Figure 2.1), the mesh must be finer around them. The macros
used for capacitance extraction specify the number of nodes on the surface of electrodes
1, 2, and 3 surfaces, and leave the rest as auto mesh. This results in a much denser mesh
around the electrodes. To find the optimal number of nodes on the electrodes’ surface,
simulations changing the number of nodes were carried out. Figures 3.40-3.41 show a
mesh with 5 nodes per electrode and a mesh with 105 nodes per electrode. The APDL
macro is given in Appendix E.
Figure 3.40: Detail of meshed model with 5 nodes per electrode’s horizontal surface
Figure 3.41: Detail of meshed model with 105 nodes per electrode’s horizontal surface
Figures 3.42-3.44 show the dimensionless lumped matrix capacitance versus the number
of nodes per electrode surface for different gaps.
45
convergency, 3x3 model, g=0.1 um
capacitance(nodes)/capacitance(5 nodes)
1.03
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
cout
1.02
1.01
1
0.99
0.98
0.97
0.96
0.95
0.94
0
20
40
60
80
nodes per surface electrode
100
120
Figure 3.42: Dimensionless lumped matrix capacitance. Gap 0.1 μm.
The capacitance is divided by the capacitance obtained with 5 nodes per electrode surface
convergency, 3x3 model, g=1 um
capacitance(nodes)/capacitance(5 nodes)
1.015
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
cout
1.01
1.005
1
0.995
0.99
0.985
0.98
0
20
40
60
80
nodes per surface electrode
100
120
Figure 3.43: Dimensionless lumped matrix capacitance. Gap 1 μm.
convergency, 3x3 model, g=10 um
capacitance(nodes)/capacitance(5 nodes)
1.004
c12
c13
c14
c15
c23
c24
c25
c34
c35
c45
cout
1.002
1
0.998
0.996
0.994
0.992
0.99
0.988
0.986
0.984
0
20
40
60
80
nodes per surface electrode
100
120
Figure 3.44: Dimensionless lumped matrix capacitance. Gap 10 μm.
46
Figures 3.42--3.44 show that reaching convergence requires less number or nodes for
larger gaps. This was expected, since shorter gaps induce greater potential gradients. A
large gradient leads to greater errors in the integration, so to keep the error low the
number of nodes has to be increased.
Reference:
[3.1] F. Stellari, A. L. Lacaita, ‘New Formulas of Interconnect Capacitances Based on
Results of Conformal Mapping Method’, IEEE Vol. 47, No. 1, January 2000
[3.2] N. D. Arora, K. V. Raol, R. Schumann, L. M. Richardson, ‘Modeling and
Extraction of Interconnect Capacitances for Multilayer VLSI Circuits’, IEEE Vol. 15,
No.1 January 1996.
[3.3] A. Toulouse, D. Bernard, C. Landrault, P. Nouet, ‘Efficient 3D Modelling for
Extraction of Interconnect Capacitance in Deep Submicron Dense Layouts’.
[3.4] U. Choudhury, A. Sangiovanni-Vincentelli, ‘Automatic Generation of Analytical
Models for Interconnect Capacitances’, IEEE 1994.
[3.5] ‘Ansys Low-Frequency Electromagnetic Analysis Guide’, Ansys Release 10.0,
August 2005
[3.6] http://ccrma.stanford.edu/~jos/NumericalInt/Lumped_vs_Distributed_Systems.html
[3.7] A. Hieke, ‘Simple APDL implementation of a 3D FEM simulator for mutual
capacitances of arbitrarily shaped objects like interconnects’, SIEMENS Microelectronics,
c/o IBM Semiconductor Research & Development Center.
[3.8] J, W. Nilsson, ‘Electric Circuits’, Addison-Wesley Publishing Company, Fourth
Edition.
47
4. Capacitance-to-voltage converters
4.1 Introduction
In chapter 2 the sensor was modeled by a lumped capacitor connected to a circuit. To
measure the impedance of a capacitor, an excitation is applied to one of the terminals, as
illustrated in Figure 4.1
Figure 4.1: Capacitance in function with displacement and voltage supplied
The output current through the capacitor is the derivative of stored charge with respect to
time. By using the definition of capacitance C=Q/V, and the definition of current i=dQ/dt,
the following expression is obtained
iC 
dQ
dV
C 
C
V
dt
dt
 t
(4.1)
where V is the voltage applied, and δ the displacement. Assuming that the excitation
voltage is a sinusoidal function whose frequency is much higher that the rate of
capacitance change with displacement, Eqn. (4.1) is simplified to
iC  C
dV
d
 C  A sin( t )   CA cos(t )
dt
dt
48
(4.2)
where A is the applied voltage amplitude, and ω the frequency. According to Eqn. (4.2), a
capacitor with a sinusoidal voltage excitation can be modeled as a sinusoidal current
source modulated by the capacitance itself. This description can easily be extended to any
periodic excitation as long as the excitation frequency is much larger than the variation of
capacitance over time.
4.2 Converters
A converter is an electrical circuit aimed at transforming an electrical signal to another
more convenient electrical signal. As explained in Section 4.1, the output of a capacitor is
a periodic current modulated by the capacitance. To electrically process this signal, it
must be converted to a different electrical signal easier to process, such as a bias voltage
linear with the capacitance or a digital signal.
Because the purpose of a capacitance-to-voltage converter is to detect changes in
capacitance, the performance will be mainly evaluated by the circuit’s ability to read the
minimum possible change in capacitance, which is limited by the circuit’s noise. The
root-mean-square (RMS) of a circuit’s noise waveform vn(t) is defined as [4.13]
tˆ / 2
v n rms  v  lim
ˆ
2
n
t 
 (v
n
(t )) 2 dt
(4.5)
tˆ / 2
Similar to the definition of RMS voltage noise, the RMS minimum detectable
capacitance is defined as [4.14]
C min rms 
vnrms
dvo / d (C )
49
(4.6)
where vo is the output voltage and ΔC is a change in the capacitance to measure over the
initial capacitance.
Extensive literature research on capacitance converters was carried out during this project
to obtain a wide understanding of the different approaches and select the best readout
circuit. The most common converters are described and analyzed throughout the
following sections.
4.3 Oscillators
Capacitance-controlled oscillators have been widely analyzed in the instrumentation
literature. However, currently other types of converters are replacing this technique. A
capacitance-controlled oscillator is based on an oscillator whose time period is modulated
by a capacitance. A modification of Martin oscillator is shown in Figure 4.2 [4.2]
Figure 4.2: Modified Martin oscillator for multielectrode capacitive sensors [4.2].
The period of the circuit in Figure 4.2 is
T=4R(Coffset-Cos+Cx,i)
(4.5)
which is proportional to the sensor capacitance Cx,i. Although large accuracy and linearity
can be achieved with this technique, the output would require complex signal processing.
Furthermore, the oscillator performance is highly dependant on parasitic capacitances.
50
4.4 Capacitive bridge
Capacitive bridges are based on the well-known Wheatstone bridge [4.3]. A possible
implementation is shown in the Figure 4.3.
Figure 4.3: Capacitive bridge
The output voltage of such circuit is
Vo  V
C1  C 2
Cf
(4.6)
In the scheme of Figure 4.3, the capacitance C1 and would be replaced by the sensor
equivalent capacitance, and C2 by a reference capacitor. The main disadvantage of this
circuit is its high sensitivity to parasitic capacitances.
4.5 Transimpedance amplifier
4.5.1 Gain and noise
The transimpedance amplifier, or charge amplifier, is basically a current to voltage
converter, i.e. a circuit that converts a current modulated signal to a voltage modulated
signal. The following figure shows the schematic of such circuit, modeling the capacitor
and its voltage supply as a current source
51
Figure 4.4: Transimpedance amplifier
The output voltage of the circuit is
Vo = -Rf Is
(4.7)
Modifying the circuit of Figure 4.4 for differential input, and including parasitic
capacitances, the circuit results in that shown in Figure 4.5
Figure 4.5: Transimpedance amplifier, sensor capacitance, and excitation. Cref can be used to cancel an
offset of Cs. Assuming that Cs=Coff+ΔC, if Cref=Coff, the circuit will only measure ΔC.
where Cr is a reference capacitance, and Cp models any parasitic capacitance at the
inverting input of the op-amp. Applying Eqn. (4.7), the output of this circuit is
│Vo│=2 π fdrive Vs Rf ΔC
(4.8)
being Vs the input voltage amplitude, fdrive the input excitation frequency, Rf the feedback
resistor, and ΔC the change in capacitance over Cs. The feedback resistor, with the
parasitic and sensor capacitance, creates a low pass filter, which limits the bandwidth.
The pole of this filter is [4.6]
f pole 
1
1
2 R f (2C s  C p )
52
(4.9)
The optimal circuit performance is obtained at resonance frequency, which is given by
the pole frequency given in Eqn. (4.9) and the amplifier gain bandwidth. Therefore, the
optimal drive frequency is
f driveopt  GBWamp
1
2R f (2C s  C p )
(4.10)
where GBWamp is the amplifier gain bandwidth. By substituting Eqn. (4.10) in Eqn. (4.8),
the output voltage for an optimal drive frequency is obtained
Vo 
2 (GBWamp ) R f
(2C s  C p )
Vm (C )
(4.11)
The amplifier noise can be modeled by ideal components and current/voltage sources
dependent on noise. The following circuit shows the amplifier with ideal components and
the noise sources.
Figure 4.6: Transimpedance amplifier with noise sources
By applying superposition, the output voltage noise is
v n ,rms  en  ( R f in ) 2  4 K B TR f  4 K B TR f
2
(4.12)
The approximation of Eqn. 4.12 assumes that an optimal ultra-low noise op-amp is used,
so that the feedback resistor is the dominant noise source. The minimum detectable
capacitance as defined in Eqn. 4.6 is:
53
C min rms 
2 K BT (2C s  C p )
1
Vm
 (GBWamp )
BW
(4.13)
Even though the feedback resistor is the main source of error, the minimum capacitance
detectable does not depend on the feedback resistor value. While the feedback resistor
increases the noise linearly with its resistance value, the capacitance measurement is also
amplified linearly with the feedback resistance. Therefore the feedback resistance value is
cancelled out for the signal to noise ratio, and the minimum capacitance detectable
becomes independent of the feedback resistance. Figures 4.7-4.8 show the minimum
detectable capacitance for different cases.
minimum
detectable capacitance transimpedance amplifier
-3
1.5
x 10
Cmin-rms [aF/sqrt(BW)]
1.45
1.4
1.35
1.3
1.25
1.2
1.15
1.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
parasitic capacitance [pF]
Figure 4.7: Minimum detectable capacitance by transimpedance
amplifier assuming Vm=1V, T=300 K, GBWamp=1 MHz, Cs=1pF
54
minimum detectable capacitance transimpedance amplifier
3
10
Csensor=1nF
Csensor=1pF
Csensor=1fF
2
Cmin-rms [aF]
10
1
10
0
10
-1
10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
parasitic capacitance/sensor capacitance
Figure 4.8: Minimum detectable capacitance by transimpedance
amplifier assuming Vm=1V, T=300 K, GBWamp=1 MHz, BW=100 KHz.
4.5.2 Stability
The amplifier model of Figure 4.4 assumes no parasitic capacitances and infinite
resistance. A more realistic model is shown in Figure 4.9.
Figure 4.9: Transimpedance amplifier with parasitic capacitance Cs and sensor finite resistance Rs
Cs introduces two drawbacks in the circuit. First, as the frequency increases, the
impedance of Cs decreases. Therefore, at high frequencies Cs acts as a short circuit, and
so the current from the source Is flows through Cs instead of through Rf. This leads to a
reduction of bandwidth. Second, Rf and Cs create a low pass filter, which introduces
negative phase into the system and reduces the bandwidth. Figures 4.10-4.11 show the
55
frequency and time response of the circuit in Figure 4.9 under different stray capacitances
Cs.
Figure 4.10: Output voltage Vo for Cs=0, Cs=50 pF, and Cs=200 pF.
Figure 4.11: Frequency response for Cs=0, Cs=50 pF, and Cs=200 pF.
Figure 4.10 shows how the output voltage oscillation increases with larger values of stray
capacitance. The reduction of bandwidth due to stray capacitance is illustrated in Figure
4.11. To improve the stability, a resistance is included in parallel in the feedback as in
Figure 4.12.
56
Figure 4.12: Transimpedance amplifier with capacitive feedback to improve stability. The values used for
the simulations are indicated in the figure
The feedback capacitor Cf creates a high pass filter with Rs, which adds positive phase to
the system and pushes the circuit into stability. Figure 4.13 shows simulation of the
circuit in Figure 4.12 under different values of Cf.
Figure 4.13: Simulations circuit Figure 4.12 for Cf= 0, Cf=2 pF, Cf=4 pF
The drawback of this approach is the reduction of bandwidth due to the low pass filter
composed by Cf and Rf..
57
Figure 4.14: Frequency response simulations circuit Figure 4.12 for Cf= 0, Cf=2 pF, Cf=4 pF
4.5.3 Synchronous demodulator
The outputs of the transimpedance amplifier and capacitive bridge are both sinusoidal
voltages modulated by the sensor capacitance. To convert this signal to a more
convenient DC signal proportional to the capacitance, a synchronous demodulator can be
used. This circuit ideally implements the following equations
Vo = Vin if Vin>0
Vo= -Vin if Vin<0
(4.14)
The following figure shows the diagram of this circuit
Figure 4.15: synchronous demodulator circuit. An amplifier obtains the negative of the input signal. A
periodic excitation, usually a square wave, controls two switches that close and open at opposite times.
58
An accurate and flexible converter can be implemented by applying a high frequency
voltage to the unknown impedance and another known reference capacitance, amplifying
the signal, applying it to a demodulator, and low-pass filtering it. A scheme is shown in
the Figure.
Figure 4.16: capacitance to voltage converter based on synchronous demodulation
The following figure shows the output waveform of the different blocks
Figure 4.17: output waveforms from the different blocks of a capacitance to voltage amplifier.
From left to right, amplifier, synchronous demodulator, and low-pass filter
4.6 Switched-capacitor Converter
4.6.1 Switched-capacitor Amplifier
Switched-capacitor circuits are based on replacing resistances by capacitors and switches.
Figure 4.17 shows a simple circuit with a resistance
59
Figure 4.18: circuit with resistance
The current flowing through the resistor is
I=R1(V2-V1)
(4.15)
If the resistor is replaced by a capacitor and two switches, the circuit in figure 4.19 is
obtained
Figure 4.19: Circuit with switched-capacitor equivalent resistance
The switches are controlled by two non-overlapping complementary clocks like in Figure
4.20.
phi1
t
phi2
t
Figure 4.20: Non-overlapping clocks
When clock φ1 is high, the capacitor charges up to V1, whereas when φ2 is high, the
capacitor charges/discharges up to V2. Therefore, from one phase to the next one there is
a transfer of charge of
60
Q = C (V1 – V2)
(4.16)
With a switch rate fclk, the amount of current transferred per unit time is
Q fclk = C fclk (V1 – V2)
(4.17)
Eqn. 4.17 has the unit of currents, so that an average current can be defined as
Iavg = C fclk (V1-V2)
(4.18)
Assuming that the clock frequency is much higher than the voltage waveforms frequency,
the switches and capacitor can be modeled as an equivalent resistance [4.4]
Req 
V1  V2
1

I avg
Cf clk
(4.19)
Based on Eqn. 4.19, an inverting amplifier with capacitors instead of resistors can be
implemented. In principle, an inverting amplifier implemented with capacitances would
not provide a dc bias for the op-amp input. This is shown in Figure 4.21.
Figure 4.21: Inverting amplifier with capacitive feedback. This configuration does not provide
dc bias at the op-amp input
However, by using switches to control the charge transfer of the capacitors, a dc path can
be provided [4.5]. The following figure shows a schematic of such a circuit
61
Figure 4.22: Switched-capacitor integrator
Circuit in Figure 4.21 can be modeled as an integrator if C1 and the switches are replaced
by the equivalent resistor by using Eqn. 4.19. Two phases can be identified in this circuit.
During the sample phase φ1 is high and its switch is closed, while φ2 is low and its switch
open. Therefore the charge stored in the capacitors during this phase is
Qsample = (0-Vs)C1 + (0-0)C2
(4.20)
During the transfer phase φ2 is high and φ1 is low, so that the charge stored is
Qtransfer = (0-0)C1 + (0-Vo)C2
(4.21)
By conservation of charge, Eqns. 4.20 and 4.21 must be equal. Therefore
Vo C1

Vs C 2
(4.22)
4.6.2 Parasitic capacitances
In the circuit of Figure 4.22, the main source of parasitic capacitance appears from the
switch nodes to ground. This circuit can be modified to become more insensible to
parasitics by arranging the switches in a way that the sensor capacitor Cs is never in
parallel with the parasitic capacitance [4.7]. This is shown in Figure 4.23.
62
Figure 4.23: Inverting switched-capacitor parasitic insensitive amplifier
Adding a parasitic capacitance at the input of the op-amp Cp, and assuming a non-infinite
op-amp gain a, the amplifier gain is [4.5]


Vo C1 
1

Vs C 2  1  C1  C 2  C p
1  
C2
 a 




 
 
(4.23)
The amplifier gain, as Eqn. 4.23 shows, is parasitic insensitive to an extent that depends
on the op-amp closed-loop gain.
4.6.3 Correlated Double Sampling
The main function of the op-amp in the circuit of Figure 4.23 is, by means of a closedloop feedback, to create a virtual ground at the input without sinking any current.
However, due to op-amp non-idealities, this voltage is larger than zero. The main nonideal effects are noise (mainly 1/f noise and thermal noise), and dc offset voltage. Two
basic techniques are mainly used to attenuate such non-idealities, known as autozeroing
(AZ) and chopper stabilization (CHS) [4.8]
Chopper stabilization technique attenuates 1/f noise by transposing the signal to a higher
frequency where there is almost no 1/f noise. At a higher frequency, it amplifies the
63
signal and demodulates it back to the original baseband. This technique is well suited in
continuous systems, but more difficult to implement for sequential.
Autozeroing (AZ) operates sequentially. During a first phase it disconnects the amplifier
from the signal path, and samples and stores the unwanted quantities. i.e. the offset and
1/f noise, forcing the output voltage to a small value. Then, the offset-free op-amp is
connected back to the signal source for amplification. Therefore any noise constant over
time (like dc offset or low frequency 1/f noise) is in principal cancelled.
AZ requires the amplifier to be disconnected during the sample phase, so that the signal is
only available for amplification during the second phase. Although this requirement
would make it incompatible for a continuous system, it is easily suited in a switchedcapacitor circuit. Correlated Double Sampling takes advantage of the switched-capacitor
transfer phase to perform an AZ phase when the voltages are held. Therefore in one
period, sampling is performed twice, a first one to obtain the unwanted part of the signal,
and a second to sample the complete signal. An efficient implementation of CDS is
known as Gregorian SCA [4.9], whose schematic is shown in Figure 4.24.
Figure 4.24: Gregorian switched-capacitor amplifier
64
The op-amp offset, modeled as a voltage source Vos, is sampled with C1 and C2 in one
phase and subtracted in the next one from the signal [4.10].
Figure 4.23 shows the designed amplifier suitable for this project. This circuit is based on
the Gregorian amplifier shown in Figure 4.19 with some modification to adapt it to the
purpose of the capacitive sensor. To avoid voltage ‘sparks’ at the output when both
clocks are down and the op-amp is in open loop, the Gregorian amplifier was modified by
placing a small capacitance between input and output [4.11], as shown in Figure 4.25.
Figure 4.25: SC amplifier based on the Gregorian amplifier, with CDS and ‘anti-spike’ capacitor Cdg.
The circuit of Figure 4.25 is composed of five switches, which could be MOSFETs, a
constant voltage source, an operational amplifier, the sensor capacitance Cs, the antispike capacitor Cdg, the feedback capacitor Cf, and two nonoverlaping clock signals φ1
and φ2, whose clock circuits are not shown in the schematic. Voffset models nonidealities
from the operational amplifier. To analyze this circuit, the two different phases will be
studied independently. During the sampling phase (φ1 high and φ2 low), the circuit can be
simplified to the circuit in Figure 4.26.
65
Figure 4.26: Simplified converter during sampling phase
Assuming that the capacitance of both differential capacitors changes from C to C+ΔC
and C-ΔC, the charge stored in the capacitors is:
Q1 = (C+ΔC)(Vin-Vos)+(C-ΔC)(-Vin-Vos)+Cf(0-Vos)
(4.24)
During the charge transfer phase, the circuit can be simplified to circuit in Figure 4.27.
Figure 4.27: Simplified Gregorian amplifier during charge transfer phase
The charge storage during this phase is
Q2 = (C+ΔC)(0-Vos)+(C-ΔC)(0-Vos)+Cf(Vout-Vos)
(4.25)
Applying conservation of charge, the offset voltage Vos is cancelled out in both Eqn. 4.24
and 4.25, and the output voltage is obtained as function of the change in capacitance ΔC
Vout 
66
C
Vin
Cf
(4.26)
4.6.4 Bandwidth
The transfer of charge of Eqn. 4.21 assumes infinite op-amp gain and no parasitic
capacitances. Including terms for both nonidealities, the equation becomes
 V 
 V 
 V

Q2    o C1    o C p    o  Vo C 2
 A
 A
 A

(4.27)
The circuit gain with parasitic capacitance and finite gain A is


Vo C1 
1


Vs C 2
1  1  C1  C 2  C p

A 
Cp









(4.28)
Assuming an op-amp with a single pole response
A( s ) 
Ao s o
Ao

s
s  so
1
so
(4.29)
Substituting the op-amp gain into the amplifier gain


Vo C1 
Ao s o


Vs C 2 
 C1  C p
1 
A
s

(
s

s
)
o
o
o

C2






 C1  K 



  C2  1  s 
p





(4.30)
where
K
Ao 
Ao
C1  C 2  C p
C2
67
(4.31)
Ao s o 
p
C1  C 2  C p
C2
C1  C 2  C p
so
(4.32)
C2
K can be simplified to one assuming that the op-amp open loop gain Ao is much larger
than the ratio of capacitances (C1+C2+Cp)/C2. Under the same assumption, Eqn. (4.32)
shows that the closed-loop bandwidth is Ao times larger than the open-loop bandwidth.
This means that the product gain-bandwidth is constant for a given op-amp. This is
shown in Figures 4.28-4.29
Bode Diagram
0
Magnitude (dB)
-10
-20
-30
-40
-50
Ao=1e3, Cp=Cf/10
Ao=1e3, Cp=Cf
Ao=1e3, Cp=Cf*10
Ao=1e5, Cp=Cf/10
Ao=1e5, Cp=Cf
Ao=1e5, Cp=Cf*10
Phase (deg)
-60
0
-45
-90
9
10
10
10
11
10
12
10
13
10
14
10
15
10
Frequency (rad/sec)
Figure 4.28: Closed-loop frequency response of Gregorian converter for different
op-amp open-loop gains (Ao) and different parasitic capacitances (Cp)
68
Bode Diagram
Magnitude (dB)
0
-0.05
-0.1
Phase (deg)
0
Ao=1e3, Cp=Cf/10
Ao=1e3, Cp=Cf
Ao=1e3, Cp=Cf*10
Ao=1e5, Cp=Cf/10
Ao=1e5, Cp=Cf
Ao=1e5, Cp=Cf*10
-45
-90
9
10
10
11
10
12
10
10
13
10
Frequency (rad/sec)
Figure 4.29: Closed-loop frequency response of Gregorian converter for different op-amp open-loop gains
(Ao) and different parasitic capacitances (Cp). Zoom at lower frequencies
From Figure 4.28 it can be extracted that the amplifier is more sensitive to parasitics for
lower open-loop op-amp gains. The closed-loop gain remains constant at low frequencies
with different parasitic capacitances values for a high open-loop op-amp gain. However,
for a low open-loop op-amp gain, both the bandwidth and the closed-loop gain
performance decrease at high frequencies.
4.6.5 Noise analysis
The switched-capacitor amplifier has two dominant sources of error. The input referred
KT/C noise is given by the following expression
2
v KT
/ C ,input 
KT
CT
CT = CS + Cf + Cp + CGS
69
(4.33)
(4.34)
where K is the Boltzmann constant, T temperature, and CT is the sum of the feedback
capacitance Cf, sensor capacitance Cs and parasitic capacitance Cp, and the gate
capacitance of the input stage of the op-amp. The output referred KT/C noise is
v
2
KT / C
C
 T
C
 f
2
 KT

 C
 T
(4.35)
The thermal noise is given by the voltage op-amp noise vn2 . The output referred thermal
noise is [4.14]
v
2
opamp
C
 T
C
 f
2
 2 GBW amp 
 vn

fs
2

(4.36)
where GBWamp is the amplifier gain bandwidth, and fs is the sampling frequent. As
explained, the CDS technique cancels out any noise that is constant over a longer period
than the sampling time. Therefore, KT/C noise and offset are removed. With these noise
sources removed, the amplifier thermal noise becomes the dominating noise source.
Using the gain given by Eqn. (4.26) and the noise from Eqns. (4.35) and (4.36) above, the
minimum detectable signal without CDS is
C min  rms
1

Vin
2 2
KTCT CT v n (GBWamp )( 2)

BW
fs
fs
(4.37)
while the noise with CDS applied is
C min  rms CDS
1

Vin
CT2 v n2 (GBWamp )
fs
70
BW
(4.38)
CDS removes the term due to KT/C noise. However, the thermal noise is twice as large
due to the double sampling. Figure 4.30 shows the performance under different sampling
frequencies
minimum detectable capacitance variation
Cmin-rms [aF/sqrt(BW)]
0.25
SC fs=0.1 MHz
SC CDS fs=0.1MHz
SC fs=1MHz
SC CDS fs=1MHz
0.2
0.15
0.1
0.05
0
0
2
4
6
8
10
12
14
16
18
20
Parasitic Capacitance [pF]
Figure 4.30: Performance of switched-capacitor with and without correlated double sampling for 0.1 MHz
and 1 MHZ sampling frequency. Sensor capacitance 1 pF, amplifier gain bandwidth 2 MHz.
Figure 4.31 compares the performance of the transimpedance amplifier and the switchedcapacitor amplifier
minimum detectable capacitance variation
0.12
switched-capacitor Cs=1pF
switched-capacitor CDS Cs=1pF
transimpedance amplifier Cs=1pF
switched-capacitor Cs=1fF
switched-capacitor CDS Cs=1fF
transimpedance amplifier Cs=1fF
Cmin-rms [aF/sqrt(BW)]
0.1
0.08
0.06
0.04
0.02
0
0
2
4
6
8
10
12
14
16
18
20
Parasitic Capacitance [pF]
Figure 4.31: Minimum readable capacitance of switched-capacitor, switched-capacitor with CDS, and
transimpedance amplifier. Amplifier gain bandwidth 1 MHz, sampling frequency 0.5 MHz
71
4.6.6 Simulations
Since the sensor capacitance swings within a wide range, the converter of Figure 4.24
with fixed components values may not be appropriate for the complete sensor capacitance
range. Assuming a fixed voltage supply of ±5 volts, which is a typical value for most
low-noise op-amps [4.19], the feedback capacitor value Cf is a trade-off between
capacitance range and accuracy. According to the noise model given by Eqn. 4.38, a
smaller feedback capacitor results in lower minimum detectable capacitance. However, a
smaller feedback capacitor also results in larger output voltage, since the output is given
by the following equation
Vout  Vb
C
Cf
(4.39)
Therefore, Cf may have to be changed to obtain an optimal Vout according to Eqn. (4.39).
The minimum detectable capacitance can be calculated with the model of Eqn. (4.38)
assuming typical values for the amplifier gain bandwidth (GBW), signal bandwidth (BW),
sampling frequency, and capacitances.
C min rms / BW 
1 (2 pF  15 pF  20 pF ) 2 (10MHz )
 0.041477aF / Hz
5
1MHz
(4.40)
This means that for a bandwidth of, say 1KHz, the minimum change in capacitance that
the circuit could read would be as small as:
C min  0.04
aF
Hz
14 KHz  4.9aF
(4.41)
The circuit of Figure 4.24 was simulated with SPICE. Figures 4.32-4.33 show the input
capacitances and the output voltage. The code is given in appendix G.
72
Figure 4.32: Voltage of voltage controlled capacitance (Vcap, red line), and output voltage from circuit in
Figure 4.24 (Vout, blue line). The sensor capacitance (Cs) value is given as C=Vcap*10-9
Figure 4.33: Zoom in from Figure 4.27. Voltage of voltage controlled capacitance (red line), and output
voltage (blue line) circuit Figure 4.20.
A continuous RC low-pass filter (LPF) can be used to obtain a DC voltage proportional
to the change of capacitance as in the following figure.
Figure 4.34: RC low-pass filter
73
A LPF filters higher frequencies than the cutoff frequency and passes lower frequency,
which results to an output proportional to the input average. The selection of values for R
and C depends on the rate of change of capacitance. Figure 4.35 shows Vout from Figure
4.28 filtered by the RC-LPF of Figure 4.34 for C=1 nF and three different values for R.
The hspice code is given in appendix G.
Figure 4.35: output from 4.27 filtered with RC LPF versus time for different values of R. C=1 nF
The ‘antispike’ capacitor Cdg value is a trade-off between losing gain for large Cdg and
loosing stability for small Cdg. The simulations in Figure 4.36 show the same output of
Figure 4.32 with the same circuit but different values for Cdg
Figure 4.36: Output voltage converter versus time with Cdg = 1μF. The gain highly decreases
74
Figure 4.37: Output voltage converter versus time with Cdg = 0.1nF.
Voltage spikes would lead circuit to instability.
4.7 Sigma-Delta modulators
Sigma-Delta modulation is a widely used technique in Signal Conditioning. Extensive
literature has been published on the topic. For the sake of clarity, only an overview is
given here.
A Sigma-Delta modulator converts a signal from analogical to digital. General Analogto-Digital Converters are based on a sampling and quantization process as shown in
Figure 4.38
Figure 4.38: General Analog-to-Digital Conversion Process [4.20]. The figure on the left shows the block
diagram, and the figure on the right shows the relation between the discrete-time signal x*(t) and digital
signal x(n), which is represented by the multilevel quantization block on the left.
75
Delta modulation, instead, is based on quantizing the change in the signal from sample to
sample rather than the absolute value of the signal at each sample, as shown in Figure
4.39
Figure 4.39: Delta modulation [4.20]. The output signal is integrated to obtain an average or expected
output, and then subtracted from the input analog signal so that the input to the quantizer is the difference
between the expected value and the input.
Sigma-Delta modulation is based on Delta modulation-demodulation. Demodulating a
modulated signal is done by integrating and lowpass-filtering the output from modulation.
Figure 4.40: Delta modulation and demodulation [4.20].
When demodulation is implemented after modulation, because the integration is a linear
operation, the integrator of demodulation can be moved and implemented before the
modulation without altering the output. Furthermore, the two integrators can be combined
and placed before the quantizer, which gives block diagram in Figure 4.41.
76
Figure 4.41: Block diagram of Sigma-Delta Modulation based on Delta Modulation-Demodulation.
In fact, the name Sigma-Delta Modulation is due to the fact that there is an integrator (Sigma)
before Delta Modulation. The integrator highpass-filters the quantization noise and pushes it to a
higher frequency.
With the block diagram of figure 4.41, a first-order oversampled Sigma-Delta A/D
converter can easily be implemented by changing the lowpass filter with a digital
decimation filter.
Figure 4.42: Block diagram of First-Order Sigma-Delta A/D Converter. Using this technique
Capacitance-to-Digital converters can be implemented based on Sigma-Delta modulation.
There is extensive literature on this topic, including the implemention techniques such as
switched-capacitor, bandpass, and correlated double sampling [4.20-4.23]. Figure 4.43
shows the implementation of switched-capacitor Sigma-Delta modulator that can be used
as capacitive sensor interface [4.23]
Figure 4.43: Switched-capacitor Sigma-Delta modulator. By replacing Cin by the capacitance to sense, the
output produces a digital signal proportional to the sensor capacitor [4.23]
77
References:
[4.1] Guru and Hiziro, ‘Electromagnetic Field Theory Fundamentals’
[4.2] F. N. Toth, Gerard Meijer, Harry Kerkvliet, ‘A Very Accurate Measurement system
for Multielectrode Capacitive Sensors’, IEEE, Vol. 45, No. 2, April 1996
[4.3] L. K. Baxter, ‘Capacitive Sensors, Design and Applications’, IEEE Press
[4.4] W. R Grise, ‘Applications of Switched-Capacitor Circuits in Active Filters and
Instrumentation Amplifiers’, the Technology Interface, Vol 3 No 3, Fall 1999
[4.5] Gray, Hurst, Lewis, Meyer, ‘Analysis and Design of Analog Integrated Circuits’,
Wiley, fourth edition.
[4.6] N. Yazdi, H. Kulah, K. Najafi, ‘Precision Readout Circuits for Capacitive
Microaccelerometers’, University of Michigan, Ann Arbor, MI, USA
[4.7] www.ecircuitcenter.com
[4.8] Ch. C. Enz, G. C. Temes, ‘Circuit Techniques for Reducing the Effects of Op-Amp
Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization’,
IEEE Vol. 84, No 11, November 1996
[4.9]
R.
Gregorian,
‘High
Resolution
Switched-Capacitor
D/A
Converter’,
Microelectronics J., Vol 12, No. 2, pp 10-13, 1981
[4.10] D. J. Willis, R. J. Jost, ‘Zero CVF Input Current Switched-Capacitor
Instrumentation Amplifier’, IEEE 2005
[4.11] H. Matsumoto, K. Watanabe, ‘Spike-free SC circuits’, Electronic Letters, vol. 8,
1987
78
[4.12] N. Wonkgomet, B. E. Boser, “Correlated Double Sampling in Capacitive Position
Sensing Circuits for Micromachined Applications”, 1998 IEEE
[4.13] S. D. Senturia, ‘Microsystem Design’, Kluwer Academic Publishers.
[4.14] N. Wongkomet, ‘Position Sensing for Electrostatic Micropositioners’, PhD
dissertation, University of California, Berkeley.
[4.15] J. Wu, G. K. Fedder, L. R. Carley, ‘A Low-Noise Low-Offset Chopper-Stabilized
Capacitive-Readout Amplifier for CMOS MEMS Accelerometers’, 2002 IEEE
International Solid-State Circuits Conference.
[4.16] J. Wu, G. K. Fedder, L. R. Carley, ‘A Low Noise Low Offset Capacitive Sensing
Amplifier for a 50-μg/Hz-1/2 Monolithic CMOS MEMS Accelerometer’, 2004 IEEE.
[4.17] H., Luo, G. Fedder, L. R. Carley, ‘Integrated Multiple-Device IMU System with
Continuos-Time Sensing Circuitry’, ECE Dept. Carnegie Mellon University, Pittsburgh,
PA.
[4.18] J. Chae, H. Kulah, K. Najafi, ‘An In-Plane High Sensitivity, Low-Noise Micro-g
Silicon Accelerometer with CMOS Readout Circuitry’, 2004 IEEE, Vol 13, No 4
[4.19] www.analog.com
[4.20] S. Park, ‘Principles of Sigma-Delta Modulation for Analog-to-Digital Converters’,
Motorola.
[4.21] N. A. Fraser, B. Nowrouzian, ‘A Novel highly Stable Hihg-Resolution
Oversampled Sigma-Delta A/D Converter Configuration’, ECE, University of Alberta,
Canada.
[4.22] M. Saukoski, L. Aaltonen, T. Salo, K. Halonen, ‘Readout Electronics With
Bandpass Delta-Sigma A/D Converter for a Bulk Micromachined Capacitive Gyroscope’,
79
Electronic, Circuit Design Laboratory, Helsinki University of Technology, Finland.
[4.23] J. O’Dowd, A. Callanan, G. Banarie, E. Company-Bosch, ‘Capacitive sensor
interfacing using sigma-delta techniques’, IAC group, Analog Devices BV, Limerick,
Ireland.
80
5. Experimental verification
5.1 Scaled models
The sensor studied in this project is meant to be fabricated by optical lithography, which
would result in a minimum feature size of approximately 1 μm. Assuming that the sensor
was used for 15x15 mm2 chips, a reasonable maximum sensor size would be 0.5 x 0.5
mm2. To test the resolution of such a sensor, a nanopositioner as shown in Fig. 1.1 would
need to be used as actuator. Nevertheless, a ‘scaled’ sensor, acting in the micrometer
range instead of the nanometer range, would simply need a microactuator, which is more
often available at any microfabrication lab. In fact, with a scaled model a simple
mechanical micropositioner can be used, which highly reduces the set-up complexity and
cost. According to the infinite plate capacitance model, scaling-up both width and gap by
the factor does not change the capacitance per unit length. This is shown in the following
equations.
C
w
( wk )
 n  n
L
g
( gk )
(5.1)
where C is capacitance, L capacitor length, n number of strips, ε the medium electrical
permittivity, w the strip width, g the gap between strips, and k a real constant.
As shown in Eqn. 5.1 if gap, width, and length are scaled, the resultant capacitance would
be proportional to the original one. This is expressed in the following equation.
C l ( w' , g ' , n' )  C l ( w, g , n)
81
n
n'
(5.2)
where Cl is capacitance per unit length. The sensor accuracy, i.e. the minimum detectable
displacement variation, can also be estimated by manipulating simple linear equations.
The minimum detectable displacement can be expressed as
x min 
dC
C min
dx
(5.3)
ΔCmin is defined in Eqn 4.6 and does not depend on the sensor geometry. In the case of
two parallel plates, the derivative of capacitance C with respect to lateral displacement x
is
dC d 
w x
1
  nL
  nL
dx dx 
g 
g
(5.4)
From Eqn 5.4 it can be extracted that for parallel plates the capacitance sensitivity to
displacement scales proportional to length, number of strips, and inverse of gap.
dC
dC
L n g'
( w' , n' , L' , g ' ) 
( w, n, L, g )
dx
dx
L ' n' g
(5.5)
In the case of 5 electrodes, the output capacitance function with displacement is more
complex to handle algebraically. To be able to obtain a simpler analytical expression, the
system of 5 electrodes can be simplified to capacitances C12 and C13. With such
simplification, the total output capacitance is expressed as
Cout  f (Ciji , j 1..5 ) 
C13C12
C12  C13
(5.6)
To calculate C13 and C12 as function of displacement x, the scheme in Figure 5.1 is used.
82
Figure 5.1: geometry used for capacitance analysis. Only the capacitances C 12 and C13 are considered
According to the sign and geometry criteria used in Fig 5.1, Eqn 5.6 can be expressed as
C out 
C13C12
C13  C12
w2
w
w
 x 2  wx 
x  x
4
nL 2
nL
2


w
g w
g
w
x  x
2
2
(5.7)
Eqn 5.6 hold as long as –w/2<x<w/2. The derivative of capacitance with respect to
displacement is
dC out nL  2 x

1
dx
g
w
(5.8)
Because the sensor aims at aligning at the center, i.e. when x equals 0, to obtain the
minimum displacement Eqn 5.8 is evaluated at x=0
dC out ( x  0) nL

dx
g
(5.9)
Eqn 5.9 gives the same result than Eqn 5.4.Therefore, for both 3 plate capacitor and 2
plate capacitor, the minimum detectable lateral displacement is
x min 
g
C min
nL
(5.10)
Obtained the accuracy of a sensor, the accuracy of a scaled version of the same sensor
can be estimated as
83
xmin ( w' , L' , g ' , n' )  xmin ( w, L, g , n)
g' L n
g L ' n'
(5.11)
Interesting consequences can be extracted from Eqn 5.10. According to this result, the
sensor accuracy is independent of electrode width, and varies proportional to the inverse
of the number of electrodes. This means that a large number of thin electrodes result in
greater sensor accuracy and one wide electrode. This makes sense with the approach
commonly used in capacitive sensors as shown in Figure 1.5.
A simple means of creating a scaled model for the sensor is by designing a printed circuit
board whose traces on one face are routed as the sensor electrodes; the board dielectric
would be equivalent to the chip oxide, and a layer of metal on the other face of the board
would be the conductive substrate.
5.2 Setup
The actuator used for the experimental verification, as shown in Figure 5.1, has the
advantage that two samples, or boards for this project’s experiments, can be placed on it.
The bottom board can be placed on top of a stage that can be moved with a 2X
micropositioner. The actuator also allows separating the plates while still keeping them
parallel by moving the rails where the top plate is placed. Figures 5.1-5.2 show the setup
in the lab.
84
Figure 5.1: Experiment setup. The picture shows the stage with the micropositioner, one board on the
stage, a second board on the table, and the computer connected to the readout circuit.
0
Figure 5.2: Detail of stage. In the center of the picture the two plates can be seen. The upper plate is fixed
in the structure, while the plate below is placed on a stage controlled by a 2D micropositioner. Also, in the
left there is a bar to move the fixed plate in the Z axis. In the right, two cables connected to the bottom plate
are plugged into the readout circuit
5.3 Readout circuit
To obtain the best performance, the readout circuit was purchased from Analog Devices
for the experiments. The model used was the AD7745, which is a Capacitance-to-Digital
Converter based on a 24-bit Σ-Δ modulator. The functional block diagram is shown in
Figure 5.3.
85
Fig 5.3: Analog Devices AD7745 block diagram [5.1]
The features of this circuit are as in Table 5.1.
Resolution
Accuracy
Full-scale range
Parasitic capacitance to ground tolerance
Update rate
4 aF
4 fF
±4 pF
60 pF
10 Hz to 90 Hz
Table 5.1: AD7745 main features [5.1]
The evaluation board of this circuit includes the software needed for the computer
interface. This interface shows the instantaneous capacitance sensed, as well as a plot of
capacitance versus time. Figure 5.4 shows the interface window
Figure 5.4: Capacitance-to-voltage converter interface. The capacitance sensed oscillates due to noise.
The capacitance considered for the measurement is the mean of this oscillation.
86
5.4 Designs tested
Two boards were designed to carry out two different experiments. First, to test the sensor
performance when the gap between the plates is the minimum achievable and a final
accurate alignment is needed, a board with large features was used to obtain a small
width/gap ratio. This experiment aims at estimating the maximum alignment accuracy
achievable by the sensor. The second board designed has larger feature size and is meant
to test the performance of the fractal geometry, as well as to verify whether both
simulations and capacitance analysis agree with the experimental results.
5.4.1 Large feature test board
To reach small width/gap ratios, the designed board with wider traces is as shown in
Figure 5.5.
Figure 5.5: Board layouts. The red color shows the traces on the top layer, while the green color shows the
traces on the bottom layer. The board dimension is 3.8’’x 2.5’’ (9.65 x 6.35 cm2)
The board is composed of three groups of electrodes. The dimensions are shown in Table
5.2.
87
left board
0.12’’
0.12’’
0.36’’
trace width
separation traces
separation groups
3.048 cm
3.048 cm
9.144 cm
right board
0.25’’
0.47’’
6.350 cm
11.938 cm
Table 5.2: Geometry boards Figure 5.5
The smallest gap that could be reached was in the order of 1 mm. For this gap the results
and comparative simulations are shown in Figure 5.6.
simulation and experiments gap 1 mm
13
capacitance [pF]
12
11
10
experiment a
experiment b
sim 1mm
sim1.5 mm
9
8
7
6
5
4
0
5
10
15
20
25
30
displacement [mm]
Figure 5.6: Capacitance [pF] versus lateral displacement [mm].. The measurement was repeated twice (red
and green in figure). The blue and black lines show simulation results for gap of 1 mm and 1.5 mm.
The experimental results and the simulations show similar variations of capacitance with
displacement. However the experimental curves have a larger ‘dc’ component than the
simulations. To compare the results, Figure 5.7 shows the curves without the ‘dc’
component.
88
simulation and experiments gap 1 mm
experiment a
experiment b
sim 1mm
sim1.5 mm
capacitance - C(displ=0) [pF]
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
0
5
10
15
20
25
30
35
displacement [mm]
Figure 5.7: Capacitance versus displacement. The initial capacitance for displacement zero was subtracted
to the capacitance, so that the curve profiles could be more easily compared. Although the experimental
results do not fit any of the simulation results, they show a similar variation of capacitance with
displacement
Figure 5.8 shows the capacitance from another experiment, where the displacement step
was reduced and the boards were near to the alignment centered position.
experimental results, gap 1 mm
16.01
capacitance [pF]
16.005
16
15.995
15.99
15.985
15.98
15.975
1.6
1.8
2
2.2
2.4
2.6
2.8
displacement [mm]
Figure 5.8: Capacitance [pF] versus lateral displacement [mm]. Gap 1 mm. The readout circuit shows to be
able to read changes in capacitance up to the order of 5 fF, which results with this geometry in an accuracy
of 0.1 mm
For longer gaps, the results were as in Figure 5.9.
89
simulation and experiments
0
capacitance -C(displ=0) [pF]
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
experiment 3 mm
sim 3 mm
experiment 6 mm
sim 6 mm
experiment 12 mm
sim 12 mm
-0.35
-0.4
-0.45
-0.5
0
5
10
15
20
25
30
35
40
displacement [mm]
Figure 5.9: Capacitance [pF] versus lateral displacement [mm]. The results show that even
for a large gap such as 12 mm the readout circuit is able to detect changes in capacitance up to
3 mm within alignment.
5.4.2 Central fractal geometry test board
The second board was designed with the traces following the central fractal geometry
explained in Section 2.2.3. The boards are shown in Figure 5.10.
Figure 5.10: Test board layout implementing central fractal geometry. The red color shows the traces on the
top layer, while the green color shows the traces on the bottom layer. The board dimension is 3.8’’x 2.5’’
(9.65 x 6.35 cm2)
Figure 5.11 zooms on the left board of Figure 5.6 and gives the geometry as function of
the minimum feature size u.
90
Figure 5.11: geometry of left board of Figure 5.6. The dimensions are given in function of the minimum
feature size u, which in this case is 0.03’’
The dimensions are also gathered in Table 5.3.
central group
lateral group
width
spacing traces
spacing subgroups
total width group
width
spacing traces
spacing groups
left board
units (u)
1
1
3
15
5
5
15
inches
0.03’’
0.03’’
0.09’’
0.45’’
0.15’’
0.15’’
0.45’’
mm
0.762
0.762
2.286
11.43
3.81
3.81
11.43
Table 5.3: dimensions board Figure 5.13
The experimental results and simulations are as in Figure 5.12.
91
right board
units
inches
2
0.06’’
1
0.03’’
4
0.12’’
14
0.42’’
10
0.3’’
mm
1.524
0.762
3.048
10.668
7.62
0.54’’
13.716
18
central fractal test board
0.2
exp g 1 mm
exp g 2 mm
exp g 3mm
exp g 4mm
sim g 1mm
sim g 2 mm
sim g 3 mm
sim g 4 mm
0
capacitance [pF]
-0.2
-0.4
-0.6
-0.8
-1
-1.2
0
5
10
15
20
25
30
35
40
displacement [mm]
Figure 5.12: capacitance [pF] versus displacement [mm]. As in Figure 5.7, the initial capacitance for
displacement zero was subtracted to the capacitance. Here again, the simulations and experiments give
curves with similar profile.
Reference:
[5.1] http://www.analog.com/en/prod/0,2877,AD7745,00.html
92
6. Conclusions and future work
6.1 Experimental results
The experiments with the test boards showed in general that the models of Section 3.3
and simulations have sufficient accuracy for design purposes. The simulations,
nevertheless, result in lower capacitance values than the experiments. This is most likely
caused by the assumption that there is no capacitance from the electrodes to the ground.
Including this capacitance to ground, the equivalent circuit model of Figure 3.8 would
look like in Figure 6.1.
Figure 6.1: Sensor equivalent circuit. The circuit includes the capacitance from the electrodes to ground
(green). Also the capacitance from the plates (nodes 4 and 5) to the stage (S), and the capacitance from the
stage to ground are included.
The difference between the simulations and the experiments increases with larger
displacement, according to Figure 5.9. For large displacement the capacitance obtained in
the experiments is less sensitive to displacement than the capacitance from simulations.
This is believed to occur because the models do not include the capacitance from the
93
plates to the stage, as shown in Figure 6.1. This large capacitance becomes dominant for
large gaps when the capacitance C12 decreases. Since this capacitance to stage is
independent of displacement, the output capacitance sensitivity to displacement decreases.
Another important difference between simulations and experiments is the assumption in
the simulations that the plates are parallel. Figure 5.7 shows two different curves from
experiments that are supposed to have the same gap. The difference between the two
experiments is most likely due to plate tilting, which can make the plates to get closer of
further with displacement depending on the tilting orientation. The chips to align with the
nanoaligner would have four sensors built-in on the four chip corners. To minimize tilting,
the nanoaligner would have to move the plates keeping the capacitance from the four
sensor as equal as possible.
As shown in Figure 5.8, the best alignment obtained with the large feature test board was
in the order of 0.1 millimeters. If optical lithography is to be used in the sensor
fabrication, the sensor width could be in the order of 1 μm. For this width, assuming that
the nanoaligner can reach a gap in the order of 100 nm, by using Eqns 5.3 and 5.4 the
expectable achievable alignment can be calculated in principle.
x min   x min PCB
LPCB n PCB g 
75mm
3
100nm
 0.1mm
 13.63nm ~ 10nm
L n  g PCB
15mm (3  4  2) 1mm
(6.1)
The sub-indexes μ and PCB refer to the sensor fabricated by means of optical
lithography, and the printed circuit board designed for the experiments respectively.
The test board with central fractal geometry gave results as expected and obtained in the
simulations. The central thinner electrodes give three peaks when the gap is in the order
of the electrodes width, and one wider peak when the gap is larger.
94
6.2 Design recommendations
Three possible sensor designs were pointed in section 2.2. To choose one of the three
approaches the nanoaligner’s capabilities have to be considered. From the simulations
and experiment results, it can be extracted that the central fractal geometry showed to
obtain the best performance. This geometry is a good trade-off between the design
optimized for best performance at larger gaps and best performance at short gaps. The
traces for this geometry can be easily designed by choosing the minimum feature size and
the maximum sensor area. The capacitor width can be calculated as:
w  3u  5 n 1
(6.1)
where u is the unit or minimum feature size (the traces’ width) and n the number of
fractal levels. The number of levels should be chosen so the capacitor fits within the
maximum sensor area. The following figure shows how the layout would look like the
following figure for three levels.
Figure 6.2: proposed central fractal geometry design. In this case the fractal has three levels.
95
The following table gathers several suggested designs that could be used and estimates
the alignment that would achieve assuming that it reaches a particular minimum gap
Design number
Min feature size
w strip-group 1
w strip-group 2
w strip-group 3
w strip-group 4
w strip-group 5
w strip-group 6
Min gap
Max gap
#groups n
Xmin scaled
Xmin calculated
1
1 um
1-3 um
1-15 um
5-75 um
25-375 um
2
1 um
1-3 um
1-15 um
5-75 um
25-375 um
0.125-1.875 mm
20 nm
25 um
5
240 nm
4.8 nm
20 nm
0.1 mm
7
34 nm
0.68 nm
3
0.1 um
100-300 nm
0.1-1.5 um
0.5-7.5 um
2.5-37.5 um
12.5-187.5 um
0.0625-0.9375 mm
10 nm
62 um
9
26 nm
0.53 nm
4
1 um
1-3 um
1- 291 um
0.1 – 1.5 mm
20 nm
0.1 mm
49+2
5.8 nm
0.11 nm
Table 6.1: Suggestions for sensor design. The three first designs (1, 2, 3) are based on the central fractal
geometry, while design 4 is composed of 2 wide electrode groups and 49 thin equal electrode groups.
Designs 1 and 2 have a minimum feature size of 1μm, so the fabrication can be done by optical lithography.
Design 1 has a size of 0.375x0.375 mm2, while design 2 is 1.875x1.875 mm2. Design 3 has a feature size of
0.1 μm and and area of 0.9375x0.9375 mm2
Design 1 tries to fit the sensor within 0.5 mm long, and therefore it has 4 levels. This
limits the number of electrode groups to 5, which worsens the sensor accuracy. As well,
due to the size limitation, the widest electrode is only 25 μm width. This makes the initial
alignment for large gaps more complex.
Design 2 is an extension of design 1 with one more group, so the area is 1.875x1.875
mm2. This improves the alignment accuracy and makes the initial alignment for larger
gaps less demanding.
Design 3 assumes that the minimum feature size is 100 nm. This allows the sensor to
have more electrodes groups in the same area, and therefore it increases the alignment
accuracy.
96
Design four does not follow exactly central fractal geometry. Instead, it is composed of 1
wide group with 0.1 mm wide electrodes to increase the accuracy at large gaps. The rest
of the areas is used for as many 1 µm wide electrode groups as could be fit, which is 49
groups of 2 electrodes each. This approach increases the number of electrode groups n,
and therefore the alignment accuracy. As well, its wide group of 0.1 mm electrodes
allows a more accurate alignment for large gaps. The disadvantage of this approach is
that the large group has to do the alignment for all the gap range from 0.1 mm to 1 µm,
where the 1 µm wide groups take over. This could potentially lead to instability in the
alignment.
6.3 Future work
New geometries should be explored to improve capacitance sensitivity. Differential
capacitors, which are mentioned in Section 2.1, Figure 2.2-2.3, may improve capacitance
sensitivity. Furthermore, assuming that the geometry is perfectly symmetrical, they result
in zero capacitance rather than a maximum capacitance at central aligned position. To
overcome the problem of connections to both plates described in Figure 2.2, one could
employ a geometry such as that illustrated in Figure 6.3.
Figure 6.3: Differential capacitor with connections on only one side. The voltage supplies are of equal
magnitude but are 180o out of phase with each other. The arrow illustrates the output to a readout circuit.
The electrodes with the same number are connected.
97
Simplifying the capacitances in Figure 6.3 to C14, C24, and C34, the circuit illustrated in
Figure 6.4 can be extracted from Figure 6.3.
Figure 6.4: Circuit from scheme Figure 6.3.
The capacitors in the circuit in Figure 6.4 are arranged in start configuration. Figure 6.5
illustrates the circuit transformed to the equivalent star-triangle configuration [6.1]
Figure 6.5: Equivalent circuit of Figure 6.4 with star-triangle transformation.
The output current of the circuit in Figure 6.5 can be calculated analytically by neglecting
fringing fields. The capacitances of the circuit in Figure 6.4 are calculated in Figure 6.6
using the parallel infinite plate capacitance equation.
98
Differential capacitor
1.4
Capacitance [fF]
1.2
1
C14
C24
0.8
0.6
0.4
0.2
0
-0.5
0
lateral displacement [um]
0.5
Figure 6.6: Capacitance circuit Figure 6.4. The geometry of capacitors, as in Figure 6.3, assumes a gap of
0.1 μm, bottom electrode width 1μm, and top electrode width 4 μm.
The impedances in Figure 6.5 are calculated using the capacitance of Figure 6.6; Figure
6.7 shows the results.
15
16
x 10
Differential capacitor
Za
Zb
Impedance [Ohms]
14
12
10
8
6
4
2
0
-0.5
0
lateral displacement [um]
0.5
Figure 6.7: Impedances of circuit Figure 6.5.
Figure 6.8 shows the output current, assuming opposite voltages in the voltage supplies in
the Figure 6.5 circuit.
99
-16
6
x 10
Differential capacitor
Current [Amps]
4
2
0
-2
-4
-6
-0.5
Current through Za
Current through Zb
Output current
0
lateral displacement [um]
0.5
Figure 6.8: Currents of circuit from Figure 6.5. The output current is zero for zero displacement.
Non-differential capacitors have the disadvantage that when close to central alignment,
the output becomes flat due to fringing field effects, as shown in Figure 5.8, which
decreases the sensor resolution. Differential capacitors have the advantage that not only
do they not loose sensitivity when near central position, but they also allow a simple
means of detecting alignment by giving no output current.
100
Appendix
Appendix A: Calculation of equivalent output capacitance
MATLAB code:
syms ig v c12
%a=23, b=24, c=34, d=51, e=41, f=25, g=12, h=13, j=35, k=45,
%capacitances
[ia,ib,ic,id,iee,iff]=solve(‘1/c23*ia + 1/c13*(ia+ib+iff-id-iee)-v’ , ‘1/c24*ib + 1/c45*(ib+ic-iee) —
1/c35*(id+iee-ib-ic-iff) + 1/c13*(ia+ib+iff-id-iee)-v’,’1/c34*ic + 1/c45*(ib+ic-iee) — 1/c35*(id+iee-ib-iciff)’ , ‘1/c15*id — 1/c13*(ia+ib+iff-id-iee) + 1/c35*(id+iee-ib-ic-iff)’,’1/c14*iee — 1/c13*(ia+ib+iff-idiee) + 1/c35*(id+iee-ib-ic-iff) — 1/c45*(ib+ic-iee)’ , ‘1/c25*iff — 1/c35*(id+iee-ib-ic-iff) +
1/c13*(ia+ib+iff-id-iee)-v’,’ia,ib,ic,id,iee,iff’);
%
Ra *ia + Rh *ih
-v , Rb *ib + Rk *ik
-Rj *ij
+Rh *
ih
-v , Rc *ic + Rk * ik
- Rj * ij
, rd *id - rh *ih
+ Rj * ij
,
Re *iee - Rh * ih
+ Rj *ij
- Rk*ik
, Rf * if — Rj *ij
+ Rh *ih —
v
ig=simplify(ia+ib+iff);
cout=simplify(ig/v)+c12
Equivalent capacitance:
cout=(c45.*c13.*c15.*c23+c45.*c15.*c35.*c23+c24.*c13.*c15.*c23+c24.*c15.*c35.*c23+c24.*c45.*c35.
*c13+c14.*c35.*c45.*c23+c25.*c23.*c45.*c15+c45.*c25.*c34.*c14+c14.*c13.*c45.*c23+c14.*c13.*c35.
*c23+c23.*c13.*c35.*c45+c34.*c13.*c15.*c23+c34.*c15.*c35.*c23+c35.*c14.*c13.*c25+c13.*c25.*c34.
*c24+c34.*c25.*c45.*c13+c34.*c35.*c13.*c25+c13.*c25.*c35.*c45+c34.*c25.*c15.*c23+c34.*c25.*c13.
*c15+c34.*c25.*c15.*c35+c25.*c45.*c15.*c34+c34.*c25.*c24.*c15+c34.*c45.*c24.*c15+c34.*c35.*c24.
*c15+c34.*c13.*c25.*c23+c34.*c35.*c24.*c13+c15.*c24.*c45.*c23+c15.*c14.*c13.*c25+c15.*c45.*c25.
*c35+c15.*c24.*c25.*c23+c14.*c24.*c35.*c23+c14.*c24.*c45.*c35+c14.*c24.*c45.*c23+c14.*c24.*c35.
*c13+c14.*c24.*c45.*c13+c14.*c15.*c34.*c24+c14.*c25.*c34.*c24+c14.*c24.*c13.*c15+c14.*c24.*c15.
*c35+c14.*c24.*c15.*c23+c14.*c45.*c13.*c25+c14.*c24.*c13.*c25+c14.*c24.*c25.*c23+c14.*c24.*c25.
*c35+c14.*c35.*c24.*c34+c14.*c24.*c45.*c34+c35.*c24.*c13.*c25+c45.*c23.*c25.*c14+c25.*c45.*c13.
*c15+c25.*c24.*c13.*c15+c25.*c24.*c15.*c35+c25.*c14.*c15.*c35+c15.*c24.*c45.*c13+c14.*c25.*c35.
*c45+c14.*c13.*c25.*c23+c25.*c23.*c15.*c14+c34.*c24.*c45.*c13+c34.*c24.*c13.*c15+c25.*c15.*c34.
*c14+c35.*c25.*c34.*c14+c24.*c15.*c35.*c45+c45.*c13.*c25.*c23+c24.*c13.*c25.*c23+c45.*c15.*c23.
*c34+c24.*c45.*c13.*c23+c24.*c35.*c13.*c23+c14.*c45.*c23.*c34+c14.*c23.*c34.*c25+c14.*c23.*c34.
*c15+c35.*c14.*c23.*c34+c34.*c35.*c23.*c13+c34.*c45.*c23.*c13+c14.*c15.*c35.*c23+c14.*c13.*c15.
*c23)./(c24.*c35.*c23+c35.*c14.*c34+c24.*c45.*c35+c24.*c45.*c23+c14.*c35.*c23+c14.*c45.*c23+c35
.*c23.*c45+c24.*c35.*c13+c24.*c45.*c13+c45.*c25.*c34+c45.*c15.*c34+c34.*c25.*c23+c34.*c13.*c25
+c34.*c25.*c35+c14.*c13.*c35+c13.*c35.*c45+c15.*c34.*c24+c14.*c13.*c45+c25.*c34.*c24+c14.*c35.
*c45+c25.*c34.*c14+c15.*c34.*c14+c45.*c15.*c35+c45.*c13.*c15+c45.*c15.*c23+c14.*c13.*c25+c14.*
c25.*c23+c14.*c25.*c35+c24.*c13.*c15+c24.*c15.*c35+c34.*c13.*c15+c34.*c15.*c35+c34.*c15.*c23+c
34.*c35.*c13+c34.*c35.*c23+c34.*c45.*c13+c34.*c45.*c23+c24.*c15.*c23+c45.*c13.*c25+c45.*c25.*c
23+c45.*c25.*c35+c24.*c13.*c25+c24.*c25.*c23+c24.*c25.*c35+c14.*c13.*c15+c14.*c15.*c35+c14.*c1
5.*c23+c35.*c24.*c34+c24.*c45.*c34+c14.*c45.*c34)+c12;
101
Appendix B: APDL macro for capacitance extraction simplified model
table 3.2
!simplified model
! -----------------4--! -----3---! --1-- --2—
! -----------------5--finish
/clear
/prep7
/title, multielectrodes capacitor chip simulations
!-----------geometry parameters (um)-----------------g=.1
!gap
t=.1
!thickness
w=1
!width
wtop=2
!width top electrode
tox=.5
!oxide thickness
tsub=381
!Si substrate
wchip=500
!width chip
!there should be 27 groups of electrodes instead of 1, so the capacitances
!are around 27 times smaller. wchip=15mm/27= .5mm so capacitances are equivalent
displfinal=5 !displacement (final position)
displinitial=0
resolution=.1
points=(displfinal-displinitial)/resolution !points
step=(displfinal-displinitial)/points
s=1
s1=3
s2=15
s3=75
s4=0
!separation between two bottom electrodes
!separation units within first group
!separation subgroups in 2nd group
!separation subgroups in 3rd group
st= 2*w+2*s-wtop !separation
n1=3
n2=1
n3=1
n4=1
!number units first group
!number subgroups 2nd group
!number subgroups 3rd group
!number subgroups 4rd group
nelect=3*n1*n2*n3
wunit=2*w+s1
!width of unit,i.e. two bottom and 1 top electrode
w1=wunit*n1+2*s1
w2=w1*n2+(n2-1)*s2 !width 2nd group
102
w3=w2*n3+(n3-1)*s3 !width 3nd group
w4=w3*n4+(n4-1)*s4 !width 4th group
wt=w4+displfinal-displinitial !total capacitor width
*dim,c12,array,points !to store capacitance and displacement
*dim,c13,array,points
*dim,c14,array,points
*dim,c15,array,points
*dim,c23,array,points
*dim,c24,array,points
*dim,c25,array,points
*dim,c34,array,points
*dim,c35,array,points
*dim,c45,array,points
*dim,displacement,array,points
!----------material and element properties-----------et,1,121
!for air, 2-D, 8-node charge-based electric element
et,2,110,1,1 !to model open of 2D unbonded problem
!1: voltage, 1: 8 node quadrilater
et,3,121
!for si dioxide
mp,perx,1,1 !relative permittivity 1 for air
mp,perx,3,3.7 !relative permittivity 3.7 of SiO2
emunit,epzro,8.854e-6 !to obtain pF/um
!--------------model---------------------------------displ=displinitial
*do,id,1,points,1 !------displacement loop---------/prep7
!removing model
*if,id,gt,1,then
cmdele,1
cmdele,2
cmdele,3
cmdele,4 !delete assembly
cmdele,5
asel,all
aclear,all !clear mesh
adele,all !delete areas
lsel,all
ldele,all !delete lines
*endif
!drawing electrodes
spos=0
stb=wunit-wtop
align=(w4+displ)/2
*do,i4,1,n4,1
*do,i3,1,n3,1
103
*do,i2,1,n2,1
*do,i1,1,n1,1
rectng,spos-align-wtop/2+stb/2+displ/2,wtop/2+spos-align+stb/2+displ/2, g/2,g/2+t !top electrode 3
rectng,spos-align-displ/2,w+spos-align-displ/2,-g/2,-g/2-t !bottom electr 1
rectng,spos-align+w+s-displ/2,spos-align+2*w+s-displ/2,-g/2,-g/2-t !bottom elec 2
spos=spos+wunit+s1
*enddo
spos=spos-s1+s2
*enddo
spos=spos-s2+s3
*enddo
spos=spos-s3+s4
*enddo
!oxide
rectng, wchip/2, -wchip/2, g/2+t, g/2+t+tox
rectng,-wchip/2,wchip/2,-g/2-t,-g/2-t-tox
!Si substrate
rectng,-wchip/2,wchip/2, g/2+t+tox, g/2+t+tox+tsub
rectng,-wchip/2,wchip/2,-g/2-t-tox,-g/2-t-tox-tsub
!gap
rectng,-wchip/2,wchip/2,g/2+t,-g/2-t
!air
diag=wchip*1.7
cyl4,0,0,diag,180
cyl4,0,0,diag,180,0,360
!infinite element
cyl4,0,0,diag*1.1,180
cyl4,0,0,diag*1.1,180,0,360
aovlap,all
numcmp,area
numcmp,line
/pnum,area,1
aadd,nelect+9,nelect+10
aadd,nelect+6,nelect+7
numcmp,area
!-------------meshing---------------------------------!10,11: substrate
!12,13: ring
!14: oxide top
!15: oxide bottom
!16: air
!17: gap
!----specifying divisions per line
!electrodes
lsel,s,line,,1
104
*do,j,3,nelect*4,2
lsel,a,line,,j
*enddo
lesize,all,,,40
!oxide
lsel,s,line,,nelect*4+2 !line oxide-substrate
lsel,a,line,,nelect*4+4
lesize,all,,,1000
lsel,s,line,,nelect*6+4 !line gap-oxide right
lsel,a,line,,nelect*7+8
lsel,a,line,,nelect*6+2 !line gap-oxide left
lsel,a,line,,nelect*7+2
lesize,all,,,1000/2
!—meshing
mshape,1 !triangles
mshkey,0 !use free meshing
type,1
amesh,nelect+8 !gap
type,3
amesh,nelect+5 !oxide
amesh,nelect+6
type,1
smrtsize,1 !way way faster with smart mesh
amesh,nelect+7 !air
!—meshing infinite elements
lsel,s,line,,nelect*5+6,nelect*5+7
lesize,all,,,1
smrtsize,off
type,2
mshape,0
mshkey,1
amesh,nelect+3
amesh,nelect+4
!-----------setting up flag and electrodes--------------csys,1 !cylindrical
nsel,s,loc,x,diag*1.1
sf,all,inf !flags
!top electrodes
*do,i,1,nelect,3
*if,i,eq,1,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
105
cm,cond3,node
!bottom electrode left
*do,i,2,nelect,3
*if,i,eq,2,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond1,node
!bottom electrode right
*do,i,3,nelect,3
*if,i,eq,3,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond2,node
!top substrate electrode
asel,s,area,,nelect+1
lsla,s
nsll,s,1
cm,cond4,node
!bottom substrate electrode
asel,s,area,,nelect+2
lsla,s
nsll,s,1
cm,cond5,node
allsel,all
finish
!--------------solutions----------/solu
solve
cmatrix,1,’cond’,5,1
displacement(id)=displ
c12(id)=cmatrix(1,2,2)
106
c13(id)=cmatrix(1,3,2)
c14(id)=cmatrix(1,4,2)
c15(id)=cmatrix(1,5,2)
c23(id)=cmatrix(2,3,2)
c24(id)=cmatrix(2,4,2)
c25(id)=cmatrix(2,5,2)
c34(id)=cmatrix(3,4,2)
c35(id)=cmatrix(3,5,2)
c45(id)=cmatrix(4,5,2)
!saving results
*cfopen,c12,txt
*vwrite,c12(1)
(F20.16)
*cfopen,c13,txt
*vwrite,c13(1)
(F20.16)
*cfopen,c14,txt
*vwrite,c14(1)
(F20.16)
*cfopen,c15,txt
*vwrite,c15(1)
(F20.16)
*cfopen,c23,txt
*vwrite,c23(1)
(F20.16)
*cfopen,c24,txt
*vwrite,c24(1)
(F20.16)
*cfopen,c25,txt
*vwrite,c25(1)
(F20.16)
*cfopen,c34,txt
*vwrite,c34(1)
(F20.16)
*cfopen,c35,txt
*vwrite,c35(1)
(F20.16)
*cfopen,c45,txt
*vwrite,c45(1)
(F20.16)
*cfopen,displ,txt
*vwrite,displacement(1)
(F20.16)
*status,c12 !to get something on screen
displ=displ+step
finish
*enddo !---finishes displacement loop
*status
finish
107
Appendix C: APDL macro model for large gap and displacement range
table
!Jose Medina, ECE Northeastern, October 2006
!Capacitive displacement sensor design
!code models metal electrode, oxide and Si chip
! electrodes:
! -----------------4--! -----3---! --1-- --2—
! -----------------5--finish
/clear
/prep7
/title, multielectrodes capacitor chip simulations
/nerr,-1 !limits warning written to file.err to 1 per command
!-----------geometry parameters (um)-----------------g=20
!gap
t=.3
!thickness
w=1
!width
wtop=2
!width top electrode
tox=.5
!oxide thickness
tsub=381
!Si substrate
displfinal=10 !displacement (final position)
displinitial=0.5
resolution=.5
points=(displfinal-displinitial)/resolution !points
step=(displfinal-displinitial)/points
s=1
s1=2
s2=13
s3=65
s4=0
!separation between two bottom electrodes
!separation units within first group
!separation subgroups in 2nd group
!separation subgroups in 3rd group
st= 2*w+2*s-wtop !separation
n1=3
n2=3
n3=3
n4=1
!number units first group
!number subgroups 2nd group
!number subgroups 3rd group
!number subgroups 4rd group
nelect=3*n1*n2*n3
108
wunit=2*w+s1
!width of unit,i.e. two bottom and 1 top electrode
w1=wunit*n1+2*s1
w2=w1*n2+(n2-1)*s2 !width 2nd group
w3=w2*n3+(n3-1)*s3 !width 3nd group
w4=w3*n4+(n4-1)*s4 !width 4th group
wt=w4+displfinal-displinitial !total capacitor width
cx=0.01 !finer mesh box x
cair=2.5
cxchip=1.5 !times wider than capacitor width wt
*dim,c12,array,points !to store capacitance and displacement
*dim,c13,array,points
*dim,c14,array,points
*dim,c15,array,points
*dim,c23,array,points
*dim,c24,array,points
*dim,c25,array,points
*dim,c34,array,points
*dim,c35,array,points
*dim,c45,array,points
*dim,displacement,array,points
!----------material and element properties-----------et,1,121
!for air, 2-D, 8-node charge-based electric element
et,2,110,1,1 !to model open of 2D unbonded problem
!1: voltage, 1: 8 node quadrilater
et,3,121
!for si dioxide
mp,perx,1,1 !relative permittivity 1 for air
mp,perx,3,3.7 !relative permittivity 3.7 of SiO2
emunit,epzro,8.854e-6 !to obtain pF/um
!--------------model---------------------------------displ=displinitial
*do,id,1,points,1 !------displacement loop----------
/prep7
!removing model
*if,id,gt,1,then
cmdele,1
cmdele,2
cmdele,3
cmdele,4 !delete assembly
cmdele,5
asel,all
aclear,all !clear mesh
adele,all !delete areas
lsel,all
ldele,all !delete lines
*endif
109
!drawing electrodes
spos=0
stb=wunit-wtop
align=(w4+displ)/2
*do,i4,1,n4,1
*do,i3,1,n3,1
*do,i2,1,n2,1
*do,i1,1,n1,1
rectng,spos-align-wtop/2+stb/2+displ/2,wtop/2+spos-align+stb/2+displ/2, g/2,g/2+t !top electrode 3
rectng,spos-align-displ/2,w+spos-align-displ/2,-g/2,-g/2-t
!bottom electr 1
rectng,spos-align+w+s-displ/2,spos-align+2*w+s-displ/2,-g/2,-g/2-t !bottom elec 2
spos=spos+wunit+s1
*enddo
spos=spos-s1+s2
*enddo
spos=spos-s2+s3
*enddo
spos=spos-s3+s4
*enddo
!oxide
rectng,-spos*cxchip,spos*cxchip, g/2+t, g/2+t+tox
rectng,-spos*cxchip,spos*cxchip,-g/2-t,-g/2-t-tox
!Si substrate
rectng,-spos*cxchip,spos*cxchip, g/2+t+tox, g/2+t+tox+tsub
rectng,-spos*cxchip,spos*cxchip,-g/2-t-tox,-g/2-t-tox-tsub
!gap
rectng,-spos*cxchip,spos*cxchip,g/2+t,-g/2-t
!air
diag=((g/2+t+tox+tsub)**2+(spos*cxchip)**2)**.5
cyl4,0,0,diag*cair,180
cyl4,0,0,diag*cair,180,0,360
!infinite element
r_infe=diag*cair*1.1
cyl4,0,0,r_infe,180
cyl4,0,0,r_infe,180,0,360
aovlap,all
numcmp,area
numcmp,line
/pnum,area,1
aadd,nelect+5,nelect+6 !air: nelect+11
aadd,nelect+9,nelect+10 !gap: nelect+5
numcmp,area
!-------------meshing---------------------------------!substrate bottom,top: 82,83
!inf elem rings bottom,top: 84,85
110
!gap: 86
!oxide top,bottom:87,88
!air: 89
!----defining divisions per line
!oxide-substrate
lsel,s,line,,326 !top
lsel,a,line,,328 !bottom
lesize,all,,,1000
!oxide-gap
lsel,s,line,,350 !top left
lsel,a,line,,377 !bottom left
lsel,a,line,,376 !top right
lsel,a,line,,431 !bottom right
lesize,all,,,500
!infinite elements
lsel,s,line,,340,341
lesize,all,,,1
!----meshing
!gap
smrtsize,1 !way faster and less errors with smart mesh
mshape,1 !triangles
mshkey,0 !use free meshing
type,1
amesh,86
!oxide
type,3
smrtsize,off
amesh,87
amesh,88
!air
type,1
smrtsize,1
amesh,89
!infinite elements
smrtsize,off
type,2
mshape,0
mshkey,1
amesh,84
amesh,85
!-----------setting up flag and electrodes--------------csys,1 !cylindrical
nsel,s,loc,x,r_infe
!nplot
sf,all,inf !flags
!top electrodes
111
*do,i,1,nelect,3
*if,i,eq,1,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond3,node
!bottom electrode left
*do,i,2,nelect,3
*if,i,eq,2,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond1,node
!bottom electrode right
*do,i,3,nelect,3
*if,i,eq,3,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond2,node
!top substrate electrode
asel,s,area,,nelect+2
lsla,s
nsll,s,1
cm,cond5,node
!bottom substrate electrode
asel,s,area,,nelect+1
lsla,s
nsll,s,1
cm,cond4,node
112
allsel,all
finish
!--------------solutions----------/solu
solve
cmatrix,1,’cond’,5,1
displacement(id)=displ
c12(id)=cmatrix(1,2,2)
c13(id)=cmatrix(1,3,2)
c14(id)=cmatrix(1,4,2)
c15(id)=cmatrix(1,5,2)
c23(id)=cmatrix(2,3,2)
c24(id)=cmatrix(2,4,2)
c25(id)=cmatrix(2,5,2)
c34(id)=cmatrix(3,4,2)
c35(id)=cmatrix(3,5,2)
c45(id)=cmatrix(4,5,2)
!saving results
*cfopen,c12chip,txt
*vwrite,c12(1)
(F20.16)
*cfopen,c13chip,txt
*vwrite,c13(1)
(F20.16)
*cfopen,c14chip,txt
*vwrite,c14(1)
(F20.16)
*cfopen,c15chip,txt
*vwrite,c15(1)
(F20.16)
*cfopen,c23chip,txt
*vwrite,c23(1)
(F20.16)
*cfopen,c24chip,txt
*vwrite,c24(1)
(F20.16)
*cfopen,c25chip,txt
*vwrite,c25(1)
(F20.16)
*cfopen,c34chip,txt
*vwrite,c34(1)
(F20.16)
*cfopen,c35chip,txt
*vwrite,c35(1)
(F20.16)
*cfopen,c45chip,txt
*vwrite,c45(1)
(F20.16)
*cfopen,displchip,txt
*vwrite,displacement(1)
(F20.16)
113
*status,c12
displ=displ+step
finish
*enddo !finishes displacement loop
*status,displacement
finish
Appendix D: MATLAB filter for ANSYS capacitance results
%’c12, c13, c14, c15, c23, c24, c25, c34, c35, c45, displ’ are input data in this file
cout=(c45.*c13.*c15.*c23+c45.*c15.*c35.*c23+c24.*c13.*c15.*c23+c24.*c15.*c35.*c23+c24.*c45.*c35.
*c13+c14.*c35.*c45.*c23+c25.*c23.*c45.*c15+c45.*c25.*c34.*c14+c14.*c13.*c45.*c23+c14.*c13.*c35.
*c23+c23.*c13.*c35.*c45+c34.*c13.*c15.*c23+c34.*c15.*c35.*c23+c35.*c14.*c13.*c25+c13.*c25.*c34.
*c24+c34.*c25.*c45.*c13+c34.*c35.*c13.*c25+c13.*c25.*c35.*c45+c34.*c25.*c15.*c23+c34.*c25.*c13.
*c15+c34.*c25.*c15.*c35+c25.*c45.*c15.*c34+c34.*c25.*c24.*c15+c34.*c45.*c24.*c15+c34.*c35.*c24.
*c15+c34.*c13.*c25.*c23+c34.*c35.*c24.*c13+c15.*c24.*c45.*c23+c15.*c14.*c13.*c25+c15.*c45.*c25.
*c35+c15.*c24.*c25.*c23+c14.*c24.*c35.*c23+c14.*c24.*c45.*c35+c14.*c24.*c45.*c23+c14.*c24.*c35.
*c13+c14.*c24.*c45.*c13+c14.*c15.*c34.*c24+c14.*c25.*c34.*c24+c14.*c24.*c13.*c15+c14.*c24.*c15.
*c35+c14.*c24.*c15.*c23+c14.*c45.*c13.*c25+c14.*c24.*c13.*c25+c14.*c24.*c25.*c23+c14.*c24.*c25.
*c35+c14.*c35.*c24.*c34+c14.*c24.*c45.*c34+c35.*c24.*c13.*c25+c45.*c23.*c25.*c14+c25.*c45.*c13.
*c15+c25.*c24.*c13.*c15+c25.*c24.*c15.*c35+c25.*c14.*c15.*c35+c15.*c24.*c45.*c13+c14.*c25.*c35.
*c45+c14.*c13.*c25.*c23+c25.*c23.*c15.*c14+c34.*c24.*c45.*c13+c34.*c24.*c13.*c15+c25.*c15.*c34.
*c14+c35.*c25.*c34.*c14+c24.*c15.*c35.*c45+c45.*c13.*c25.*c23+c24.*c13.*c25.*c23+c45.*c15.*c23.
*c34+c24.*c45.*c13.*c23+c24.*c35.*c13.*c23+c14.*c45.*c23.*c34+c14.*c23.*c34.*c25+c14.*c23.*c34.
*c15+c35.*c14.*c23.*c34+c34.*c35.*c23.*c13+c34.*c45.*c23.*c13+c14.*c15.*c35.*c23+c14.*c13.*c15.
*c23)./(c24.*c35.*c23+c35.*c14.*c34+c24.*c45.*c35+c24.*c45.*c23+c14.*c35.*c23+c14.*c45.*c23+c35
.*c23.*c45+c24.*c35.*c13+c24.*c45.*c13+c45.*c25.*c34+c45.*c15.*c34+c34.*c25.*c23+c34.*c13.*c25
+c34.*c25.*c35+c14.*c13.*c35+c13.*c35.*c45+c15.*c34.*c24+c14.*c13.*c45+c25.*c34.*c24+c14.*c35.
*c45+c25.*c34.*c14+c15.*c34.*c14+c45.*c15.*c35+c45.*c13.*c15+c45.*c15.*c23+c14.*c13.*c25+c14.*
c25.*c23+c14.*c25.*c35+c24.*c13.*c15+c24.*c15.*c35+c34.*c13.*c15+c34.*c15.*c35+c34.*c15.*c23+c
34.*c35.*c13+c34.*c35.*c23+c34.*c45.*c13+c34.*c45.*c23+c24.*c15.*c23+c45.*c13.*c25+c45.*c25.*c
23+c45.*c25.*c35+c24.*c13.*c25+c24.*c25.*c23+c24.*c25.*c35+c14.*c13.*c15+c14.*c15.*c35+c14.*c1
5.*c23+c35.*c24.*c34+c24.*c45.*c34+c14.*c45.*c34)+c12;
n=length(displ)
displsym=[-displ(n:-1:1),displ];
coutsym=[cout(n:-1:1),cout];
windowSize = 20;
coutfilteredsym=filter(ones(1,windowSize)/windowSize,1,coutsym);
figure(1)
plot(displsym,coutsym,’b.’)
xlabel(‘displacement [um]’)
ylabel(‘capacitance [pF/um]’)
title(‘output capacitance, 3x3x3x3 model, g=20 um’)
figure(2)
plot(displsym,coutsym,’b’,’linewidth’,2)
xlabel(‘displacement [um]’)
ylabel(‘capacitance [pF/um]’)
114
title(‘output capacitance, 3x3x3x3 model, g=20 um’)
figure(3)
plot(displsym,coutfilteredsym,’b.’,’linewidth’,2)
xlabel(‘displacement [um]’)
ylabel(‘capacitance [pF/um]’)
title(‘filtered output capacitance, 3x3x3x3 model, g=20 um’)
Appendix E: APDL macro to calculate lumped matrix capacitance
versus number of nodes per electrode’s horizontal surface
!analysis convergency
! -----------------4--! -----3---! --1-- --2—
! -----------------5--finish
/clear
/prep7
/title, multielectrodes capacitor chip simulations
!-----------geometry parameters (um)-----------------g=.1
!gap
t=.1
!thickness
w=1
!width
wtop=2
!width top electrode
tox=.5
!oxide thickness
tsub=381
!Si substrate
wchip=500
!width chip
!there should be 27 groups of electrodes instead of 1, so the capacitances
!are around 27 times smaller. wchip=15mm/27= .5mm so capacitances are equivalent
displ=0
divinitial=5
divfinal=100
step=5
points=(displfinal-displinitial)/step+1 !points
s=1
s1=3
s2=15
s3=75
s4=0
!separation between two bottom electrodes
!separation units within first group
!separation subgroups in 2nd group
!separation subgroups in 3rd group
st= 2*w+2*s-wtop !separation
n1=3
!number units first group
115
n2=1
n3=1
n4=1
!number subgroups 2nd group
!number subgroups 3rd group
!number subgroups 4rd group
nelect=3*n1*n2*n3
wunit=2*w+s1
!width of unit,i.e. two bottom and 1 top electrode
w1=wunit*n1+2*s1
w2=w1*n2+(n2-1)*s2 !width 2nd group
w3=w2*n3+(n3-1)*s3 !width 3nd group
w4=w3*n4+(n4-1)*s4 !width 4th group
wt=w4+displfinal-displinitial !total capacitor width
*dim,c12,array,points !to store capacitance and displacement
*dim,c13,array,points
*dim,c14,array,points
*dim,c15,array,points
*dim,c23,array,points
*dim,c24,array,points
*dim,c25,array,points
*dim,c34,array,points
*dim,c35,array,points
*dim,c45,array,points
*dim,divisions,array,points
!----------material and element properties-----------et,1,121
!for air, 2-D, 8-node charge-based electric element
et,2,110,1,1 !to model open of 2D unbonded problem
!1: voltage, 1: 8 node quadrilater
et,3,121
!for si dioxide
mp,perx,1,1 !relative permittivity 1 for air
mp,perx,3,3.7 !relative permittivity 3.7 of SiO2
emunit,epzro,8.854e-6 !to obtain pF/um
!--------------model---------------------------------div=divinitial
*do,id,1,points,1 !------displacement loop----------
/prep7
!removing model
*if,id,gt,1,then
cmdele,1
cmdele,2
cmdele,3
cmdele,4 !delete assembly
cmdele,5
asel,all
aclear,all !clear mesh
adele,all !delete areas
lsel,all
116
ldele,all !delete lines
*endif
!drawing electrodes
spos=0
stb=wunit-wtop
align=(w4+displ)/2
*do,i4,1,n4,1
*do,i3,1,n3,1
*do,i2,1,n2,1
*do,i1,1,n1,1
rectng,spos-align-wtop/2+stb/2+displ/2,wtop/2+spos-align+stb/2+displ/2, g/2,g/2+t !top electrode 3
rectng,spos-align-displ/2,w+spos-align-displ/2,-g/2,-g/2-t !bottom electr 1
rectng,spos-align+w+s-displ/2,spos-align+2*w+s-displ/2,-g/2,-g/2-t !bottom elec 2
spos=spos+wunit+s1
*enddo
spos=spos-s1+s2
*enddo
spos=spos-s2+s3
*enddo
spos=spos-s3+s4
*enddo
!oxide
rectng, wchip/2, -wchip/2, g/2+t, g/2+t+tox
rectng,-wchip/2,wchip/2,-g/2-t,-g/2-t-tox
!Si substrate
rectng,-wchip/2,wchip/2, g/2+t+tox, g/2+t+tox+tsub
rectng,-wchip/2,wchip/2,-g/2-t-tox,-g/2-t-tox-tsub
!gap
rectng,-wchip/2,wchip/2,g/2+t,-g/2-t
!air
diag=wchip*1.7
cyl4,0,0,diag,180
cyl4,0,0,diag,180,0,360
!infinite element
cyl4,0,0,diag*1.1,180
cyl4,0,0,diag*1.1,180,0,360
aovlap,all
numcmp,area
numcmp,line
/pnum,area,1
aadd,nelect+9,nelect+10
aadd,nelect+6,nelect+7
numcmp,area
!-------------meshing---------------------------------!10,11: substrate
117
!12,13: ring
!14: oxide top
!15: oxide bottom
!16: air
!17: gap
!----specifying divisions per line
!electrodes
lsel,s,line,,1
*do,j,3,nelect*4,2
lsel,a,line,,j
*enddo
lesize,all,,,div
!oxide
lsel,s,line,,nelect*4+2 !line oxide-substrate
lsel,a,line,,nelect*4+4
lesize,all,,,1000
lsel,s,line,,nelect*6+4 !line gap-oxide right
lsel,a,line,,nelect*7+8
lsel,a,line,,nelect*6+2 !line gap-oxide left
lsel,a,line,,nelect*7+2
lesize,all,,,1000/2
!—meshing
mshape,1 !triangles
mshkey,0 !use free meshing
type,1
amesh,nelect+8 !gap
type,3
amesh,nelect+5 !oxide
amesh,nelect+6
type,1
smrtsize,1 !way way faster with smart mesh
amesh,nelect+7 !air
!—meshing infinite elements
lsel,s,line,,nelect*5+6,nelect*5+7
lesize,all,,,1
smrtsize,off
type,2
mshape,0
mshkey,1
amesh,nelect+3
amesh,nelect+4
!-----------setting up flag and electrodes--------------csys,1 !cylindrical
nsel,s,loc,x,diag*1.1
sf,all,inf !flags
!top electrodes
*do,i,1,nelect,3
118
*if,i,eq,1,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond3,node
!bottom electrode left
*do,i,2,nelect,3
*if,i,eq,2,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond1,node
!bottom electrode right
*do,i,3,nelect,3
*if,i,eq,3,then
asel,s,area,,i
lsla,s !selects lines from selected area
nsll,s,1 !selects nodes from selected lines
*else
asel,a,area,,i
lsla,a
nsll,a,1
*endif
*enddo
cm,cond2,node
!top substrate electrode
asel,s,area,,nelect+1
lsla,s
nsll,s,1
cm,cond4,node
!bottom substrate electrode
asel,s,area,,nelect+2
lsla,s
nsll,s,1
cm,cond5,node
allsel,all
finish
119
!--------------solutions----------/solu
solve
cmatrix,1,’cond’,5,1
divisions(id)=div
c12(id)=cmatrix(1,2,2)
c13(id)=cmatrix(1,3,2)
c14(id)=cmatrix(1,4,2)
c15(id)=cmatrix(1,5,2)
c23(id)=cmatrix(2,3,2)
c24(id)=cmatrix(2,4,2)
c25(id)=cmatrix(2,5,2)
c34(id)=cmatrix(3,4,2)
c35(id)=cmatrix(3,5,2)
c45(id)=cmatrix(4,5,2)
!saving results
*cfopen,c12convg01,txt
*vwrite,c12(1)
(F20.16)
*cfopen,c13convg01,txt
*vwrite,c13(1)
(F20.16)
*cfopen,c14convg01,txt
*vwrite,c14(1)
(F20.16)
*cfopen,c15convg01,txt
*vwrite,c15(1)
(F20.16)
*cfopen,c23convg01,txt
*vwrite,c23(1)
(F20.16)
*cfopen,c24convg01,txt
*vwrite,c24(1)
(F20.16)
*cfopen,c25convg01,txt
*vwrite,c25(1)
(F20.16)
*cfopen,c34convg01,txt
*vwrite,c34(1)
(F20.16)
*cfopen,c35convg01,txt
*vwrite,c35(1)
(F20.16)
*cfopen,c45convg01,txt
*vwrite,c45(1)
(F20.16)
*cfopen,divconvg01,txt
*vwrite,divisions(1)
(F20.16)
div=div+step
finish
*enddo !---finishes displacement loop
finish
120
Appendix F: input equivalent capacitance for connected plates.
The electrodes are numbered as shown in the figure below.
Figure. F.1: scheme sensor with plates connected
The following figure shows the selected tree and the branches.
Figure F.2: Circuit graph with selected tree and branch current references
The fundamental loops, branches, and equations are as follows.
Loop
2-3
2-4
1-4
Branch
2-3, 1-2, 1-3
2-4, 2-3, 3-4
1-4, 1-3, 3-4
Equation
0 = i23 Z23 – V + i13Z13
0 = i24 Z24 – i23Z23 + i34Z34
0 = i14 Z14 + i13 Z13 + i34 Z34
The cut set equations are as follows
i12 = i23 + i24
(F.1)
i34 = i24 + i14
(F.2)
i13 = i23 + i34 = i14 + i23 + i24
The following code implements the equations in MATLAB
syms v c12
[i14,i24,i23]=solve('i23*1/c23 - v + (i14+i23+i24)*1/c13','i24*1/c24 - i23*1/c23 +
(i24+i14)*1/c34','i14*1/c14 + (i14+i23+i24)*1/c13 + (i24+i14)*1/c34','i14,i24,i23');
i12=i23+i24;
cout=simplify(i12/v) +c12
121
(F.3)
The result is
cout =
(c34*c24*c13+c24*c14*c13+c24*c14*c34+c24*c14*c23+c13*c34*c23+c14*c13*c23+c14*c34*c23+c24
*c23*c13) / (c13*c34+c14*c13+c14*c34+c23*c34+c14*c23+c24*c34+c24*c13+c24*c23)+c12
Appendix G: hspice code readout circuit Figure 4.24 and RC LPF
*gregorian SCA
.lib 'models2.lib' devicemodels
.option post
.tran 10us 300ms sweep data=filter
.option dcstep=1e-5
.op
.data filter
rfilter
2meg
20meg
200meg
.enddata
Vinp in 0 1
M1 in phi1 1 0 cmosn
M2 1 phi2 0 0 cmosn
Cs 1 2 'V(var1)*1e-9' ic=0 $sensor capacitance
E1 out 0 3 2 1e6
Vos 3 0 .01
Cdg 1 out '5e-10' $anti-spike capacitor
Cf 2 4 '1e-9' ic=0 $feedback capacitor
M5 4 phi1 0 0 cmosn
M4 4 phi2 out 0 cmosn
M3 2 phi1 out 0 cmosn
*RC low pass filter
R7 out outf rfilter
C7 outf 0 1n
*nonoverlapping clocks
.param f=1ms
Vphi1 phi1 0 pulse(0 5 '0*f' '.1*f' '.1*f' '2.3*f' '5*f')
Vphi2 phi2 0 pulse(0 5 '2.5*f' '.1*f' '.1*f' '2.3*f' '5*f')
*control capacitance
Vc1 var1 0 pwl(0,0.1 100ms,1 200ms,1 300ms,0.1)
Rc1 var1 0 10k
.end
122