Contents
5.
External I/O Control ...................................................................................5-1
5.1.
5.2.
實驗目的.............................................................................................5-1
實驗原理.............................................................................................5-1
5.2.1.
About the GPIO unit ...................................................................5-1
5.2.2.
GPIO Overview ..........................................................................5-2
5.2.3.
Programmer’s model ...................................................................5-3
5.3.
引導實驗.............................................................................................5-4
5.3.1.
檔案說明.....................................................................................5-4
5.3.2.
實驗步驟.....................................................................................5-5
5.4.
實驗要求...........................................................................................5-22
5.5.
問題與討論.......................................................................................5-22
5.6.
參考文件...........................................................................................5-22
說明
1. 本實驗所需設備：ARM Integrator AP、CM、LM (Altera)、ARM Multi-ICE、
麵包版、LED、文字型 LCD；本實驗所需軟體：ARM Developer Suite、
LeonadoSpetrum、Quartus II。
2. 本實驗需用到 LM 中的 FPGA。規劃 LM 的 FPGA 的方法在另一個實驗「ASIC Logic」
中提及，故授課教師可依實際狀況將本實驗安排在「ASIC Logic」實驗之後。
3. 本實驗之操作步驟適合於使用 Altera 型式的 LM。採用 Xilinx LM 的學校，
請將本實驗安排在「ASIC Logic」實驗之後，等學生學會規劃 Xilinx LM 的
FPGA 的方法後，才安排本實驗。
External I/O control
5. External I/O Control
--Using the GPIO Unit to Control the External I/O Devices
5.1. 實驗目的
In this Lab, you will learn (1) the operation mechanism of a GPIO (General
Purpose Input/Output) unit, (2) the method of connecting an external I/O device to the
ARM Integrator Platform, and (3) how to employ the GPIO to control the external I/O
device.
5.2. 實驗原理
5.2.1.
About the GPIO unit
The GPIO (General Purpose Input/Output) unit is an AMBA slave module that
connects to the APB. It has 16 bits of programmable input/output organized as two
8-bit ports, port A and port B. Pins of both ports can be configured as either inputs or
outputs. The GPIO unit interface with input/output pad cells using a data input, data
output and output enable line per pad. Figure 10-1 illustrates the GPIO interfaces, and
Figure 10-2 shows the GPIO block diagram.
Figure 10-1. GPIO interfaces.
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Figure 10-2. GPIO block diagram
5.2.2.
GPIO Overview
GPIO provides 16 inputs/outputs organized as two 8-bit groups, port A and port
B. The CPU reads and writes data and control/status information to and from GPIO
via the AMBA APB interface. Each port has an associated data direction register and
a data register.
Data direction register
The data direction register is 8 bits wide, and is programmed to select whether
each individual input/output pin is configured as an input or an output.
Data register
The data register is 8 bits wide, and is used to read the value input on those
GPIO lines that are configured as inputs, and to program the value output on those
GPIO line that are configured as outputs.
AMBA APB interface
The AMBA APB groups narrow-bus peripherals to avoid loading the system
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bus, and provides an interface using memory-mapped registers which are accessed
under programmed control.
The AMBA APB interface generate read and write decodes for accesses to the
control register and data register for each input/output port.
5.2.3.
Programmer’s model
The GPIO registers are shown in Table 10-1.
Table 10-1. GPIO register summary
GPIOPADDR is the port A data direction register. Bits set in GPIOPADDR will
set the corresponding pin in PORT A to be an output. Clearing a bit configures the pin
to be an input.
GPIOPBDDR is the port B data direction register. Bits cleared in GPIOPBDDR
will set the corresponding pin in PORT B to be an output. Setting a bit configures the
pin to be an input.
The base address of the PrimeCell GPIO is not fixed, and may be different for
any particular system implementation. However, the offset of any particular register
from the base address is fixed.
In this Lab, the GPIO unit is implemented in the FPGA of LM, and the base
address of GPIO is selected as 0xC2100000.
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Figure 10-3. Memory map of Logic Module
5.3. 引導實驗
In this Lab, you will implement a GPIO in the FPGA of the logic module. The
port A and port B of the GPIO unit will be assigned to those FPGA pins that
connected to the prototyping grids such that the ports of GPIO can be accessed via the
prototyping grids on the logic module. You will use the GPIO to control the flashing
of LCDs on a breadboard. In the exercise, you are asked to employ the GPIO unit to
control a text LCD display.
5.3.1.
檔案說明
The associated Verilog files include
AHBAPBSys.v
AHBAHBTop.v
AHB2APB.v
AHBDecoder.v
AHBDefaultSlave.v
AHBMuxS2M.v
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AHBZBTRAM.v
APBIntcon.v
APBRegs.v
GPIO060.v
APBMuxP2B.v
You can find the Verilog files in the directory Codes/HW/GPIO/Verilog. Also, you
can find a testbench for simulating the GPIO unit in the directory
Codes/HW/GPIO/Testbench.
The associated software source codes can be found in the directory
Codes/SW/GPIO.
The associated reference documents, such as ARM PrimeCell™ General Purpose
Input/Output （PL060）Technical Reference Manual, the document of the LM PCB
layout, and documents for text LCD display, can be found in the directory Doc/Ref.
5.3.2.
實驗步驟
1. Logic Synthesis
In the logic synthesis stage, we use LeonadoSpetrum to compile the HDL files
into a netlist file (EDIF file).
(1) Start LeonadoSpetrum.
(2) Specify the FPGA device （Figure 10-4）.Choose the Family =>APEX 20KE;
Device =>EP20K1000EFC672; Speed Grade => -2.
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Figure 10-4. Specify the FPGA device.
(3) Specify the input HDL files. Click the Input tab and Click the Open file icon
to add the input HDL files, and set the working directory. (Figure 10-5)
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Figure 10-5. Specify the input HDL files.
(4) Specify the output file and its path. Click the Output tab and fill the output
filename, e.g., GPIO060.edf. (Figure 10-6)
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Figure 10-6. Specify the output file.
(5) Click the Run Flow icon to start logic synthesis. After synthesis, you will get
the output netlist file, GPIO060.edf.
2. Place and Route
We will use the Quartus II to complete the Place and Route of the design.
(1) Select 「Programs/Altera/Quartus II 2.2」to start Quartus II..
(2) Create a new project for the design. Click the 「File/New Project Wizard」,
and then fill the working directory, the project name, and the name of the
top-level design entry in the New Project Wizard window (Figure 10-7).
Click Next.
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Figure 10-7. Create a new project.
(3) Specify the input netlist file, e.g., GPIO060.edf (Figure 10-8). Click
Next.
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Figure 10-8. Specify the input netlist file.
(4) In the EDA tool field, choose 「Design entry/synthesis -LeonardoSpectrum」(Figure 10-9). Click Next.
Figure 10-9. EDA Tools Settings.
(5) Specify the Family as APEX20KE (Figure 10-10). Click Next.
Figure 10-10. Specify the FPGA family.
(6) Select the target device as EP20K1000EFC672-2 (Figure 10-11). Click
Next.
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Figure 10-11. Select the target device.
(7) Check the information and click Finish (Figure 10-12).
Figure 10-12. Check the summary
(8) Specify the compiler settings. In the Quartus II window, Click
「Assignments/Settings…」(Figure 10-13).
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Figure 10-13. Specify the compiler settings
(9) Click 「Compiler Settings/Device」 in the Category field (Figure 10-14).
Figure 10-14. Device settings
(10) Click the Device & Pin Options, and a new Device & Pin Options window will
appear. Set the options as shown in Figure 10-15.
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Figure 10-15. Device & Pin Options
(11) Click the Configuration tab and modify the Configuration scheme as
shown in Figure 10-16.
Figure 10-16. Configuration setting
(12) Click the Program tab and check the Raw Binary File box (Figure 10-17).
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Figure 10-17. Program file settings
(13) Click the Unused Pins tab, and check the As input, tri-state option (Figure
10-18).
Figure 10-18. Unused pins setting
(14) Click the Dual-Purpose Pins tab, and disable all options (Figure 10-19).
Click OK to return the main window of Quartus II.
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Figure 10-19. Dual-Purpose pins settings
(15) Click the Compile icon in the Quartus II window to compile the design
(Figure 10-20). When compiling is finished, the files xxx.rbf and xxx.csf will
appear in working directory.
Figure 10-20.
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3. Pin Assignment
We want the input/output ports of GPIO to be connected to the prototyping grids
in the logic module such that we can access the input/output ports of GPIO via the
prototyping grids. From the document lm_ep20k600e_reva.pdf (in “\Program
Files\ARM\Logic Modules\LM-EP20K600E\schematics\lm_ep20k600e_reva.pdf”),
you can find the schematic diagram of the LM PCB. Figure 10-21 shows part of the
pin names of prototyping grids in the logic module, and Figure 10-22 shows the
Bank-5 pin names of the FPGA. You can see that many Bank-5 pins of FPGA are
wired to the prototyping grids in the logic module. You have to modify the file xxx.csf
（AHBAHBTOP.csf）such that the pins of the GPIO are assigned to the appropriate
pins of the FPGA that are connected to the prototyping grids. In the following, we will
assign the port A of GPIO to row 2 of prototyping grid, and assign port B to row 3 of
the prototyping grid.
Figure 10-21. Pin names of prototyping grids in the logic module
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Figure 10-22. The Bank-5 pin names of the FPGA (20K600E-672)
(1) In the Quartus II window, click “Assignment/Back-Annotate
Assignments”. Check the Pin & Device assignments option (Figure 10-23).
Click OK. This step will save the current pin assignment (which need to be
modified) in the file ***.csf （AHBAHBTOP.csf）.
Figure 10-23. Back-annotate assignment
(2) Modify the pin assignment in ***.csf （AHBAHBTOP.csf）as follows:
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GPIO1XPA[0] : LOCATION = Pin_Y24;
GPIO1XPA[1] : LOCATION = Pin_AA24;
GPIO1XPA[2] : LOCATION = Pin_AB24;
GPIO1XPA[3] : LOCATION = Pin_Y23;
GPIO1XPA[4] : LOCATION = Pin_AA23;
GPIO1XPA[5] : LOCATION = Pin_AB23;
GPIO1XPA[6] : LOCATION = Pin_AD23;
GPIO1XPA[7] : LOCATION = Pin_AC22;
GPIO1XPB[0] : LOCATION = Pin_AD22;
GPIO1XPB[1] : LOCATION = Pin_AC21;
GPIO1XPB[2] : LOCATION = Pin_AD21;
GPIO1XPB[3] : LOCATION = Pin_W20;
GPIO1XPB[4] : LOCATION = Pin_Y20;
GPIO1XPB[5] : LOCATION = Pin_AA20;
GPIO1XPB[6] : LOCATION = Pin_AB20;
GPIO1XPB[7] : LOCATION = Pin_AC20;
GPIO1XPB[8] : LOCATION = Pin_AD20;
GPIO1XPB[9] : LOCATION = Pin_Y19;
CTRLCLK2[6] : LOCATION = Pin_K18;
(3) Click the Compile icon in the Quartus II window to re-compile the design. When
compiling is finished, the file xxx.rbf (AHBAHBTop.rbf) will be created in the
working directory. Now the xxx.rbf has a correct pin assignment.
4. Porting the RBF file (AHBAHBTop.rbf) to the Logic Module
(1) Create a BRD file as below
[General]
Name = example2 AHB EP20K1000E -> flash (addr 0x0)
Priority = 1
[ScanChain]
TAPs = 2
TAP0 = EP20K1000E
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TAP1 = ARMFLASH
[Program]
SequenceLength = 2
Step1Method
= IntelFlash
Step1TAP
=1
Step1File
= AHBAHBTop.rbf
Step2Method
= IntelFlashVerify
Step2TAP
=1
Step2File
= AHBAHBTop.rbf
Save the file and rename it as GPIO.brd.
(2) Copy the file progcard.exe (in \Program Files\ARM\Logic
Modules\LM-EP20K600E\configure\) to your working directory
(3) Make sure that the Integrator is power off.
(4) Adjust the logic module into Flash Program Mode as follows:
(i)
Let the CONFIG LINK be shorted.
(ii)
Close the switch S1[4] (the switch is pull down)..
(5) Connect the Multi-ICE unit to the Logic Module.
(6) Power on the Integrator.
(7) Run the ARM Multi-ICE Server (/Programs/ARM Multi-ICE v2.2/Multi-ICE
Server) (Figure 10-24).
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Figure 10-24. Multi-ICE Server
(8) Check if the three files AHBAHBTop.rbf , GPIO.brd, and progcard.exe
exist in the working directory. Execute progcard.exe (Figure 10-25). This
step will download the design into the flash of LM.
Figure 10-25. Execute the progcard.exe to download the design into the
flash.
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(9) Shutdown the Integrator.
(10) Adjust the logic module into the User Mode as follows:
(i)
Adjust the CONFIG Link as open;
(ii)
Adjust the S1[4] as open (pull up).
(11) Adjust the switch S1[1] as closed (down) and switch S1[3] as open (up) to
select flash image 0.
5. Running the application program
An application example that employs the GPIO implemented in LM FPGA to
control the LED is given in the directory Codes/SW/GPIO.
(1) Connect Row 2 and Row 3 of the prototyping grid to the LEDs in a breadboardy
(Figure 10-26).
Figure 10-26. Connect the prototype grids to the LEDs in a breadboard
(2) Connect Multi-ICE to the Core Module
(3) Start the Multi-ICE Server
(4) Start ADS. Create a new project, and add the files in the directory
Codes/SW/GPIO to the project. Build this project.
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(5) Run the AXD and you will see the LEDs connected on the breadboard are
flashing.
5.4. 實驗要求
1. Understand the Verilog codes of GPIO and the source codes of the
application program, and try to modify the application program such that the
LCDs flash in a different way.
2. Modify the application program such that you can use the GPIO unit to
control an external text LCD such that you can display an arbitrary string in
the LCD.
5.5. 問題與討論
1. Read the ARM PrimeCell General Purpose Input/Output (PL061) Technical
Reference Manual and compare the differences between GPIO PL060 and GPIO
PL061.
5.6. 參考文件
1. ARM PrimeCell General Purpose Input/Output (PL060) Technical Reference
Manual (ARM DDI 0142B).
2. Zong-xin Lin, “Design of an ARM-based System-on-Chip for Real-time QRS
Detection in Electrocardiogram,” master thesis, Department of Electrical
Engineering, Chang Gung University, Taiwan, June 2003.
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