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SCR 1043
UNIVERSITI TEKNOLOGI MALAYSIA
TEST 2 SEMESTER 2 2008/2009
SUBJECT CODE
:
SCR 1043
SUBJECT TITLE
:
COMPUTER ORGANIZATION AND ARCHITECTURE
YEAR/COURSE
:
SCV, SCD, SCR, SCJ, SCI, SCK
DATE/TIME
:
13 MARCH 2009/ 2 HOURS
VENUE
:
MSI
(GENERAL INSTRUCTION):
Answer all questions. You are not allowed to ask ANY QUESTIONS during examination.
Answer Part A on an objective on the answer sheet provided.
Answer Part B on the space provided in the question paper.
This test will contribute 25% towards the total marks of 100 points.
Warning!
Students who are caught cheating during the Examination will be reported to the
disciplinary board for action to suspend the student for one or two semesters.
Name
SEC
Matric No
Lecturer
PM DR. MAZLEENA BT SALLEH
01
MOHD FO’AD BIN ROHANI
02 / 04
FIROZ BIN YUSOF PATEL DAWOODI
03 / 08
MOHD SETH BIN YAACOB
05 / 07
MARINA BT MD ARSHAD
06 / 09
ABD BAHRIM BIN YUSOFF
10
VIKNESH RAMAMOORTHY
11
This paper contains 15 pages including this cover page
MARKS
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SCR 1043
Part A: Objective Questions [30 marks]
1. If the initial value of register AL is FE, which of the following instructions will makes
AL equal to 0 (zero)?
A.
B.
C.
D.
ADD AL,2
INC AL
DEC AL
SUB AL,2
2. Which instruction has the same effect as Temp = Temp + 2?
A.
B.
C.
D.
3.
INC Temp
DEC Temp
SUB Temp,2
SUB Temp,-2
Given AX = F028h. Determine the flags’ values after the operation ADD AH,AL.
A.
B.
C.
D.
ZF = 0, SF = 1, CF = 1, AF = 0, OF = 0
ZF = 0, SF = 0, CF = 1, AF = 0, OF = 0
ZF = 0, SF = 0, CF = 1 , AF = 0, OF = 1
ZF = 0, SF = 1, CF = 0, AF =0 , OF = 1
4. If the processor uses even parity and after an arithmetic operation the value of the flags are
ZF = 0, SF = 1, CF = 1, OF = 0 and PF = 0. The possible result in the destination register is
A.
B.
C.
D.
1111 1111
0000 1111
1001 1001
1000 0000
5. Given the data declaration as
word1
WORD
1000h, 2000h, 3000h, 4000h, 5000h
What is the final value of AX after these codes have been executed?
A.
B.
C.
D.
8040h
9040h
4020h
3020h
L1:
mov
mov
mov
mov
add
sub
Loop
edx,OFFSET word1+8
ecx,2
ax,0
ax,[edx]
ax,20h
edx,4
L1
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6. Which CALL statement will display a signed 32 bit integer to a standard output?
A.
B.
C.
D.
call WriteString
call WriteChar
call WriteOct
call WriteInt
7. What does the following codes do?
call
mov
call
call
A.
B.
C.
D.
Clrscr
ax,500
Delay
DumpRegs
Refresh screen, delay program for 500 microseconds, dump flags
Clear screen, delay program for 500 milliseconds, dump registers and flags
Clear screen, delay program for 500 seconds, dump flags
Refresh screen, delay programs for 500 seconds, dump registers
8. Which library routine is used to generate a pseudorandom integer within a specified range?
A.
B.
C.
D.
RandomInt32
GenerateRand
PseudoRand
RandomRange
9. All of the following are elements of instruction EXCEPT:
A.
B.
C.
D.
destination counter
operation code/mnemonic
source operand
destination operand
10. All of the following are addressing modes EXCEPT:
A.
B.
C.
D.
displacement
indirect
direct
operand forwarding
11. Given the instruction MOV AX,[[ESI]] what kind of addressing mode does the
instruction use?
A. Immediate
B. Stack
C. Register indirect
D. Displacement
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12. Given a simple instruction format as follows, how many operation codes (opcodes)
are allowed for this ISA?
Opcode (8 bits)
A.
B.
C.
D.
Operand
bits)
Reference
(12 Operand
bits)
Reference
4096
256
255
128
13. Which one of the following is NOT a user visible register?
A. Control register
B. General purpose register
C. Data register
D. Address register
14. All the followings are the causes for interrupts EXCEPT:
A.
B.
C.
D.
program
timer
hardware failure
CPU performance
15. Select the CORRECT sequence of instruction cycle.
A. Indirect cycle, fetch cycle, execute cycle, interrupt cycle
B. Execute cycle, fetch cycle, interrupt cycle, indirect cycle
C. Fetch cycle, indirect cycle, execute cycle, interrupt cycle
D. Fetch cycle, interrupt cycle, indirect cycle, execute cycle
16. Select the CORRECT statement for Control Unit operations.
A. Generate control signals and transfer them to related components using the
registers.
B. Synchronize all activities in the computer based on the timing of the clock.
C. Control and manage all data transfer between memory and I/O only.
D. Executes instruction by generating registers based on the control signal.
17. Choose the CORRECT statement regarding pipeline.
A.
B.
C.
D.
A single task is divided into several small independent tasks.
It can be done by executing only one task at a time.
It decreases the performance of the CPU.
It has to wait for the previous instruction to finish before processing the new
instruction.
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18. Which technique is NOT a solution to data dependencies in pipeline?
A.
B.
C.
D.
Hardware interlocks
Instruction queue
Operand forwarding
Delayed load
19. ________ occurs when two segment in a pipeline need to access memory at the same time.
A.
B.
C.
D.
Loop buffer
Conflict of resources
Instruction address calculation
Operand prefetch
20. When the compiler detects a branch, it will automatically insert several _____ so that there is
no interruption in the pipeline.
A.
B.
C.
D.
JMP
RET
NOP
MOV
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SCR 1043
TEST II
SEMESTER II 2008/2009
PART A : ANSWER SHEET
Name
Section
Lecturer
Mark your answer clearly.
Example: =A=
=B= =C=
=D=
1.
=A=
=B=
=C=
=D=
11.
=A=
=B=
=C=
=D=
2.
=A=
=B=
=C=
=D=
12.
=A=
=B=
=C=
=D=
3.
=A=
=B=
=C=
=D=
13.
=A=
=B=
=C=
=D=
4.
=A=
=B=
=C=
=D=
14.
=A=
=B=
=C=
=D=
5.
=A=
=B=
=C=
=D=
15.
=A=
=B=
=C=
=D=
6.
=A=
=B=
=C=
=D=
16.
=A=
=B=
=C=
=D=
7.
=A=
=B=
=C=
=D=
17.
=A=
=B=
=C=
=D=
8.
=A=
=B=
=C=
=D=
18.
=A=
=B=
=C=
=D=
9.
=A=
=B=
=C=
=D=
19.
=A=
=B=
=C=
=D=
10.
=A=
=B=
=C=
=D=
20.
=A=
=B=
=C=
=D=
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SCR 1043
Part B: Structured Questions [70 marks]
Question 1 [15 marks]
a) Given a partial program as follows, write all the arithmetic equations in terms of value1, value2,
value3, value4 and total in the blank spaces below.
[9 marks]
:
mov EAX,0
mov EBX,0
mov AX,value1
add AX,value2
;AX=______________________________________________________
mov BX,value3
sub BX,value4
;BX=______________________________________________________
neg BX
;BX=______________________________________________________
add AX,BX
;AX=______________________________________________________
inc AX
;AX=_______________________________________________________
mov Total,AX
;Total=_____________________________________________________
:
b) Fill in the blanks with the appropriate data type and call function that can be used in the program
in order to obtain the given output. You may refer to the data types and call functions given below.
[6 marks]
ReadHex
ReadDec
WriteChar
DumpMem
ReadChar
WriteBin
WriteString Clrscr
ReadInt
WriteDec WriteHex
Crlf
ReadString WriteInt
DumpRegs
GetCommandtail
Word
Qword
Dword
Byte
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SCR 1043
INCLUDE Irvine32.inc
.data
string1 byte "Integer Number Representation (32 bits):",0
IntValue
________________ 2000
.code
main PROC
call Crlf
mov
edx,OFFSET string1
call
______
_
_______
call Crlf
call Crlf
mov
eax,IntValue
call
_____
_________
call Crlf
call
mov
___________
_____
eax,IntValue
call
____
_________
______
________
call Crlf
call Crlf
mov
eax,IntValue
call
call Crlf
call Crlf
exit
main ENDP
END main
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SCR 1043
Question 2 [15 marks]
a)
An assembly program is given as follows.
.data
intArray
DWORD
.code
main proc
mov
mov
mov
again:
add
add
intArray
loop
1000, 200, 3000, 5000
; declaration of intArray
esi,OFFSET
intArray
ecx,LENGTHOF intArray
eax,0
eax,[esi]
esi,TYPE intArray
;
;
;
;
;
address of intArray in ESI
set counter ECX
set accumulator EAX to 0
add number to accumulator
point to next number in
again
; loop to label again until ECX
; = 0
exit
main endp
end main
Questions:
i. What is the initial value of the register ECX?
[1 mark]
ii. If the value of OFFSET intArray is 404000h, show the addresses associated with each
number in intArray
[2 marks]
Number in intArray
Address
1000
200
3000
5000
iii. What is the value added to register ESI for the instruction: add esi, TYPE intArray?
[1 mark]
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iv. Find the final value stored in register EAX in hexadecimal. Show the value for each loop
cycle.
[6 marks]
Loop
Value in EAX register
b) The aim of this program is to sum the numbers in array table. However, the program contains
errors.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
i.
.data
table WORD
10,20,30,40,50,60,70,80,90,100
.code
main
proc
mov ax,0
mov cx,10
mov esi, OFFSET table
again:
add ax,[esi]
sub esi,2
inc cx
loop again
exit
main
endp
end
main
Can the loop in the program be executed properly?
[1 mark]
ii. State the line numbers that are creating the problem.
[2 marks]
iii. Correct the related instructions so the loop can be executed properly.
[2 marks]
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SCR 1043
Question 3 [10 marks]
(a) Given the following register and memory values and a one address instruction with an
accumulator, determine the EFFECTIVE ADDRESS (EA) and the OPERAND to be loaded
for the following address modes:
[6 marks]
Addressing Modes
Effective Address
Operand
LOAD DIRECT 600
LOAD INDIRECT 700
LOAD REGISTER INDIRECT R1
(b) A new simple machine has the following general instruction format:
Opcode
Operand 1
Operand 2
It is in fixed length format with an 18-bit instruction length. The Opcode occupies 3 bits.
Operand 1 may specify one of the 32 general purpose registers. Operand 2 can be used as a
memory address.
i.
How many instructions are allowed for this ISA?
[1mark]
ii.
How many bits are needed for Operand 1?
[1mark]
iii.
What is the maximum directly addressable memory capacity?
[2marks]
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SCR 1043
Question 4 [15 marks]
(a) Fill in the blanks using RTL (register transfer language) for the fetch cycle.
[3marks]
MAR  ______________
t1:
t2:
_________________
 [MAR]
IP/PC  IP/PC + 1
t3:
_________________
 MBR
(b) Complete the values for i to xii for the execution of instructions in table below by showing all the
changes in CPU registers (control and general purpose registers). The initial values for execution of
each instruction are given.
[12 marks]
Memory address
Memory Content
Instruction
400:
5410
ADD DX, VAL1
401:
4CD0
SUB DX,CX
100
VAL1
402:
410:
Clock
IP/PC
MAR
MBR
IR
CX
DX
t0
400
-
-
-
50
0
t1
t2
i.
ii.
iii.
t3
iv.
t4
v.
t5
vi.
t6
vii.
t7
401
t8
t9
t10
-
-
-
viii.
ix.
x.
xi.
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SCR 1043
t11
xii.
Question 5 [15 marks]
A pipeline processor has 5 segments. Its interface delay is 2 ns and the segment
execution time is shown in the table below.
Segment Name
Fetch Instruction (FI)
Decode Instruction (DI)
Fetch Operand (FO)
Execute Instruction (EI)
Store Operand (SO)
Segment Execution Time (ns)
10
8
10
10
7
a) What is the pipeline cycle time (execution delay time), tp ?
b) What is the maximum speedup, Smax?
[1 mark]
[1 mark]
c) Determine the real speedup for:
i. 100 instructions
[2 marks]
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ii. 20,000 instructions
[2 marks]
iii. From your answers in c(i) and c(ii), what is the effect of the speedup with
respect to the number of instructions?
[1 mark]
d) Based on the assembly coding below, draw the space time diagram to determine the
occurrence (based on unit time) of data dependency in the pipeline. CIRCLE your
answer on the particular location/box.
MOV
edi,offset num1
INC edi
ADD dx,[edi]
Time
Segment
[2 marks]
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e) The line numbers of an assembly program is given as follows:
I1
I2
:
I29
:
I31
JMP
L1
:
I73 L1:
The opcode of instruction I31 is a unconditional branch (JMP) that jump to instruction I73.
Fill the space time diagram to show the instruction execution starting with instruction I29.
Show the instruction(s) that will be flushed from the pipeline.
[3 marks]
Time
Segment
f) Solve the problem 5(e) by applying the rearrangement of instructions technique. Explain
with a space time diagram.
[3 marks]
Time
Segment
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