Faculty: FACULTY OF ELECTRICAL ENGINEERING
Subject : ELECTRICAL ENGINEERING
LABORATORY
Subject Code : SKEL 3742
Review
Release Date
Last Amendment
Procedure Number
:
: 9 February 2014
: 9 February 2014
:
Prepared by :
Name: 1) Ismahani Binti Ismail
2) Izam Bin Kamisian
Signature & Stamp :
Date:
Approved by: Head of Department
Name: Dr. Nasir Bin Shaikh Husin
Signature & Stamp:
Date:
© 2014 Universiti Teknologi Malaysia – All Rights Reserved

A simple calculator, such as the one found in every computer, is the basis of many software and hardware projects. Within a microprocessor this is called an arithmetic logic unit (ALU). The most basic operations are AND, OR, NOT, XOR and (unsigned) ADD. Modern microprocessors extend this with multiply, divide and barrel shift operations (high speed shifting of an arbitrary number of bits).
The objectives of this project are:
1.
To design the combinational logic circuit of the calculator using bit slice technique and use register to store data.
2.
To draw the combinational logic circuit of the calculator using schematic design entry and verify its function using Altera Quartus II Tools software.
3.
To prototype and demonstrate the combinational logic of calculator using Altera FPGA DE2 board.
In this lab, you are required to design a simple 8-bit calculator with the addition of one 8-bit register based on the descriptions as shown in the Appendix A. To develop your calculator, choose four arithmetic and four logical operations from the appendix. Your calculator should be able to store numbers from a previous operation and perform more complex operations, like a typical calculator, and have only one number input at a time. Mathematic operations are performed using the value in the register as one operand and the “input” value as the other operand. The operations performed by the ALU will depend on the state of the control bits in the control signal.
Identify inputs and outputs of your system, encoding and decoding method, circuit topology and suitable algorithm to be used. Design the system and verify its function using
Quartus II CAD Tools. Final task is to prototype and demonstrate your system using DE2 FPGA board. Refer to Quartus II and DE2 FPGA tutorials to help you to implement this project.
For the first session of your lab, write a proposal about the project containing system block diagram and a design methodology to implement the system. Finally, a report with the well presented design steps, simulation results and FPGA prototyping methodology are expected to be produced at the end of the project after the second session of the lab.
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Design the calculator with the description as shown below:
Table of Operations and signals:
Arithmetic Operation Description
A + B A plus B
A - B
A + 1
A minus B
A plus 1
Logical Operation
A AND B
A OR B
A XOR B
B + 1
A - 1
B - 1
B - A
A + B + 1
A - B - 1
B plus 1
A minus 1
B minus 1
B minus A
A plus B plus 1
A XNOR B
NOT A
NOT B
(NOT A) NAND B
A NOR (NOT B)
A minus B minus 1 NOT (A AND B)
Signal
KEY3 Clock input for registering the calculation
Ctrl
A
Description
3-bit control signal
Data input
LEDR0 Overflow output from add/subtract operation
LEDG0 If A equal B
KEY0 Circuit reset
Signal Display
Calculation display HEX1, HEX0 (each is 4-bit output)
Input A display HEX5, HEX4 (each is 4-bit output)
Design guidelines:
1.
Design the basic circuit using two primary inputs A and B.
2.
Replace the B input with the 8-bit register. The addition of the 8-bit register enables storage of the result of any ALU operation. It also serves as the B input.
3. A binary adder can be easily adapted to perform both addition and subtraction of 2’s complement numbers.
4. The A input will be eventually connected to the toggle switches on the DE2 board.
5. The clock, overflow, equal and reset signals will be eventually connected to the KEY3 pushbutton, red LED (LEDR0), green LED (LEDG0) and KEY0 pushbutton on the DE2 board.
6. The 3-bit control signal (Ctrl) will be eventually connected to three toggle switches on the
DE2 board.
7. The input A and outputs from the calculator will be eventually displayed on the 7-segment displays on the DE2 board.
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